Trying to access the vpiPort of the DUT

[r2com]

So let's say I have simple DUT in VHDL which has top ports a,b,c,d and inside entity there are signals e,f,g,h.

consider the below routine I have:

static PLI_INT32 get_handles2(p_cb_data data)
{
  vpiHandle iter, net;
      const char *net_name;
    int         net_width;
    int         net_dir;

    h_module_iter = vpi_iterate(vpiModule, NULL);
    h_top = vpi_scan(h_module_iter);
    vpi_free_object(h_module_iter);
    printf("Top-level module: %s\n", vpi_get_str(vpiFullName, h_top));

    iter = vpi_iterate(vpiPort, h_top);
    if (iter) {
        while ((net = vpi_scan(iter)) != NULL) {
            printf(" port/net found!\n");
            net_name = vpi_get_str(vpiName, net);
            net_width = vpi_get(vpiSize, net);
            net_dir = vpi_get(vpiDirection, net);
          }
        }
return 0;
}

When I have vpiPort in the "iter = vpi_iterate(vpiPort, h_top);" then I do not get print statement that port/net is found.

However, when I change vpiPort to vpiNet, it will give me that print statement 8 times, basically, it found 4 ports (top entity ports) and another 4 signals inside entity.

So, my question is, does it mean that there is no support for explicitly identifying the PORTS of the VHDL DUT? for example, what if I don't care about any signals in my VHDL entity but just want to read all ports of the entity and drive/read them during verification?