diff --git a/po/es.po b/po/es.po index d1638072031..f259c4b23ac 100644 --- a/po/es.po +++ b/po/es.po @@ -1,7 +1,7 @@ msgid "" msgstr "" "Project-Id-Version: Comprehensive Rust 馃\n" -"POT-Creation-Date: 2024-01-24T15:37:30-08:00\n" +"POT-Creation-Date: 2024-01-25T15:03:24-08:00\n" "PO-Revision-Date: \n" "Last-Translator: \n" "Language-Team: \n" @@ -17771,14 +17771,18 @@ msgstr "" msgid "" "// Safe because `HEAP` is only used here and `entry` is only called once.\n" msgstr "" +"// Es seguro porque `HEAP` solo se usa aqu铆 y solo se llama una vez a " +"`entry`.\n" #: src/bare-metal/alloc.md msgid "// Give the allocator some memory to allocate.\n" -msgstr "" +msgstr "// Proporciona al asignador algo de memoria para asignar.\n" #: src/bare-metal/alloc.md msgid "// Now we can do things that require heap allocation.\n" msgstr "" +"// Ahora podemos llevar a cabo acciones que requieran la asignaci贸n de " +"mont铆culo.\n" #: src/bare-metal/alloc.md #, fuzzy @@ -17867,33 +17871,36 @@ msgstr "" #: src/bare-metal/microcontrollers/mmio.md msgid "/// GPIO port 0 peripheral address\n" -msgstr "" +msgstr "/// Direcci贸n de perif茅rico del puerto GPIO 0\n" #: src/bare-metal/microcontrollers/mmio.md msgid "// GPIO peripheral offsets\n" -msgstr "" +msgstr "// Offset de perif茅ricos GPIO\n" #: src/bare-metal/microcontrollers/mmio.md msgid "// PIN_CNF fields\n" -msgstr "" +msgstr "// Campos PIN_CNF\n" #: src/bare-metal/microcontrollers/mmio.md #: src/bare-metal/microcontrollers/pacs.md #: src/bare-metal/microcontrollers/hals.md msgid "// Configure GPIO 0 pins 21 and 28 as push-pull outputs.\n" -msgstr "" +msgstr "// Configura los pines 21 y 28 de GPIO 0 como salidas push-pull.\n" #: src/bare-metal/microcontrollers/mmio.md msgid "" "// Safe because the pointers are to valid peripheral control registers, and\n" " // no aliases exist.\n" msgstr "" +"// Es seguro porque los punteros dirigen a registros de control de " +"perif茅ricos v谩lidos y\n" +" // no existe ning煤n alias.\n" #: src/bare-metal/microcontrollers/mmio.md #: src/bare-metal/microcontrollers/pacs.md #: src/bare-metal/microcontrollers/hals.md msgid "// Set pin 28 low and pin 21 high to turn the LED on.\n" -msgstr "" +msgstr "// Define el pin 28 bajo y 21 alto para encender el LED.\n" #: src/bare-metal/microcontrollers/mmio.md msgid "" @@ -17982,7 +17989,7 @@ msgstr "" #: src/bare-metal/microcontrollers/hals.md msgid "// Create HAL wrapper for GPIO port 0.\n" -msgstr "" +msgstr "// Crea un envoltorio HAL para el puerto GPIO 0.\n" #: src/bare-metal/microcontrollers/hals.md msgid "" @@ -18036,11 +18043,11 @@ msgstr "El patr贸n de tipo de estado" #: src/bare-metal/microcontrollers/type-state.md msgid "// let gpio0_01_again = gpio0.p0_01; // Error, moved.\n" -msgstr "" +msgstr "// let gpio0_01_again = gpio0.p0_01; // Error, se ha movido.\n" #: src/bare-metal/microcontrollers/type-state.md msgid "// pin_input.is_high(); // Error, moved.\n" -msgstr "" +msgstr "// pin_input.is_high(); // Error, se ha movido.\n" #: src/bare-metal/microcontrollers/type-state.md msgid "" @@ -18162,6 +18169,8 @@ msgstr " y JTAG a trav茅s de comprobaciones CMSIS-DAP, ST-Link y J-Link" #: src/bare-metal/microcontrollers/probe-rs.md msgid "GDB stub and Microsoft DAP (Debug Adapter Protocol) server" msgstr "" +"Stub de GDB y servidor de Microsoft DAP (protocolo de adaptador de " +"depuraci贸n)" #: src/bare-metal/microcontrollers/probe-rs.md msgid "Cargo integration" @@ -18251,7 +18260,7 @@ msgstr "En otro terminal del mismo directorio:" #: src/bare-metal/microcontrollers/debugging.md msgid "On gLinux or Debian:" -msgstr "" +msgstr "En gLinux o Debian:" #: src/bare-metal/microcontrollers/debugging.md msgid "In GDB, try running:" @@ -18457,29 +18466,33 @@ msgstr "`src/main.rs`:" #: src/exercises/bare-metal/compass.md #: src/exercises/bare-metal/solutions-morning.md msgid "// Configure serial port.\n" -msgstr "" +msgstr "// Configura el puerto serie.\n" #: src/exercises/bare-metal/compass.md #: src/exercises/bare-metal/solutions-morning.md msgid "// Use the system timer as a delay provider.\n" -msgstr "" +msgstr "// Usa el temporizador del sistema como proveedor de retrasos.\n" #: src/exercises/bare-metal/compass.md msgid "" "// Set up the I2C controller and Inertial Measurement Unit.\n" " // TODO\n" msgstr "" +"// Configura el controlador I2C y la unidad de medici贸n inercial.\n" +" // TAREA\n" #: src/exercises/bare-metal/compass.md #: src/exercises/bare-metal/solutions-morning.md msgid "\"Ready.\"" -msgstr "" +msgstr "\"Listo.\"" #: src/exercises/bare-metal/compass.md msgid "" "// Read compass data and log it to the serial port.\n" " // TODO\n" msgstr "" +"// Lee datos de la br煤jula y reg铆stralos en el puerto serie.\n" +" // TAREA\n" #: src/exercises/bare-metal/compass.md src/exercises/bare-metal/rtc.md #, fuzzy @@ -18521,23 +18534,23 @@ msgstr "([volver al ejercicio](compass.md))" #: src/exercises/bare-metal/solutions-morning.md msgid "// Set up the I2C controller and Inertial Measurement Unit.\n" -msgstr "" +msgstr "// Configura el controlador de I2C y la unidad de medici贸n inercial.\n" #: src/exercises/bare-metal/solutions-morning.md msgid "\"Setting up IMU...\"" -msgstr "" +msgstr "\"Configurando IMU...\"" #: src/exercises/bare-metal/solutions-morning.md msgid "// Set up display and timer.\n" -msgstr "" +msgstr "// Configura la pantalla y el temporizador.\n" #: src/exercises/bare-metal/solutions-morning.md msgid "// Read compass data and log it to the serial port.\n" -msgstr "" +msgstr "// Lee los datos de la br煤jula y reg铆stralos en el puerto serie.\n" #: src/exercises/bare-metal/solutions-morning.md msgid "\"{},{},{}\\t{},{},{}\"" -msgstr "" +msgstr "\"{},{},{}\\t{},{},{}\"" #: src/exercises/bare-metal/solutions-morning.md msgid "" @@ -18545,6 +18558,9 @@ msgid "" "LEDs\n" " // on.\n" msgstr "" +"// Si se pulsa el bot贸n A, cambia al siguiente modo y haz que parpadeen " +"brevemente todos los LED\n" +" // activados.\n" #: src/bare-metal/aps.md msgid "Application processors" @@ -18664,6 +18680,78 @@ msgid "" " b 2b\n" "```" msgstr "" +"```armasm\n" +".section .init.entry, \"ax\"\n" +".global entry\n" +"entry:\n" +" /*\n" +" * Load and apply the memory management configuration, ready to enable " +"MMU and\n" +" * caches.\n" +" */\n" +" adrp x30, idmap\n" +" msr ttbr0_el1, x30\n" +"\n" +" mov_i x30, .Lmairval\n" +" msr mair_el1, x30\n" +"\n" +" mov_i x30, .Ltcrval\n" +" /* Copy the supported PA range into TCR_EL1.IPS. */\n" +" mrs x29, id_aa64mmfr0_el1\n" +" bfi x30, x29, #32, #4\n" +"\n" +" msr tcr_el1, x30\n" +"\n" +" mov_i x30, .Lsctlrval\n" +"\n" +" /*\n" +" * Ensure everything before this point has completed, then invalidate " +"any\n" +" * potentially stale local TLB entries before they start being used.\n" +" */\n" +" isb\n" +" tlbi vmalle1\n" +" ic iallu\n" +" dsb nsh\n" +" isb\n" +"\n" +" /*\n" +" * Configure sctlr_el1 to enable MMU and cache and don't proceed until " +"this\n" +" * has completed.\n" +" */\n" +" msr sctlr_el1, x30\n" +" isb\n" +"\n" +" /* Disable trapping floating point access in EL1. */\n" +" mrs x30, cpacr_el1\n" +" orr x30, x30, #(0x3 << 20)\n" +" msr cpacr_el1, x30\n" +" isb\n" +"\n" +" /* Zero out the bss section. */\n" +" adr_l x29, bss_begin\n" +" adr_l x30, bss_end\n" +"0: cmp x29, x30\n" +" b.hs 1f\n" +" stp xzr, xzr, [x29], #16\n" +" b 0b\n" +"\n" +"1: /* Prepare the stack. */\n" +" adr_l x30, boot_stack_end\n" +" mov sp, x30\n" +"\n" +" /* Set up exception vector. */\n" +" adr x30, vector_table_el1\n" +" msr vbar_el1, x30\n" +"\n" +" /* Call into Rust code. */\n" +" bl main\n" +"\n" +" /* Loop forever waiting for interrupts. */\n" +"2: wfi\n" +" b 2b\n" +"```" #: src/bare-metal/aps/entry-point.md msgid "" @@ -18783,42 +18871,44 @@ msgid "" "// Safe because this only uses the declared registers and doesn't do\n" " // anything with memory.\n" msgstr "" +"// Es seguro porque solo utiliza los registros declarados y no\n" +" // hace nada con la memoria.\n" #: src/bare-metal/aps/inline-assembly.md msgid "\"hvc #0\"" -msgstr "" +msgstr "\"hvc #0\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w0\"" -msgstr "" +msgstr "\"w0\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w1\"" -msgstr "" +msgstr "\"w1\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w2\"" -msgstr "" +msgstr "\"w2\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w3\"" -msgstr "" +msgstr "\"w3\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w4\"" -msgstr "" +msgstr "\"w4\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w5\"" -msgstr "" +msgstr "\"w5\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w6\"" -msgstr "" +msgstr "\"w6\"" #: src/bare-metal/aps/inline-assembly.md msgid "\"w7\"" -msgstr "" +msgstr "\"w7\"" #: src/bare-metal/aps/inline-assembly.md msgid "" @@ -18956,7 +19046,7 @@ msgstr "" #: src/bare-metal/aps/uart.md msgid "/// Minimal driver for a PL011 UART.\n" -msgstr "" +msgstr "/// Controlador m铆nimo para un UART PL011.\n" #: src/bare-metal/aps/uart.md src/bare-metal/aps/better-uart/driver.md msgid "" @@ -18971,32 +19061,46 @@ msgid "" "process\n" " /// as device memory and not have any other aliases.\n" msgstr "" +"/// Construye una instancia nueva del controlador de UART para un " +"dispositivo PL011 en la\n" +" /// direcci贸n base proporcionada.\n" +" ///\n" +" /// # Seguridad\n" +" ///\n" +" /// La direcci贸n base debe apuntar a los 8 registros de control MMIO de " +"un \n" +" /// dispositivo PL011, que debe asignarse al espacio de direcciones del " +"proceso\n" +" /// como memoria del dispositivo y no tener ning煤n otro alias.\n" #: src/bare-metal/aps/uart.md src/bare-metal/aps/better-uart/driver.md #: src/exercises/bare-metal/rtc.md msgid "/// Writes a single byte to the UART.\n" -msgstr "" +msgstr "/// Escribe un solo byte en el UART.\n" #: src/bare-metal/aps/uart.md src/bare-metal/aps/better-uart/driver.md #: src/exercises/bare-metal/rtc.md msgid "// Wait until there is room in the TX buffer.\n" -msgstr "" +msgstr "// Espera hasta que haya espacio en el b煤fer de TX.\n" #: src/bare-metal/aps/uart.md msgid "" "// Safe because we know that the base address points to the control\n" " // registers of a PL011 device which is appropriately mapped.\n" msgstr "" +"// Es seguro porque sabemos que la direcci贸n base apunta a los registros\n" +" // de control de un dispositivo PL011 que est谩 asignado " +"correctamente.\n" #: src/bare-metal/aps/uart.md src/bare-metal/aps/better-uart/driver.md #: src/exercises/bare-metal/rtc.md msgid "// Write to the TX buffer.\n" -msgstr "" +msgstr "// Escribe en el b煤fer de TX.\n" #: src/bare-metal/aps/uart.md src/bare-metal/aps/better-uart/driver.md #: src/exercises/bare-metal/rtc.md msgid "// Wait until the UART is no longer busy.\n" -msgstr "" +msgstr "// Espera hasta que el UART est茅 libre.\n" #: src/bare-metal/aps/uart.md msgid "" @@ -19053,6 +19157,8 @@ msgid "" "// Safe because it just contains a pointer to device memory, which can be\n" "// accessed from any context.\n" msgstr "" +"// Es seguro porque solo contiene un puntero a la memoria del dispositivo,\n" +"// a la que se puede acceder desde cualquier contexto.\n" #: src/bare-metal/aps/uart/traits.md msgid "" @@ -19242,43 +19348,43 @@ msgstr "" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Flags from the UART flag register.\n" -msgstr "" +msgstr "/// Marcas del registro de marcas de UART.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Clear to send.\n" -msgstr "" +msgstr "/// Borra para enviar.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Data set ready.\n" -msgstr "" +msgstr "/// Conjunto de datos listo.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Data carrier detect.\n" -msgstr "" +msgstr "/// Detecci贸n del portador de datos.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// UART busy transmitting data.\n" -msgstr "" +msgstr "/// UART est谩 transmitiendo datos.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Receive FIFO is empty.\n" -msgstr "" +msgstr "/// El FIFO de recepci贸n est谩 vac铆o\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Transmit FIFO is full.\n" -msgstr "" +msgstr "/// El FIFO de transmisi贸n est谩 completo.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Receive FIFO is full.\n" -msgstr "" +msgstr "/// El FIFO de recepci贸n est谩 completo.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Transmit FIFO is empty.\n" -msgstr "" +msgstr "/// El FIFO de transmisi贸n est谩 vac铆o.\n" #: src/bare-metal/aps/better-uart/bitflags.md src/exercises/bare-metal/rtc.md msgid "/// Ring indicator.\n" -msgstr "" +msgstr "/// Indicador de anillo.\n" #: src/bare-metal/aps/better-uart/bitflags.md msgid "" @@ -19322,23 +19428,28 @@ msgstr "" #: src/bare-metal/aps/better-uart/driver.md msgid "/// Driver for a PL011 UART.\n" -msgstr "" +msgstr "/// Controlador para un UART PL011.\n" #: src/bare-metal/aps/better-uart/driver.md src/exercises/bare-metal/rtc.md msgid "" "// Safe because we know that self.registers points to the control\n" " // registers of a PL011 device which is appropriately mapped.\n" msgstr "" +"// Es seguro porque sabemos que self.registers apunta\n" +" // a los registros de control de un dispositivo PL011 que est谩 " +"asignado correctamente.\n" #: src/bare-metal/aps/better-uart/driver.md src/exercises/bare-metal/rtc.md msgid "" "/// Reads and returns a pending byte, or `None` if nothing has been\n" " /// received.\n" msgstr "" +"/// Lee y devuelve un byte pendiente o `None` si no se ha recibido nada\n" +" ///.\n" #: src/bare-metal/aps/better-uart/driver.md src/exercises/bare-metal/rtc.md msgid "// TODO: Check for error conditions in bits 8-11.\n" -msgstr "" +msgstr "// TAREA: Comprueba si hay condiciones de error en los bits 8 a 11.\n" #: src/bare-metal/aps/better-uart/driver.md msgid "" @@ -19365,7 +19476,7 @@ msgstr "" #: src/exercises/bare-metal/rtc.md #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Base address of the primary PL011 UART.\n" -msgstr "" +msgstr "/// Direcci贸n base del UART de PL011 principal.\n" #: src/bare-metal/aps/better-uart/using.md src/bare-metal/aps/logging/using.md #: src/exercises/bare-metal/rtc.md @@ -19374,26 +19485,29 @@ msgid "" "// Safe because `PL011_BASE_ADDRESS` is the base address of a PL011 device,\n" " // and nothing else accesses that address range.\n" msgstr "" +"// Es seguro porque `PL011_BASE_ADDRESS` es la direcci贸n base de un " +"dispositivo PL011\n" +" // y ninguna m谩s accede a ese intervalo de direcciones.\n" #: src/bare-metal/aps/better-uart/using.md src/bare-metal/aps/logging/using.md msgid "\"main({x0:#x}, {x1:#x}, {x2:#x}, {x3:#x})\"" -msgstr "" +msgstr "\"main({x0:#x}, {x1:#x}, {x2:#x}, {x3:#x})\"" #: src/bare-metal/aps/better-uart/using.md msgid "b'\\r'" -msgstr "" +msgstr "b'\\r'" #: src/bare-metal/aps/better-uart/using.md src/async/pitfalls/cancellation.md msgid "b'\\n'" -msgstr "" +msgstr "b'\\n'" #: src/bare-metal/aps/better-uart/using.md msgid "b'q'" -msgstr "" +msgstr "b'q'" #: src/bare-metal/aps/better-uart/using.md msgid "\"Bye!\"" -msgstr "" +msgstr "\"隆Adi贸s!\"" #: src/bare-metal/aps/better-uart/using.md msgid "" @@ -19422,11 +19536,11 @@ msgstr "" #: src/bare-metal/aps/logging.md src/exercises/bare-metal/rtc.md msgid "\"[{}] {}\"" -msgstr "" +msgstr "\"[{}] {}\"" #: src/bare-metal/aps/logging.md src/exercises/bare-metal/rtc.md msgid "/// Initialises UART logger.\n" -msgstr "" +msgstr "/// Inicia el registro de UART.\n" #: src/bare-metal/aps/logging.md msgid "" @@ -19443,7 +19557,7 @@ msgstr "Debemos inicializar el registrador antes de utilizarlo." #: src/bare-metal/aps/logging/using.md src/exercises/bare-metal/rtc.md #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"{info}\"" -msgstr "" +msgstr "\"{info}\"" #: src/bare-metal/aps/logging/using.md msgid "Note that our panic handler can now log details of panics." @@ -19683,15 +19797,15 @@ msgstr "" #: src/bare-metal/useful-crates/aarch64-paging.md msgid "// Create a new page table with identity mapping.\n" -msgstr "" +msgstr "// Crea una tabla de p谩ginas con mapeado de identidades.\n" #: src/bare-metal/useful-crates/aarch64-paging.md msgid "// Map a 2 MiB region of memory as read-only.\n" -msgstr "" +msgstr "// Asigna una regi贸n de 2 MiB de memoria como de solo lectura.\n" #: src/bare-metal/useful-crates/aarch64-paging.md msgid "// Set `TTBR0_EL1` to activate the page table.\n" -msgstr "" +msgstr "// Configura `TTBR0_EL1` para activar la tabla de p谩ginas.\n" #: src/bare-metal/useful-crates/aarch64-paging.md msgid "" @@ -19970,12 +20084,12 @@ msgstr "" #: src/exercises/bare-metal/rtc.md #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Base addresses of the GICv3.\n" -msgstr "" +msgstr "/// Direcciones base de GICv3.\n" #: src/exercises/bare-metal/rtc.md #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"main({:#x}, {:#x}, {:#x}, {:#x})\"" -msgstr "" +msgstr "\"main({:#x}, {:#x}, {:#x}, {:#x})\"" #: src/exercises/bare-metal/rtc.md #: src/exercises/bare-metal/solutions-afternoon.md @@ -19984,14 +20098,21 @@ msgid "" " // addresses of a GICv3 distributor and redistributor respectively, and\n" " // nothing else accesses those address ranges.\n" msgstr "" +"// Es seguro porque `GICD_BASE_ADDRESS` y `GICR_BASE_ADDRESS` son las " +"direcciones base\n" +" // de un distribuidor y un redistribuidor GICv3 respectivamente,\n" +" // y ning煤n otro elemento tiene acceso a esos intervalos de " +"direcciones.\n" #: src/exercises/bare-metal/rtc.md msgid "// TODO: Create instance of RTC driver and print current time.\n" msgstr "" +"// TAREA: crear una instancia del controlador RTC e imprimir la hora " +"actual.\n" #: src/exercises/bare-metal/rtc.md msgid "// TODO: Wait for 3 seconds.\n" -msgstr "" +msgstr "// TAREA: esperar 3 segundos.\n" #: src/exercises/bare-metal/rtc.md #, fuzzy @@ -20018,103 +20139,121 @@ msgid "" "// See the License for the specific language governing permissions and\n" "// limitations under the License.\n" msgstr "" +"// Copyright 2023 Google LLC\n" +"//\n" +"// Con licencia Apache, versi贸n 2.0 (la \"Licencia\");\n" +"// Este archivo solo se puede utilizar seg煤n lo estipulado en la Licencia.\n" +"// Puedes obtener una copia de la Licencia en\n" +"//\n" +"// http://www.apache.org/licenses/LICENSE-2.0\n" +"//\n" +"// Salvo que lo exija la legislaci贸n aplicable o se haya acordado por " +"escrito, el software\n" +"// distribuido bajo la Licencia se distribuye \"TAL CUAL\",\n" +"// SIN GARANT脥AS NI CONDICIONES DE NING脷N TIPO, ya sean expl铆citas o " +"impl铆citas.\n" +"// Consulta la Licencia para saber los permisos y las limitaciones " +"aplicables a cada idioma\n" +"//.\n" #: src/exercises/bare-metal/rtc.md msgid "\"sync_exception_current\"" -msgstr "" +msgstr "\"sync_exception_current\"" #: src/exercises/bare-metal/rtc.md msgid "\"irq_current\"" -msgstr "" +msgstr "\"irq_current\"" #: src/exercises/bare-metal/rtc.md msgid "\"No pending interrupt\"" -msgstr "" +msgstr "\"No hay interrupciones pendientes\"" #: src/exercises/bare-metal/rtc.md msgid "\"IRQ {intid:?}\"" -msgstr "" +msgstr "\"IRQ {intid:?}\"" #: src/exercises/bare-metal/rtc.md msgid "\"fiq_current\"" -msgstr "" +msgstr "\"fiq_current\"" #: src/exercises/bare-metal/rtc.md msgid "\"serr_current\"" -msgstr "" +msgstr "\"serr_current\"" #: src/exercises/bare-metal/rtc.md msgid "\"sync_lower\"" -msgstr "" +msgstr "\"sync_lower\"" #: src/exercises/bare-metal/rtc.md msgid "\"irq_lower\"" -msgstr "" +msgstr "\"irq_lower\"" #: src/exercises/bare-metal/rtc.md msgid "\"fiq_lower\"" -msgstr "" +msgstr "\"fiq_lower\"" #: src/exercises/bare-metal/rtc.md msgid "\"serr_lower\"" -msgstr "" +msgstr "\"serr_lower\"" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_src/logger.rs_ (you shouldn't need to change this):" -msgstr "`src/logger.rs` (no deber铆a ser necesario cambiarlo):" +msgstr "_src/logger.rs_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR: main\n" -msgstr "" +msgstr "// ANCHOR: main\n" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_src/pl011.rs_ (you shouldn't need to change this):" -msgstr "`src/pl011.rs` (no deber铆a ser necesario cambiarlo):" +msgstr "_src/pl011.rs_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR: Flags\n" -msgstr "" +msgstr "// ANCHOR: Flags\n" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR_END: Flags\n" -msgstr "" +msgstr "// ANCHOR_END: Flags\n" #: src/exercises/bare-metal/rtc.md msgid "" "/// Flags from the UART Receive Status Register / Error Clear Register.\n" msgstr "" +"/// Marcas del registro de estado de recepci贸n de UART/Registro de borrado " +"de errores.\n" #: src/exercises/bare-metal/rtc.md msgid "/// Framing error.\n" -msgstr "" +msgstr "/// Error de encuadre.\n" #: src/exercises/bare-metal/rtc.md msgid "/// Parity error.\n" -msgstr "" +msgstr "/// Error de paridad.\n" #: src/exercises/bare-metal/rtc.md msgid "/// Break error.\n" -msgstr "" +msgstr "/// Error de break.\n" #: src/exercises/bare-metal/rtc.md msgid "/// Overrun error.\n" -msgstr "" +msgstr "/// Error de desbordamiento.\n" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR: Registers\n" -msgstr "" +msgstr "// ANCHOR: Registers\n" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR_END: Registers\n" -msgstr "" +msgstr "// ANCHOR_END: Registers\n" #: src/exercises/bare-metal/rtc.md msgid "" "// ANCHOR: Uart\n" "/// Driver for a PL011 UART.\n" msgstr "" +"// ANCHOR: Uart\n" +"/// Controlador para un UART PL011.\n" #: src/exercises/bare-metal/rtc.md msgid "" @@ -20129,54 +20268,60 @@ msgid "" "process\n" " /// as device memory and not have any other aliases.\n" msgstr "" +"/// Crea una instancia nueva del controlador UART para un dispositivo PL011 " +"en la\n" +" /// direcci贸n base proporcionada.\n" +" ///\n" +" /// # Seguridad\n" +" ///\n" +" /// El objeto la direcci贸n base debe apuntar a los registros de control " +"MMIO de un dispositivo\n" +" /// PL011, que debe asignarse al espacio de direcciones del proceso\n" +" /// como memoria del dispositivo y no tener ning煤n otro alias.\n" #: src/exercises/bare-metal/rtc.md msgid "// ANCHOR_END: Uart\n" -msgstr "" +msgstr "// ANCHOR_END: Uart\n" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_build.rs_ (you shouldn't need to change this):" -msgstr "`build.rs` (no deber铆a ser necesario cambiarlo):" +msgstr "_build.rs_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "\"linux\"" -msgstr "" +msgstr "\"linux\"" #: src/exercises/bare-metal/rtc.md msgid "\"CROSS_COMPILE\"" -msgstr "" +msgstr "\"CROSS_COMPILE\"" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "\"aarch64-linux-gnu\"" -msgstr "aarch64-paging" +msgstr "\"aarch64-linux-gnu\"" #: src/exercises/bare-metal/rtc.md msgid "\"aarch64-none-elf\"" -msgstr "" +msgstr "\"aarch64-none-elf\"" #: src/exercises/bare-metal/rtc.md msgid "\"entry.S\"" -msgstr "" +msgstr "\"entry.S\"" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "\"exceptions.S\"" -msgstr "Excepciones" +msgstr "\"exceptions.S\"" #: src/exercises/bare-metal/rtc.md msgid "\"idmap.S\"" -msgstr "" +msgstr "\"idmap.S\"" #: src/exercises/bare-metal/rtc.md msgid "\"empty\"" -msgstr "" +msgstr "\"empty\"" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_entry.S_ (you shouldn't need to change this):" -msgstr "`entry.S` (no deber铆a ser necesario cambiarlo):" +msgstr "_entry.S_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "" @@ -20339,14 +20484,6 @@ msgid "" "\tb 2b\n" "```" msgstr "" - -#: src/exercises/bare-metal/rtc.md -#, fuzzy -msgid "_exceptions.S_ (you shouldn't need to change this):" -msgstr "`exceptions.S` (no deber铆a ser necesario cambiarlo):" - -#: src/exercises/bare-metal/rtc.md -msgid "" "```armasm\n" "/*\n" " * Copyright 2023 Google LLC\n" @@ -20364,77 +20501,433 @@ msgid "" " * limitations under the License.\n" " */\n" "\n" -"/**\n" -" * Saves the volatile registers onto the stack. This currently takes 14\n" -" * instructions, so it can be used in exception handlers with 18 " -"instructions\n" -" * left.\n" -" *\n" -" * On return, x0 and x1 are initialised to elr_el2 and spsr_el2 " -"respectively,\n" -" * which can be used as the first and second arguments of a subsequent " -"call.\n" -" */\n" -".macro save_volatile_to_stack\n" -"\t/* Reserve stack space and save registers x0-x18, x29 & x30. */\n" -"\tstp x0, x1, [sp, #-(8 * 24)]!\n" -"\tstp x2, x3, [sp, #8 * 2]\n" -"\tstp x4, x5, [sp, #8 * 4]\n" -"\tstp x6, x7, [sp, #8 * 6]\n" -"\tstp x8, x9, [sp, #8 * 8]\n" -"\tstp x10, x11, [sp, #8 * 10]\n" -"\tstp x12, x13, [sp, #8 * 12]\n" -"\tstp x14, x15, [sp, #8 * 14]\n" -"\tstp x16, x17, [sp, #8 * 16]\n" -"\tstr x18, [sp, #8 * 18]\n" -"\tstp x29, x30, [sp, #8 * 20]\n" -"\n" -"\t/*\n" -"\t * Save elr_el1 & spsr_el1. This such that we can take nested exception\n" -"\t * and still be able to unwind.\n" -"\t */\n" -"\tmrs x0, elr_el1\n" -"\tmrs x1, spsr_el1\n" -"\tstp x0, x1, [sp, #8 * 22]\n" +".macro adr_l, reg:req, sym:req\n" +"\tadrp \\reg, \\sym\n" +"\tadd \\reg, \\reg, :lo12:\\sym\n" ".endm\n" "\n" -"/**\n" -" * Restores the volatile registers from the stack. This currently takes 14\n" -" * instructions, so it can be used in exception handlers while still leaving " -"18\n" -" * instructions left; if paired with save_volatile_to_stack, there are 4\n" -" * instructions to spare.\n" -" */\n" -".macro restore_volatile_from_stack\n" -"\t/* Restore registers x2-x18, x29 & x30. */\n" -"\tldp x2, x3, [sp, #8 * 2]\n" -"\tldp x4, x5, [sp, #8 * 4]\n" -"\tldp x6, x7, [sp, #8 * 6]\n" -"\tldp x8, x9, [sp, #8 * 8]\n" -"\tldp x10, x11, [sp, #8 * 10]\n" -"\tldp x12, x13, [sp, #8 * 12]\n" -"\tldp x14, x15, [sp, #8 * 14]\n" -"\tldp x16, x17, [sp, #8 * 16]\n" -"\tldr x18, [sp, #8 * 18]\n" -"\tldp x29, x30, [sp, #8 * 20]\n" -"\n" -"\t/* Restore registers elr_el1 & spsr_el1, using x0 & x1 as scratch. */\n" -"\tldp x0, x1, [sp, #8 * 22]\n" -"\tmsr elr_el1, x0\n" -"\tmsr spsr_el1, x1\n" -"\n" -"\t/* Restore x0 & x1, and release stack space. */\n" -"\tldp x0, x1, [sp], #8 * 24\n" +".macro mov_i, reg:req, imm:req\n" +"\tmovz \\reg, :abs_g3:\\imm\n" +"\tmovk \\reg, :abs_g2_nc:\\imm\n" +"\tmovk \\reg, :abs_g1_nc:\\imm\n" +"\tmovk \\reg, :abs_g0_nc:\\imm\n" ".endm\n" "\n" -"/**\n" -" * This is a generic handler for exceptions taken at the current EL while " -"using\n" -" * SP0. It behaves similarly to the SPx case by first switching to SPx, " -"doing\n" -" * the work, then switching back to SP0 before returning.\n" -" *\n" -" * Switching to SPx and calling the Rust handler takes 16 instructions. To\n" +".set .L_MAIR_DEV_nGnRE,\t0x04\n" +".set .L_MAIR_MEM_WBWA,\t0xff\n" +".set .Lmairval, .L_MAIR_DEV_nGnRE | (.L_MAIR_MEM_WBWA << 8)\n" +"\n" +"/* 4 KiB granule size for TTBR0_EL1. */\n" +".set .L_TCR_TG0_4KB, 0x0 << 14\n" +"/* 4 KiB granule size for TTBR1_EL1. */\n" +".set .L_TCR_TG1_4KB, 0x2 << 30\n" +"/* Disable translation table walk for TTBR1_EL1, generating a translation " +"fault instead. */\n" +".set .L_TCR_EPD1, 0x1 << 23\n" +"/* Translation table walks for TTBR0_EL1 are inner sharable. */\n" +".set .L_TCR_SH_INNER, 0x3 << 12\n" +"/*\n" +" * Translation table walks for TTBR0_EL1 are outer write-back read-allocate " +"write-allocate\n" +" * cacheable.\n" +" */\n" +".set .L_TCR_RGN_OWB, 0x1 << 10\n" +"/*\n" +" * Translation table walks for TTBR0_EL1 are inner write-back read-allocate " +"write-allocate\n" +" * cacheable.\n" +" */\n" +".set .L_TCR_RGN_IWB, 0x1 << 8\n" +"/* Size offset for TTBR0_EL1 is 2**39 bytes (512 GiB). */\n" +".set .L_TCR_T0SZ_512, 64 - 39\n" +".set .Ltcrval, .L_TCR_TG0_4KB | .L_TCR_TG1_4KB | .L_TCR_EPD1 | ." +"L_TCR_RGN_OWB\n" +".set .Ltcrval, .Ltcrval | .L_TCR_RGN_IWB | .L_TCR_SH_INNER | ." +"L_TCR_T0SZ_512\n" +"\n" +"/* Stage 1 instruction access cacheability is unaffected. */\n" +".set .L_SCTLR_ELx_I, 0x1 << 12\n" +"/* SP alignment fault if SP is not aligned to a 16 byte boundary. */\n" +".set .L_SCTLR_ELx_SA, 0x1 << 3\n" +"/* Stage 1 data access cacheability is unaffected. */\n" +".set .L_SCTLR_ELx_C, 0x1 << 2\n" +"/* EL0 and EL1 stage 1 MMU enabled. */\n" +".set .L_SCTLR_ELx_M, 0x1 << 0\n" +"/* Privileged Access Never is unchanged on taking an exception to EL1. */\n" +".set .L_SCTLR_EL1_SPAN, 0x1 << 23\n" +"/* SETEND instruction disabled at EL0 in aarch32 mode. */\n" +".set .L_SCTLR_EL1_SED, 0x1 << 8\n" +"/* Various IT instructions are disabled at EL0 in aarch32 mode. */\n" +".set .L_SCTLR_EL1_ITD, 0x1 << 7\n" +".set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << " +"28) | (0x1 << 29)\n" +".set .Lsctlrval, .L_SCTLR_ELx_M | .L_SCTLR_ELx_C | .L_SCTLR_ELx_SA | ." +"L_SCTLR_EL1_ITD | .L_SCTLR_EL1_SED\n" +".set .Lsctlrval, .Lsctlrval | .L_SCTLR_ELx_I | .L_SCTLR_EL1_SPAN | ." +"L_SCTLR_EL1_RES1\n" +"\n" +"/**\n" +" * Es un punto de entrada gen茅rico para una imagen. It carries out the " +"operations required to prepare the\n" +" * loaded image to be run. Specifically, it zeroes the bss section using " +"registers x25 and above,\n" +" * prepares the stack, enables floating point, and sets up the exception " +"vector. It preserves x0-x3\n" +" * for the Rust entry point, as these may contain boot parameters.\n" +" */\n" +".section .init.entry, \"ax\"\n" +".global entry\n" +"entry:\n" +"\t/* Load and apply the memory management configuration, ready to enable MMU " +"and caches. */\n" +"\tadrp x30, idmap\n" +"\tmsr ttbr0_el1, x30\n" +"\n" +"\tmov_i x30, .Lmairval\n" +"\tmsr mair_el1, x30\n" +"\n" +"\tmov_i x30, .Ltcrval\n" +"\t/* Copy the supported PA range into TCR_EL1.IPS. */\n" +"\tmrs x29, id_aa64mmfr0_el1\n" +"\tbfi x30, x29, #32, #4\n" +"\n" +"\tmsr tcr_el1, x30\n" +"\n" +"\tmov_i x30, .Lsctlrval\n" +"\n" +"\t/*\n" +"\t * Ensure everything before this point has completed, then invalidate any " +"potentially stale\n" +"\t * local TLB entries before they start being used.\n" +"\t */\n" +"\tisb\n" +"\ttlbi vmalle1\n" +"\tic iallu\n" +"\tdsb nsh\n" +"\tisb\n" +"\n" +"\t/*\n" +"\t * Configure sctlr_el1 to enable MMU and cache and don't proceed until " +"this has completed.\n" +"\t */\n" +"\tmsr sctlr_el1, x30\n" +"\tisb\n" +"\n" +"\t/* Disable trapping floating point access in EL1. */\n" +"\tmrs x30, cpacr_el1\n" +"\torr x30, x30, #(0x3 << 20)\n" +"\tmsr cpacr_el1, x30\n" +"\tisb\n" +"\n" +"\t/* Zero out the bss section. */\n" +"\tadr_l x29, bss_begin\n" +"\tadr_l x30, bss_end\n" +"0:\tcmp x29, x30\n" +"\tb.hs 1f\n" +"\tstp xzr, xzr, [x29], #16\n" +"\tb 0b\n" +"\n" +"1:\t/* Prepare the stack. */\n" +"\tadr_l x30, boot_stack_end\n" +"\tmov sp, x30\n" +"\n" +"\t/* Set up exception vector. */\n" +"\tadr x30, vector_table_el1\n" +"\tmsr vbar_el1, x30\n" +"\n" +"\t/* Call into Rust code. */\n" +"\tbl main\n" +"\n" +"\t/* Loop forever waiting for interrupts. */\n" +"2:\twfi\n" +"\tb 2b\n" +"```" + +#: src/exercises/bare-metal/rtc.md +msgid "_exceptions.S_ (you shouldn't need to change this):" +msgstr "_exceptions.S_ (no deber铆a ser necesario cambiarlo):" + +#: src/exercises/bare-metal/rtc.md +msgid "" +"```armasm\n" +"/*\n" +" * Copyright 2023 Google LLC\n" +" *\n" +" * Licensed under the Apache License, Version 2.0 (the \"License\");\n" +" * you may not use this file except in compliance with the License.\n" +" * You may obtain a copy of the License at\n" +" *\n" +" * https://www.apache.org/licenses/LICENSE-2.0\n" +" *\n" +" * Unless required by applicable law or agreed to in writing, software\n" +" * distributed under the License is distributed on an \"AS IS\" BASIS,\n" +" * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n" +" * See the License for the specific language governing permissions and\n" +" * limitations under the License.\n" +" */\n" +"\n" +"/**\n" +" * Saves the volatile registers onto the stack. This currently takes 14\n" +" * instructions, so it can be used in exception handlers with 18 " +"instructions\n" +" * left.\n" +" *\n" +" * On return, x0 and x1 are initialised to elr_el2 and spsr_el2 " +"respectively,\n" +" * which can be used as the first and second arguments of a subsequent " +"call.\n" +" */\n" +".macro save_volatile_to_stack\n" +"\t/* Reserve stack space and save registers x0-x18, x29 & x30. */\n" +"\tstp x0, x1, [sp, #-(8 * 24)]!\n" +"\tstp x2, x3, [sp, #8 * 2]\n" +"\tstp x4, x5, [sp, #8 * 4]\n" +"\tstp x6, x7, [sp, #8 * 6]\n" +"\tstp x8, x9, [sp, #8 * 8]\n" +"\tstp x10, x11, [sp, #8 * 10]\n" +"\tstp x12, x13, [sp, #8 * 12]\n" +"\tstp x14, x15, [sp, #8 * 14]\n" +"\tstp x16, x17, [sp, #8 * 16]\n" +"\tstr x18, [sp, #8 * 18]\n" +"\tstp x29, x30, [sp, #8 * 20]\n" +"\n" +"\t/*\n" +"\t * Save elr_el1 & spsr_el1. This such that we can take nested exception\n" +"\t * and still be able to unwind.\n" +"\t */\n" +"\tmrs x0, elr_el1\n" +"\tmrs x1, spsr_el1\n" +"\tstp x0, x1, [sp, #8 * 22]\n" +".endm\n" +"\n" +"/**\n" +" * Restores the volatile registers from the stack. This currently takes 14\n" +" * instructions, so it can be used in exception handlers while still leaving " +"18\n" +" * instructions left; if paired with save_volatile_to_stack, there are 4\n" +" * instructions to spare.\n" +" */\n" +".macro restore_volatile_from_stack\n" +"\t/* Restore registers x2-x18, x29 & x30. */\n" +"\tldp x2, x3, [sp, #8 * 2]\n" +"\tldp x4, x5, [sp, #8 * 4]\n" +"\tldp x6, x7, [sp, #8 * 6]\n" +"\tldp x8, x9, [sp, #8 * 8]\n" +"\tldp x10, x11, [sp, #8 * 10]\n" +"\tldp x12, x13, [sp, #8 * 12]\n" +"\tldp x14, x15, [sp, #8 * 14]\n" +"\tldp x16, x17, [sp, #8 * 16]\n" +"\tldr x18, [sp, #8 * 18]\n" +"\tldp x29, x30, [sp, #8 * 20]\n" +"\n" +"\t/* Restore registers elr_el1 & spsr_el1, using x0 & x1 as scratch. */\n" +"\tldp x0, x1, [sp, #8 * 22]\n" +"\tmsr elr_el1, x0\n" +"\tmsr spsr_el1, x1\n" +"\n" +"\t/* Restore x0 & x1, and release stack space. */\n" +"\tldp x0, x1, [sp], #8 * 24\n" +".endm\n" +"\n" +"/**\n" +" * This is a generic handler for exceptions taken at the current EL while " +"using\n" +" * SP0. It behaves similarly to the SPx case by first switching to SPx, " +"doing\n" +" * the work, then switching back to SP0 before returning.\n" +" *\n" +" * Switching to SPx and calling the Rust handler takes 16 instructions. To\n" +" * restore and return we need an additional 16 instructions, so we can " +"implement\n" +" * the whole handler within the allotted 32 instructions.\n" +" */\n" +".macro current_exception_sp0 handler:req\n" +"\tmsr spsel, #1\n" +"\tsave_volatile_to_stack\n" +"\tbl \\handler\n" +"\trestore_volatile_from_stack\n" +"\tmsr spsel, #0\n" +"\teret\n" +".endm\n" +"\n" +"/**\n" +" * This is a generic handler for exceptions taken at the current EL while " +"using\n" +" * SPx. It saves volatile registers, calls the Rust handler, restores " +"volatile\n" +" * registers, then returns.\n" +" *\n" +" * This also works for exceptions taken from EL0, if we don't care about\n" +" * non-volatile registers.\n" +" *\n" +" * Saving state and jumping to the Rust handler takes 15 instructions, and\n" +" * restoring and returning also takes 15 instructions, so we can fit the " +"whole\n" +" * handler in 30 instructions, under the limit of 32.\n" +" */\n" +".macro current_exception_spx handler:req\n" +"\tsave_volatile_to_stack\n" +"\tbl \\handler\n" +"\trestore_volatile_from_stack\n" +"\teret\n" +".endm\n" +"\n" +".section .text.vector_table_el1, \"ax\"\n" +".global vector_table_el1\n" +".balign 0x800\n" +"vector_table_el1:\n" +"sync_cur_sp0:\n" +"\tcurrent_exception_sp0 sync_exception_current\n" +"\n" +".balign 0x80\n" +"irq_cur_sp0:\n" +"\tcurrent_exception_sp0 irq_current\n" +"\n" +".balign 0x80\n" +"fiq_cur_sp0:\n" +"\tcurrent_exception_sp0 fiq_current\n" +"\n" +".balign 0x80\n" +"serr_cur_sp0:\n" +"\tcurrent_exception_sp0 serr_current\n" +"\n" +".balign 0x80\n" +"sync_cur_spx:\n" +"\tcurrent_exception_spx sync_exception_current\n" +"\n" +".balign 0x80\n" +"irq_cur_spx:\n" +"\tcurrent_exception_spx irq_current\n" +"\n" +".balign 0x80\n" +"fiq_cur_spx:\n" +"\tcurrent_exception_spx fiq_current\n" +"\n" +".balign 0x80\n" +"serr_cur_spx:\n" +"\tcurrent_exception_spx serr_current\n" +"\n" +".balign 0x80\n" +"sync_lower_64:\n" +"\tcurrent_exception_spx sync_lower\n" +"\n" +".balign 0x80\n" +"irq_lower_64:\n" +"\tcurrent_exception_spx irq_lower\n" +"\n" +".balign 0x80\n" +"fiq_lower_64:\n" +"\tcurrent_exception_spx fiq_lower\n" +"\n" +".balign 0x80\n" +"serr_lower_64:\n" +"\tcurrent_exception_spx serr_lower\n" +"\n" +".balign 0x80\n" +"sync_lower_32:\n" +"\tcurrent_exception_spx sync_lower\n" +"\n" +".balign 0x80\n" +"irq_lower_32:\n" +"\tcurrent_exception_spx irq_lower\n" +"\n" +".balign 0x80\n" +"fiq_lower_32:\n" +"\tcurrent_exception_spx fiq_lower\n" +"\n" +".balign 0x80\n" +"serr_lower_32:\n" +"\tcurrent_exception_spx serr_lower\n" +"```" +msgstr "" +"```armasm\n" +"/*\n" +" * Copyright 2023 Google LLC\n" +" *\n" +" * Licensed under the Apache License, Version 2.0 (the \"License\");\n" +" * you may not use this file except in compliance with the License.\n" +" * You may obtain a copy of the License at\n" +" *\n" +" * https://www.apache.org/licenses/LICENSE-2.0\n" +" *\n" +" * Unless required by applicable law or agreed to in writing, software\n" +" * distributed under the License is distributed on an \"AS IS\" BASIS,\n" +" * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n" +" * See the License for the specific language governing permissions and\n" +" * limitations under the License.\n" +" */\n" +"\n" +"/**\n" +" * Saves the volatile registers onto the stack. This currently takes 14\n" +" * instructions, so it can be used in exception handlers with 18 " +"instructions\n" +" * left.\n" +" *\n" +" * On return, x0 and x1 are initialised to elr_el2 and spsr_el2 " +"respectively,\n" +" * which can be used as the first and second arguments of a subsequent " +"call.\n" +" */\n" +".macro save_volatile_to_stack\n" +"\t/* Reserve stack space and save registers x0-x18, x29 & x30. */\n" +"\tstp x0, x1, [sp, #-(8 * 24)]!\n" +"\tstp x2, x3, [sp, #8 * 2]\n" +"\tstp x4, x5, [sp, #8 * 4]\n" +"\tstp x6, x7, [sp, #8 * 6]\n" +"\tstp x8, x9, [sp, #8 * 8]\n" +"\tstp x10, x11, [sp, #8 * 10]\n" +"\tstp x12, x13, [sp, #8 * 12]\n" +"\tstp x14, x15, [sp, #8 * 14]\n" +"\tstp x16, x17, [sp, #8 * 16]\n" +"\tstr x18, [sp, #8 * 18]\n" +"\tstp x29, x30, [sp, #8 * 20]\n" +"\n" +"\t/*\n" +"\t * Save elr_el1 & spsr_el1. This such that we can take nested exception\n" +"\t * and still be able to unwind.\n" +"\t */\n" +"\tmrs x0, elr_el1\n" +"\tmrs x1, spsr_el1\n" +"\tstp x0, x1, [sp, #8 * 22]\n" +".endm\n" +"\n" +"/**\n" +" * Restores the volatile registers from the stack. This currently takes 14\n" +" * instructions, so it can be used in exception handlers while still leaving " +"18\n" +" * instructions left; if paired with save_volatile_to_stack, there are 4\n" +" * instructions to spare.\n" +" */\n" +".macro restore_volatile_from_stack\n" +"\t/* Restore registers x2-x18, x29 & x30. */\n" +"\tldp x2, x3, [sp, #8 * 2]\n" +"\tldp x4, x5, [sp, #8 * 4]\n" +"\tldp x6, x7, [sp, #8 * 6]\n" +"\tldp x8, x9, [sp, #8 * 8]\n" +"\tldp x10, x11, [sp, #8 * 10]\n" +"\tldp x12, x13, [sp, #8 * 12]\n" +"\tldp x14, x15, [sp, #8 * 14]\n" +"\tldp x16, x17, [sp, #8 * 16]\n" +"\tldr x18, [sp, #8 * 18]\n" +"\tldp x29, x30, [sp, #8 * 20]\n" +"\n" +"\t/* Restore registers elr_el1 & spsr_el1, using x0 & x1 as scratch. */\n" +"\tldp x0, x1, [sp, #8 * 22]\n" +"\tmsr elr_el1, x0\n" +"\tmsr spsr_el1, x1\n" +"\n" +"\t/* Restore x0 & x1, and release stack space. */\n" +"\tldp x0, x1, [sp], #8 * 24\n" +".endm\n" +"\n" +"/**\n" +" * This is a generic handler for exceptions taken at the current EL while " +"using\n" +" * SP0. It behaves similarly to the SPx case by first switching to SPx, " +"doing\n" +" * the work, then switching back to SP0 before returning.\n" +" *\n" +" * Switching to SPx and calling the Rust handler takes 16 instructions. To\n" " * restore and return we need an additional 16 instructions, so we can " "implement\n" " * the whole handler within the allotted 32 instructions.\n" @@ -20537,12 +21030,10 @@ msgid "" "serr_lower_32:\n" "\tcurrent_exception_spx serr_lower\n" "```" -msgstr "" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_idmap.S_ (you shouldn't need to change this):" -msgstr "`idmap.S` (no deber铆a ser necesario cambiarlo):" +msgstr "_idmap.S_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "" @@ -20592,11 +21083,55 @@ msgid "" "\t.fill\t\t255, 8, 0x0\t\t\t// 255 GiB of remaining VA space\n" "```" msgstr "" +"```armasm\n" +"/*\n" +" * Copyright 2023 Google LLC\n" +" *\n" +" * Licensed under the Apache License, Version 2.0 (the \"License\");\n" +" * you may not use this file except in compliance with the License.\n" +" * You may obtain a copy of the License at\n" +" *\n" +" * https://www.apache.org/licenses/LICENSE-2.0\n" +" *\n" +" * Unless required by applicable law or agreed to in writing, software\n" +" * distributed under the License is distributed on an \"AS IS\" BASIS,\n" +" * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n" +" * See the License for the specific language governing permissions and\n" +" * limitations under the License.\n" +" */\n" +"\n" +".set .L_TT_TYPE_BLOCK, 0x1\n" +".set .L_TT_TYPE_PAGE, 0x3\n" +".set .L_TT_TYPE_TABLE, 0x3\n" +"\n" +"/* Access flag. */\n" +".set .L_TT_AF, 0x1 << 10\n" +"/* Not global. */\n" +".set .L_TT_NG, 0x1 << 11\n" +".set .L_TT_XN, 0x3 << 53\n" +"\n" +".set .L_TT_MT_DEV, 0x0 << 2\t\t\t// MAIR #0 (DEV_nGnRE)\n" +".set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8)\t// MAIR #1 (MEM_WBWA), inner " +"shareable\n" +"\n" +".set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN\n" +".set .L_BLOCK_MEM, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG\n" +"\n" +".section \".rodata.idmap\", \"a\", %progbits\n" +".global idmap\n" +".align 12\n" +"idmap:\n" +"\t/* level 1 */\n" +"\t.quad\t\t.L_BLOCK_DEV | 0x0\t\t // 1 GiB of device mappings\n" +"\t.quad\t\t.L_BLOCK_MEM | 0x40000000\t// 1 GiB of DRAM\n" +"\t.fill\t\t254, 8, 0x0\t\t\t// 254 GiB of unmapped VA space\n" +"\t.quad\t\t.L_BLOCK_DEV | 0x4000000000 // 1 GiB of device mappings\n" +"\t.fill\t\t255, 8, 0x0\t\t\t// 255 GiB of remaining VA space\n" +"```" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_image.ld_ (you shouldn't need to change this):" -msgstr "`image.ld` (no deber铆a ser necesario cambiarlo):" +msgstr "_image.ld_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "" @@ -20708,32 +21243,137 @@ msgid "" "}\n" "```" msgstr "" +"```ld\n" +"/*\n" +" * Copyright 2023 Google LLC\n" +" *\n" +" * Licensed under the Apache License, Version 2.0 (the \"License\");\n" +" * you may not use this file except in compliance with the License.\n" +" * You may obtain a copy of the License at\n" +" *\n" +" * https://www.apache.org/licenses/LICENSE-2.0\n" +" *\n" +" * Unless required by applicable law or agreed to in writing, software\n" +" * distributed under the License is distributed on an \"AS IS\" BASIS,\n" +" * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n" +" * See the License for the specific language governing permissions and\n" +" * limitations under the License.\n" +" */\n" +"\n" +"/*\n" +" * Code will start running at this symbol which is placed at the start of " +"the\n" +" * image.\n" +" */\n" +"ENTRY(entry)\n" +"\n" +"MEMORY\n" +"{\n" +"\timage : ORIGIN = 0x40080000, LENGTH = 2M\n" +"}\n" +"\n" +"SECTIONS\n" +"{\n" +"\t/*\n" +"\t * Collect together the code.\n" +"\t */\n" +"\t.init : ALIGN(4096) {\n" +"\t\ttext_begin = .;\n" +"\t\t*(.init.entry)\n" +"\t\t*(.init.*)\n" +"\t} >image\n" +"\t.text : {\n" +"\t\t*(.text.*)\n" +"\t} >image\n" +"\ttext_end = .;\n" +"\n" +"\t/*\n" +"\t * Collect together read-only data.\n" +"\t */\n" +"\t.rodata : ALIGN(4096) {\n" +"\t\trodata_begin = .;\n" +"\t\t*(.rodata.*)\n" +"\t} >image\n" +"\t.got : {\n" +"\t\t*(.got)\n" +"\t} >image\n" +"\trodata_end = .;\n" +"\n" +"\t/*\n" +"\t * Collect together the read-write data including .bss at the end which\n" +"\t * will be zero'd by the entry code.\n" +"\t */\n" +"\t.data : ALIGN(4096) {\n" +"\t\tdata_begin = .;\n" +"\t\t*(.data.*)\n" +"\t\t/*\n" +"\t\t * The entry point code assumes that .data is a multiple of 32\n" +"\t\t * bytes long.\n" +"\t\t */\n" +"\t\t. = ALIGN(32);\n" +"\t\tdata_end = .;\n" +"\t} >image\n" +"\n" +"\t/* Everything beyond this point will not be included in the binary. */\n" +"\tbin_end = .;\n" +"\n" +"\t/* The entry point code assumes that .bss is 16-byte aligned. */\n" +"\t.bss : ALIGN(16) {\n" +"\t\tbss_begin = .;\n" +"\t\t*(.bss.*)\n" +"\t\t*(COMMON)\n" +"\t\t. = ALIGN(16);\n" +"\t\tbss_end = .;\n" +"\t} >image\n" +"\n" +"\t.stack (NOLOAD) : ALIGN(4096) {\n" +"\t\tboot_stack_begin = .;\n" +"\t\t. += 40 * 4096;\n" +"\t\t. = ALIGN(4096);\n" +"\t\tboot_stack_end = .;\n" +"\t} >image\n" +"\n" +"\t. = ALIGN(4K);\n" +"\tPROVIDE(dma_region = .);\n" +"\n" +"\t/*\n" +"\t * Remove unused sections from the image.\n" +"\t */\n" +"\t/DISCARD/ : {\n" +"\t\t/* The image loads itself so doesn't need these sections. */\n" +"\t\t*(.gnu.hash)\n" +"\t\t*(.hash)\n" +"\t\t*(.interp)\n" +"\t\t*(.eh_frame_hdr)\n" +"\t\t*(.eh_frame)\n" +"\t\t*(.note.gnu.build-id)\n" +"\t}\n" +"}\n" +"```" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "_Makefile_ (you shouldn't need to change this):" -msgstr "`Makefile` (no deber铆a ser necesario cambiarlo):" +msgstr "_Makefile_ (no deber铆a ser necesario cambiarlo):" #: src/exercises/bare-metal/rtc.md msgid "# Copyright 2023 Google LLC" -msgstr "" +msgstr "# Copyright 2023 Google LLC" #: src/exercises/bare-metal/rtc.md msgid "$(shell uname -s)" -msgstr "" +msgstr "$(shell uname -s)" #: src/exercises/bare-metal/rtc.md -#, fuzzy msgid "aarch64-linux-gnu" -msgstr "aarch64-paging" +msgstr "aarch64-linux-gnu" #: src/exercises/bare-metal/rtc.md msgid "stdio -display none -kernel $< -s" -msgstr "" +msgstr "stdio -display none -kernel $< -s" #: src/exercises/bare-metal/rtc.md msgid "cargo clean" -msgstr "" +msgstr "cargo clean" #: src/exercises/bare-metal/rtc.md msgid "Run the code in QEMU with `make qemu`." @@ -20741,98 +21381,96 @@ msgstr "Ejecuta el c贸digo en QEMU con `make qemu`." #: src/exercises/bare-metal/solutions-afternoon.md msgid "Bare Metal Rust Afternoon" -msgstr "Rust Bare Metal: tarde" +msgstr "Rust Bare Metal: Tarde" #: src/exercises/bare-metal/solutions-afternoon.md msgid "([back to exercise](rtc.md))" msgstr "([volver al ejercicio](rtc.md))" #: src/exercises/bare-metal/solutions-afternoon.md -#, fuzzy msgid "_main.rs_:" -msgstr "`main.rs`:" +msgstr "_main.rs_:" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Base address of the PL031 RTC.\n" -msgstr "" +msgstr "/// Direcci贸n base de PL031 RTC.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// The IRQ used by the PL031 RTC.\n" -msgstr "" +msgstr "/// IRQ que utiliza PL031 RTC.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" "// Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device,\n" " // and nothing else accesses that address range.\n" msgstr "" +"// Es seguro porque `PL031_BASE_ADDRESS` es la direcci贸n base de un " +"dispositivo PL031\n" +" // y ning煤n otro elemento puede acceder a ese intervalo de direcciones.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"RTC: {time}\"" -msgstr "" +msgstr "\"RTC: {time}\"" #: src/exercises/bare-metal/solutions-afternoon.md msgid "// Wait for 3 seconds, without interrupts.\n" -msgstr "" +msgstr "// Espera 3 segundos, sin interrupciones.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"Waiting for {}\"" -msgstr "" +msgstr "\"Esperando a {}\"" #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"matched={}, interrupt_pending={}\"" -msgstr "" +msgstr "\"matched={}, interrupt_pending={}\"" #: src/exercises/bare-metal/solutions-afternoon.md msgid "\"Finished waiting\"" -msgstr "" +msgstr "\"Espera finalizada\"" #: src/exercises/bare-metal/solutions-afternoon.md msgid "// Wait another 3 seconds for an interrupt.\n" -msgstr "" +msgstr "// Espera otros 3 segundos a que se produzca una interrupci贸n.\n" #: src/exercises/bare-metal/solutions-afternoon.md -#, fuzzy msgid "_pl031.rs_:" -msgstr "`pl031.rs`:" +msgstr "_pl031.rs_:" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Data register\n" -msgstr "" +msgstr "/// Registro de datos\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Match register\n" -msgstr "" +msgstr "/// Registro de coincidencias\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Load register\n" -msgstr "" +msgstr "/// Registro de cargas\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Control register\n" -msgstr "" +msgstr "/// Registro de control\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Interrupt Mask Set or Clear register\n" -msgstr "" +msgstr "/// Interrumpe Mask Set o Clear register\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Raw Interrupt Status\n" -msgstr "" +msgstr "/// Estado de interrupci贸n sin procesar\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Masked Interrupt Status\n" -msgstr "" +msgstr "/// Estado de interrupci贸n enmascarada\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Interrupt Clear Register\n" -msgstr "" +msgstr "/// Interrumpir registro de limpieza\n" #: src/exercises/bare-metal/solutions-afternoon.md -#, fuzzy msgid "/// Driver for a PL031 real-time clock.\n" -msgstr "" -"Escribiremos un controlador para el dispositivo de reloj en tiempo real " -"PL031." +msgstr "/// Controlador para un reloj en tiempo real PL031.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" @@ -20847,22 +21485,38 @@ msgid "" "process\n" " /// as device memory and not have any other aliases.\n" msgstr "" +"/// Crea una instancia nueva del controlador RTC para un dispositivo PL031 " +"en la\n" +" /// direcci贸n base proporcionada.\n" +" ///\n" +" /// # Seguridad\n" +" ///\n" +" /// El objeto la direcci贸n base debe apuntar a los registros de control " +"MMIO de un dispositivo\n" +" /// PL031, que debe asignarse al espacio de direcciones del proceso\n" +" /// como memoria del dispositivo y no tener ning煤n otro alias.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Reads the current RTC value.\n" -msgstr "" +msgstr "/// Lee el valor de RTC actual.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" "// Safe because we know that self.registers points to the control\n" " // registers of a PL031 device which is appropriately mapped.\n" msgstr "" +"// Es seguro porque sabemos que self.registers apunta\n" +" // a los registros de control de un dispositivo PL031 que est谩 " +"asignado correctamente.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" "/// Writes a match value. When the RTC value matches this then an interrupt\n" " /// will be generated (if it is enabled).\n" msgstr "" +"/// Escribe un valor de coincidencia. Cuando el valor de RTC coincida, se " +"generar谩 una interrupci贸n\n" +" /// (si est谩 habilitada).\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" @@ -20870,6 +21524,9 @@ msgid "" "not\n" " /// the interrupt is enabled.\n" msgstr "" +"/// Devuelve en funci贸n de si el registro de coincidencias coincide con el " +"valor de RTC,\n" +" /// si la interrupci贸n est谩 habilitada o no.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" @@ -20878,6 +21535,10 @@ msgid "" " /// This should be true if and only if `matched` returns true and the\n" " /// interrupt is masked.\n" msgstr "" +"/// Devuelve si hay una interrupci贸n pendiente.\n" +" ///\n" +" /// Solo debe ser true si `matched` devuelve true y\n" +" /// la interrupci贸n est谩 enmascarada.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "" @@ -20887,10 +21548,14 @@ msgid "" "the\n" " /// interrupt is disabled.\n" msgstr "" +"/// Define o borra la m谩scara de interrupci贸n.\n" +" ///\n" +" /// Si la m谩scara es true, se habilita la interrupci贸n; Si es false,\n" +" /// se inhabilita la interrupci贸n.\n" #: src/exercises/bare-metal/solutions-afternoon.md msgid "/// Clears a pending interrupt, if any.\n" -msgstr "" +msgstr "/// Borra una interrupci贸n pendiente, si la hubiera.\n" #: src/concurrency.md msgid "Welcome to Concurrency in Rust"