Unoptimised verilog code (simple_add example)

[RohitPatil555]

Hi,

I tried example of "simple_add" code. And successfully generated code in verilog.
After looking at verilog code it not look like optimised code.
I mean it just add function but it use lots of buffer. Just want normal combination logic without using clock to synchronise.

expected output. module ...
out = a + b;
endmodule

Note, I just followed command specified in document. (and also tried removing pipeline option from code generation step)
Do I need to do special action to avoid using additional buffer or clock?

Thanks,
~Rohit

[RohitPatil555]

Found solution : https://groups.google.com/g/xls-dev/c/R4wRBRgQIe4/m/uBxH5jWACwAJ

[cdleary]

Thanks for posting the question! Yes, as Rob mentions in that thread we have to make the documentation more clear here. The pipeline generator by default puts flops on input and output to avoid combinational overhang from causing timing closure issues, but we do have the flop_inputs/flop_outputs boolean arguments to the codegen build macro when generating pipelines as well, if the input/output flops are not necessary; see https://google.github.io/xls/build_system/#dslx_codegen

[proppy]

closing this as --generator=combinational doesn't generate flopped i/o:

module __simpler_adder__simpler_adder(
  input wire [7:0] a,
  input wire [7:0] b,
  output wire [7:0] out
);
  wire [7:0] add_6;
  assign add_6 = a + b;
  assign out = add_6;
endmodule