vcd.scn

/*
tb: bin
tb:u0_sUART: bin
tb:dut: bin
tb:dut:u0_top: bin
tb:dut:u0_clk_gen: bin
tb:dut:u0_peripherals: bin
tb:dut:u0_dma: bin
tb:dut:u0_sUART: bin
tb:dut:u0_risc_V_core:u0_register_file: bin
tb:dut:u0_risc_V_core:u0_dbg_mem: bin


tb:dut:u0_mem: bin
tb:dut:u1_mem: bin

tb:dut:u0_sdram_ctrl: bin

tb:dut:u0_hdmi: bin
tb:dut:u0_hdmi:u0_char_buf: bin
tb:dut:u0_hdmi:u0_font: bin
tb:dut:u0_hdmi:u0_ddio: bin
*/
tb:dut:u0_risc_V_core: bin

tb:dut:u0_csr_irq: bin
/*
tb:dut:u0_mem: bin
tb:dut:u1_mem: bin
*/
tb:dut:u0_sUART: bin
tb:dut:u0_spi: bin
tb:u0_spi: bin
tb:dut:dbg bin
tb:u0_sUART: bin
/*
tb: bin
*/
/*
tb: bin
tb:u0_clk_gen: bin
*/
/*
tb:dut:u0_risc_V_core:u0_register_file: bin
tb:dut:u0_risc_V_core:core2datamem_o.addr bin
tb:dut:u0_risc_V_core:core2datamem_o.cs_n bin
tb:dut:u0_risc_V_core:core2datamem_o.wr_n bin
tb:dut:u0_risc_V_core:core2datamem_o.data bin
tb:dut:u0_risc_V_core:instmem2core_i.data bin
tb:dut:u0_risc_V_core:datamem2core_i.data bin
tb:dut:u0_risc_V_core:ropcode bin
tb:dut:u0_risc_V_core:raw_opcode bin
tb:dut:u0_risc_V_core:rinstr bin
tb:dut:u0_risc_V_core:rrinstr bin
tb:dut:u0_risc_V_core:PC bin
tb:dut:u0_risc_V_core:mepc bin
tb:dut:u0_risc_V_core:PCp bin
tb:dut:u0_risc_V_core:rop1 bin
tb:dut:u0_risc_V_core:rop2 bin
tb:dut:u0_risc_V_core:regs(1) bin
tb:dut:u0_risc_V_core:regs(2) bin
tb:dut:u0_risc_V_core:regs(3) bin
tb:dut:u0_risc_V_core:regs(4) bin
tb:dut:u0_risc_V_core:regs(5) bin
tb:dut:u0_risc_V_core:regs(6) bin
tb:dut:u0_risc_V_core:regs(7) bin
tb:dut:u0_risc_V_core:regs(8) bin
tb:dut:u0_risc_V_core:regs(9) bin
tb:dut:u0_risc_V_core:regs(10) bin
tb:dut:u0_risc_V_core:regs(11) bin
tb:dut:u0_risc_V_core:regs(12) bin
tb:dut:u0_risc_V_core:regs(13) bin
tb:dut:u0_risc_V_core:regs(14) bin
tb:dut:u0_risc_V_core:regs(25) bin
tb:dut:u0_risc_V_core:regs(26) bin
tb:dut:u0_risc_V_core:regs(27) bin
tb:dut:u0_risc_V_core:regs(31) bin
tb:dut:u0_risc_V_core:
tb:dut:u0_peripherals:
tb:dut:u0_hdmi: 
*/