{"payload":{"header_redesign_enabled":false,"results":[{"id":"318853153","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"ibrahimayaz95/UART","hl_trunc_description":"UART communication between FPGA and Computer","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":318853153,"name":"UART","owner_id":75534198,"owner_login":"ibrahimayaz95","updated_at":"2020-12-11T08:58:12.420Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":69,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aibrahimayaz95%252FUART%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/ibrahimayaz95/UART/star":{"post":"N4BQKQZbi1qvvXrzsqvdO4s5YWl4Sq-pDG0810znEA_x-hqz0C8eXFLb2USIlSmZqA0UJJ0rMnN2nAcAK6vo7w"},"/ibrahimayaz95/UART/unstar":{"post":"rjFVKI7jGRoXnTmzZUcd2HmMfwwXiq5iIYQQ404SJVP8mjAMGq8a-1V0PshxWeHm0bJAt8zz9ikbrE4bfURJMw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"DYWiIWdESNkGhZjQ45zCPG3EaXGb7SOZh07m6ZEDySSlUwvUq8Tbq6WjfpSkcsaaVVHbIktDwKS9czUPxMH-Ig"}}},"title":"Repository search results"}