From 1a3770b668be703e84e483458a2f114fad735786 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 3 Nov 2024 12:47:20 +0000 Subject: [PATCH 01/21] Add the transmission gate (still onging) folder from the SaltyChi team in Chipathon 2024 --- .../transmission_gate_saltychip/inv_lib.py | 43 ++++++++++ .../transmission_gate.py | 83 +++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100755 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py create mode 100755 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py new file mode 100755 index 000000000..3d6b13370 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py @@ -0,0 +1,43 @@ +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +from glayout.flow.pdk.mappedpdk import MappedPDK +from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port +from gdsfactory import Component +from gdsfactory.components import rectangle +from glayout.flow.primitives.fet import pmos +from glayout.flow.primitives.fet import nmos +from glayout.flow.routing.straight_route import straight_route +from glayout.flow.routing.c_route import c_route +from glayout.flow.routing.L_route import L_route +from glayout.flow.routing.smart_route import smart_route + +def basic_inv_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length, orientation): + # Create a top level component + top_level = Component("inverter") + # To prepare one PMOS and one NMOS for the subsequent inverter cell construction + pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + + # Instantiation of above PMOS and NMOS under the top level + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) + top_level.add(pfet_ref) + top_level.add(nfet_ref) + + # To add the ports + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + + # Placement (relative move) + mos_spacing = pdk.util_max_metal_seperation() + if(orientation=="horizontal"): + #pfet_ref.drotate(90) + #nfet_ref.drotate(90) + pass + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + # Routing + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"]) + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"]) + + return top_level diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py new file mode 100755 index 000000000..1d75347b7 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -0,0 +1,83 @@ +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +from glayout.flow.pdk.mappedpdk import MappedPDK +from glayout.flow.pdk.util.comp_utils import evaluate_bbox +from gdsfactory import Component +from gdsfactory.components import rectangle +from glayout.flow.primitives.fet import pmos +from glayout.flow.primitives.fet import nmos +from glayout.flow.routing.straight_route import straight_route +from glayout.flow.routing.c_route import c_route +from glayout.flow.routing.L_route import L_route +from glayout.flow.routing.smart_route import smart_route +from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized +from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized +from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port + +# My own cell library +from inv_lib import basic_inv_cell + +def naive_tg_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): + # To prepare all necessary cells to construct a transmission gate, i.e. + # 1) PMOS + # 2) NMOS + # 3) Inverter (to control the gates of above PMOS and NMOS) + pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + inv = basic_inv_cell(pdk=pdk, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="vertical") + + # Placement and adding ports + top_level = Component(name="TG") + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) +# inv_ref = prec_ref_center(inv) + top_level.add(pfet_ref) + top_level.add(nfet_ref) +# top_level.add(inv_ref) + inv_ref = top_level << inv + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") + + # Placement + mos_spacing = pdk.util_max_metal_seperation() + pfet_ref.movey(evaluate_bbox(nfet_ref)[1]+mos_spacing) + pfet_ref.movex(evaluate_bbox(inv_ref)[0]+mos_spacing) # Placing the TG's PMOS at right side of the inverter + nfet_ref.movex(evaluate_bbox(inv_ref)[0]+mos_spacing) # Placing the TG's NMOS at right side of the inverter + + # Routing + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG + top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_W"], pfet_ref.ports["multiplier_0_gate_W"]) # connect inv's output to PMOS's gate + top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_E"], nfet_ref.ports["multiplier_0_gate_E"]) + + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + + # To define the layers + gds_met1 = pdk.get_glayer("met2")[0] + gds_met2 = gds_met1+1 + gds_met3 = gds_met2+1 + gds_met4 = gds_met3+1 + gds_met5 = gds_met4+1 + # To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port + tg_din_portLayer = top_level.ports["pmos_multiplier_0_source_W"].layer[0] + tg_dout_portLayer = top_level.ports["pmos_multiplier_0_drain_E"].layer[0] + # To create the pins w/ labels and append to info list + tg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) + tg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy() + tg_din_pin.add_label(text="Vin", layer=(tg_din_portLayer, 5)) + tg_dout_pin.add_label(text="Vout", layer=(tg_dout_portLayer, 5)) + pins_labels_info.append((tg_din_pin, top_level.ports["pmos_multiplier_0_source_W"], None)) + pins_labels_info.append((tg_dout_pin, top_level.ports["pmos_multiplier_0_drain_E"], None)) + + #print(top_level.ports["pmos_multiplier_0_source_W"].name) + #top_level.pprint_ports() + + # Move everythin to position + for comp, prt, alignment in pins_labels_info: + alignment = ('c', 'b') if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + #top_level.add(compref) + + return top_level #top_level.flatten() From 0377bae1691e1c4740fbc02bd9d762ab6870e6e0 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 3 Nov 2024 13:05:57 +0000 Subject: [PATCH 02/21] Add the README and __init__.py files for the transmission gate block Developer: SaltyChip team in Chipathon 2024 --- .../flow/blocks/transmission_gate_saltychip/README.md | 6 ++++++ .../flow/blocks/transmission_gate_saltychip/__init__.py | 2 ++ 2 files changed, 8 insertions(+) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md new file mode 100644 index 000000000..11a8225b4 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md @@ -0,0 +1,6 @@ +# Transmission gate block for SAR A/D converter + +| Design File | Description | Remark | +| --- | --- | --- | +| inv_lib.py | Layout generation of inverter for controlling the transmission gate's PMOS and NMOS | | +| transmission_gate.py | Layout generation of a transmission gate | The layout is still under construction | diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py new file mode 100644 index 000000000..8118c6390 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py @@ -0,0 +1,2 @@ +from glayout.flow.blocks.transmission_gate_saltychip.inv_lib import basic_inv_cell +from glayout.flow.blocks.transmission_gate_saltychip.transmission_gate import naive_tg_cell From 5d7dc555ecc00a32bf9ed7ee42b1b616bb0aa497 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 3 Nov 2024 13:28:15 +0000 Subject: [PATCH 03/21] Add mimcap array layout --- .../transmission_gate_saltychip/README.md | 3 + .../mimcap_array.py | 451 ++++++++++++++++++ 2 files changed, 454 insertions(+) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md index 11a8225b4..d2cc04388 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md @@ -1,6 +1,9 @@ # Transmission gate block for SAR A/D converter +- Team: SaltyChip +- Design (our target): DAC for 6-bit A/D converter | Design File | Description | Remark | | --- | --- | --- | | inv_lib.py | Layout generation of inverter for controlling the transmission gate's PMOS and NMOS | | | transmission_gate.py | Layout generation of a transmission gate | The layout is still under construction | +| mimcap_array.py | Layout generation of a 8x8 MIM capacitor array | Transmission gate combined with a MIM capacitor array is the aim in this project | diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py new file mode 100644 index 000000000..0b87f2310 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py @@ -0,0 +1,451 @@ +# Primitives +from glayout.flow.primitives.mimcap import mimcap +from glayout.flow.primitives.mimcap import mimcap_array +from glayout.flow.primitives.via_gen import via_stack, via_array + +# Standard +from glayout.flow.pdk.mappedpdk import MappedPDK +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 + +# gdsfactory +from gdsfactory import Component +from gdsfactory.cell import cell +from gdsfactory.components.rectangle import rectangle + +# Utility +from glayout.flow.pdk.util.comp_utils import evaluate_bbox, prec_center, prec_array, align_comp_to_port + +# Routing +from glayout.flow.routing.straight_route import straight_route +from glayout.flow.routing.c_route import c_route + +import copy + +def get_mimcap_layerconstruction_info(pdk: MappedPDK) -> tuple[str,str]: + """returns the glayer metal below and glayer metal above capmet + args: pdk + """ + capmettop = pdk.layer_to_glayer(pdk.get_grule("capmet")["capmettop"]) + capmetbottom = pdk.layer_to_glayer(pdk.get_grule("capmet")["capmetbottom"]) + pdk.has_required_glayers(["capmet",capmettop,capmetbottom]) + pdk.activate() + return capmettop, capmetbottom + +def create_6bit_dac_mimcap_array(pdk: MappedPDK): + """ + Creates a 6-bit DAC using an 8x8 MIM capacitor array with binary weighting. + """ + # Create the top-level component + dac_mim_cap = Component("6bit_DAC_MIMCAP_Array") + + ''' + # Define unit capacitor size (for example, 2x2 microns) + unit_size = [5.0, 5.0] + unit_mimcap = mimcap(pdk, size=unit_size) + + # Define bit weights for binary weighted capacitors + bit_weights = [32, 16, 8, 4, 2, 1] # From MSB to LSB + total_units = sum(bit_weights) + total_caps = 64 # 8x8 array + dummy_units = total_caps - total_units # Extra units as dummy + + # Generate common centroid indices for optimal matching + cap_indices = [(i, j) for i in range(8) for j in range(8)] + ''' + + # metal and via layers + met2 = pdk.get_glayer('met3') + met3_capmetbottom = pdk.get_glayer('met4') + met4_capmettop = pdk.get_glayer('met5') + via3 = pdk.get_glayer('via4') + mimcap_arr = Component("mimcap_arr") + #test_cap << rectangle(size=(1, 1), layer=via3) + mimcap_single_size = 5 + mimcap_single = mimcap(pdk, size=(mimcap_single_size,mimcap_single_size)) + rows_num = 8 + columns_num = 8 + mimcap_space = 10*pdk.get_grule("capmet")["min_separation"] + met4_width = pdk.get_grule("met5")["min_width"] + array_ref = mimcap_arr << prec_array(mimcap_single, rows=rows_num, columns=columns_num, spacing=2*[mimcap_space]) + mimcap_arr.add_ports(array_ref.get_ports_list()) + mim_metal_space = mimcap_space/9 + ##################### + port_pairs = list() + port_sides_pairs = list() + via_refs = list() + for rownum in range(rows_num): + for colnum in range(columns_num): + base_mimcap = f"row{rownum}_col{colnum}_" + right_mimcap = f"row{rownum}_col{colnum+1}_" + up_mimcap = f"row{rownum+1}_col{colnum}_" + capmetbottom = "met4" + capmettop = "met5" + + # Bottom Metal + level = "bottom_met_" + layer = capmetbottom + base_east_port = mimcap_arr.ports.get(base_mimcap+level+"E") + right_west_port = mimcap_arr.ports.get(right_mimcap+level+"W") + base_north_port = mimcap_arr.ports.get(base_mimcap+level+"N") + up_south_port = mimcap_arr.ports.get(up_mimcap+level+"S") + if rownum == rows_num-1 and colnum == columns_num-1: + pass #continue + elif rownum == rows_num-1: + port_pairs.append((base_east_port,right_west_port,layer)) + elif colnum == columns_num-1: + port_pairs.append((base_north_port,up_south_port,layer)) + else: + port_pairs.append((base_east_port,right_west_port,layer)) + port_pairs.append((base_north_port,up_south_port,layer)) + + # Top metal + level = "top_met_" + position_up = "up_" + position_down = "down_" + position_right = "right_" + position_left = "left_" + layer = capmettop + base_east_port = mimcap_arr.ports.get(base_mimcap+level+"E") + met4_distance_from_center = base_east_port.width/2 - pdk.get_grule(layer)["min_width"] + if base_east_port is not None: + base_east_port_up = base_east_port.copy() + base_east_port_up.name = base_mimcap+position_up+level+"E" + base_east_port_up.center[1] += met4_distance_from_center #(base_east_port_up.width/2 - pdk.get_grule(layer)["min_width"]) + base_east_port_up_space1 = base_east_port_up.copy() + base_east_port_up_space1.name = base_mimcap+position_up+level+"W" + base_east_port_up_space1.center[0] += mim_metal_space*1 + base_east_port_up_space4 = base_east_port_up.copy() + base_east_port_up_space4.name = base_mimcap+position_up+level+"W" + base_east_port_up_space4.center[0] += mim_metal_space*4 + base_east_port_down = base_east_port.copy() + base_east_port_down.name = base_mimcap+position_down+level+"E" + base_east_port_down.center[1] -= met4_distance_from_center #(base_north_port.width/2 - pdk.get_grule(layer)["min_width"]) + base_east_port_down_space1 = base_east_port_down.copy() + base_east_port_down_space1.name = base_mimcap+position_down+level+"W" + base_east_port_down_space1.center[0] += mim_metal_space*1 + base_east_port_down_space4 = base_east_port_down.copy() + base_east_port_down_space4.name = base_mimcap+position_down+level+"W" + base_east_port_down_space4.center[0] += mim_metal_space*4 + right_west_port = mimcap_arr.ports.get(right_mimcap+level+"W") + if right_west_port is not None: + right_west_port_up = right_west_port.copy() + right_west_port_up.name = right_mimcap+position_up+level+"W" + right_west_port_up.center[1] += met4_distance_from_center #(right_west_port_up.width/2 - pdk.get_grule(layer)["min_width"]) + right_west_port_up_space3 = right_west_port_up.copy() + right_west_port_up_space3.name = right_mimcap+position_up+level+"E" + right_west_port_up_space3.center[0] -= mim_metal_space*3 + right_west_port_up_space4 = right_west_port_up.copy() + right_west_port_up_space4.name = right_mimcap+position_up+level+"E" + right_west_port_up_space4.center[0] -= mim_metal_space*4 + right_west_port_up_space7 = right_west_port_up.copy() + right_west_port_up_space7.name = right_mimcap+position_up+level+"E" + right_west_port_up_space7.center[0] -= mim_metal_space*7 + right_west_port_down = right_west_port.copy() + right_west_port_down.name = right_mimcap+position_down+level+"W" + right_west_port_down.center[1] -= met4_distance_from_center #(right_west_port_down.width/2 - pdk.get_grule(layer)["min_width"]) + right_west_port_down_space3 = right_west_port_down.copy() + right_west_port_down_space3.name = right_mimcap+position_down+level+"E" + right_west_port_down_space3.center[0] -= mim_metal_space*3 + right_west_port_down_space4 = right_west_port_down.copy() + right_west_port_down_space4.name = right_mimcap+position_down+level+"E" + right_west_port_down_space4.center[0] -= mim_metal_space*4 + right_west_port_down_space7 = right_west_port_down.copy() + right_west_port_down_space7.name = right_mimcap+position_down+level+"E" + right_west_port_down_space7.center[0] -= mim_metal_space*7 + base_north_port = mimcap_arr.ports.get(base_mimcap+level+"N") + if base_north_port is not None: + base_north_port_right = base_north_port.copy() + base_north_port_right.name = base_mimcap+position_right+level+"N" + base_north_port_right.center[0] += met4_distance_from_center #(base_north_port_right.width/2 - pdk.get_grule(layer)["min_width"]) + base_north_port_right_space = base_north_port_right.copy() + base_north_port_right_space.name = base_mimcap+position_right+level+"S" + base_north_port_right_space.center[1] += mim_metal_space*4 + base_north_port_left = base_north_port.copy() + base_north_port_left.name = base_mimcap+position_left+level+"N" + base_north_port_left.center[0] -= met4_distance_from_center #(base_north_port_left.width/2 - pdk.get_grule(layer)["min_width"]) + base_north_port_left_space = base_north_port_left.copy() + base_north_port_left_space.name = base_mimcap+position_left+level+"S" + base_north_port_left_space.center[1] += mim_metal_space*4 + up_south_port = mimcap_arr.ports.get(up_mimcap+level+"S") + if up_south_port is not None: + up_south_port_right = up_south_port.copy() + up_south_port_right.name = base_mimcap+position_right+level+"S" + up_south_port_right.center[0] += met4_distance_from_center #(up_south_port_right.width/2 - pdk.get_grule(layer)["min_width"]) + up_south_port_right_space = up_south_port_right.copy() + up_south_port_right_space.name = base_mimcap+position_right+level+"N" + up_south_port_right_space.center[1] -= mim_metal_space*4 + up_south_port_left = up_south_port.copy() + up_south_port_left.name = base_mimcap+position_left+level+"S" + up_south_port_left.center[0] -= met4_distance_from_center #(up_south_port_left.width/2 - pdk.get_grule(layer)["min_width"]) + up_south_port_left_space = up_south_port_left.copy() + up_south_port_left_space.name = base_mimcap+position_left+level+"N" + up_south_port_left_space.center[1] -= mim_metal_space*4 + + ''' + if rownum in (0,1,2,4): + if colnum == 0: + base_west_side_port = mimcap_arr.ports.get(base_mimcap+level+"W") + base_west_side_port.name = base_mimcap+level+"westside_"+"W" + base_west_side_port.center + += met4_distance_from_center + else: + if colnum == 7: + ''' + + if rownum == 0: + # North and South + if colnum in (2,3,5,6): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (5,6): #(1,7) + port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) + via_mimcap = via_stack(pdk, "met3", capmettop) + #via_mimcap = via_array(pdk, "met3", capmettop, size=(met4_width,met4_width), num_vias=(2,2), fullbottom=False) + via_refs.append(align_comp_to_port(via_mimcap, right_west_port_up_space7, ("c", "c"))) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 1: + # North and South + if colnum in (1,2,4,5): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (0,2,3,5): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum in (1,6): #(1,7) + port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) + elif colnum == 4: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 2: + # North and South + if colnum in (0,1,2,3,4,5,7): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (4,5): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum in (0,6): #(1,7) + port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) + elif colnum == 3: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 3: + # North and South + if colnum in (0,1,2,3,5,6,7): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (0,1,2,3): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 4: + # North and South + if colnum in (0,2,3,4,5,6,7): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (2,3): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum in (5,6): #(1,7) + port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) + elif colnum == 4: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 5: + # North and South + if colnum in (2,3,5,6): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (2,3,6): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum == 1: #(1,7) + port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) + elif colnum == 0: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 6: + # North and South + if colnum in (1,2,4,5): + port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) + port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) + port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) + port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) + else: + port_pairs.append((base_north_port_left,up_south_port_left,layer)) + port_pairs.append((base_north_port_right,up_south_port_right,layer)) + # West and East + if colnum in (1,2,3,4,5,6): #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum == 0: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + elif rownum == 7: + # West and East + if colnum == 1: #(4,4) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) + elif colnum == 0: #(4,3) + port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) + port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) + port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) + port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) + elif colnum == columns_num-1: + pass #continue + else: + port_pairs.append((base_east_port_up,right_west_port_up,layer)) + port_pairs.append((base_east_port_down,right_west_port_down,layer)) + + # metal2 + layer = "met3" + base_east_port_metal2_up = mimcap_arr.ports.get(base_mimcap+level+"E") + base_east_port_metal2_up.name = base_mimcap+"east_metal2_up" + base_east_port_metal2_up.center[0] += mim_metal_space*3 + base_east_port_metal2_up.center[1] += (met4_distance_from_center + met4_width/2) + base_east_port_metal2_up.orientation = 270 + base_east_port_metal2_up.layer = met2 + base_east_port_metal2_down = base_east_port_metal2_up.copy() + base_east_port_metal2_down.name = base_mimcap+"east_metal2_down" + if colnum == 4: + base_east_port_metal2_down.center[1] -= (mimcap_single_size*15/2 + mimcap_space*8) + else: + base_east_port_metal2_down.center[1] -= (mimcap_single_size*17/2 + mimcap_space*8) + port_pairs.append((base_east_port_metal2_up,base_east_port_metal2_down,layer)) + base_west_port_metal2_up = mimcap_arr.ports.get(base_mimcap+level+"W") + base_west_port_metal2_up.name = base_mimcap+"west_metal2_up" + base_west_port_metal2_up.center[0] -= mim_metal_space*3 + base_west_port_metal2_up.center[1] += (met4_distance_from_center + met4_width/2) + base_west_port_metal2_up.orientation = 270 + base_west_port_metal2_up.layer = met2 + base_west_port_metal2_down = base_west_port_metal2_up.copy() + base_west_port_metal2_down.name = base_mimcap+"west_metal2_down" + if colnum in (1,2,6,7): + base_west_port_metal2_down.center[1] -= (mimcap_single_size*15/2 + mimcap_space*8) + else: + base_west_port_metal2_down.center[1] -= (mimcap_single_size*17/2 + mimcap_space*8) + port_pairs.append((base_west_port_metal2_up,base_west_port_metal2_down,layer)) + + for port_pair in port_pairs: + mimcap_arr << straight_route(pdk, port_pair[0], port_pair[1], width=met4_width) + for via_ref in via_refs: + mimcap_arr.add(via_refs) + + cap_ref = dac_mim_cap.add_ref(mimcap_arr) + #cap_ref.movey(-30) + + + return dac_mim_cap + + + +# Create and show the DAC MIM capacitor array layout +dac_mimcap_component = create_6bit_dac_mimcap_array(sky130).show() From 23738f6a9e9cdff7e86bdb4dcb67529af1f19aa0 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 3 Nov 2024 13:36:09 +0000 Subject: [PATCH 04/21] Update the progress in the README --- .../glayout/flow/blocks/transmission_gate_saltychip/README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md index d2cc04388..4049e2a20 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md @@ -1,6 +1,7 @@ # Transmission gate block for SAR A/D converter - Team: SaltyChip -- Design (our target): DAC for 6-bit A/D converter +- Design (our target): DAC for 6-bit A/D converter +- Progress: ongoing, 03/11/2024 | Design File | Description | Remark | | --- | --- | --- | From de306c858d390f6c13bfb85cb4df68f7501efab7 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Fri, 8 Nov 2024 07:59:24 +0000 Subject: [PATCH 05/21] Modify the layout of the transmission by rotating every MOSFET 90 degree --- .../transmission_gate_saltychip/__init__.py | 4 +- .../transmission_gate_saltychip/inv_lib.py | 9 ++-- .../transmission_gate.py | 52 +++++++++++++------ 3 files changed, 43 insertions(+), 22 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py index 8118c6390..841af6bae 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py @@ -1,2 +1,2 @@ -from glayout.flow.blocks.transmission_gate_saltychip.inv_lib import basic_inv_cell -from glayout.flow.blocks.transmission_gate_saltychip.transmission_gate import naive_tg_cell +from glayout.flow.blocks.transmission_gate_saltychip.inv_lib import reconfig_inv +from glayout.flow.blocks.transmission_gate_saltychip.transmission_gate import tg_with_inv diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py index 3d6b13370..bd0f3eb87 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py @@ -11,9 +11,9 @@ from glayout.flow.routing.L_route import L_route from glayout.flow.routing.smart_route import smart_route -def basic_inv_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length, orientation): +def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation): # Create a top level component - top_level = Component("inverter") + top_level = Component(component_name) # To prepare one PMOS and one NMOS for the subsequent inverter cell construction pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) @@ -31,8 +31,9 @@ def basic_inv_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_len # Placement (relative move) mos_spacing = pdk.util_max_metal_seperation() if(orientation=="horizontal"): - #pfet_ref.drotate(90) - #nfet_ref.drotate(90) + pfet_ref.rotate(90) + nfet_ref.rotate(90) + else: pass pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 1d75347b7..c2bf6437e 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -15,46 +15,38 @@ from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port # My own cell library -from inv_lib import basic_inv_cell +from inv_lib import reconfig_inv def naive_tg_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - # 3) Inverter (to control the gates of above PMOS and NMOS) pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) - inv = basic_inv_cell(pdk=pdk, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="vertical") - + # Placement and adding ports top_level = Component(name="TG") pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) -# inv_ref = prec_ref_center(inv) top_level.add(pfet_ref) top_level.add(nfet_ref) -# top_level.add(inv_ref) - inv_ref = top_level << inv top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") # Placement mos_spacing = pdk.util_max_metal_seperation() - pfet_ref.movey(evaluate_bbox(nfet_ref)[1]+mos_spacing) - pfet_ref.movex(evaluate_bbox(inv_ref)[0]+mos_spacing) # Placing the TG's PMOS at right side of the inverter - nfet_ref.movex(evaluate_bbox(inv_ref)[0]+mos_spacing) # Placing the TG's NMOS at right side of the inverter + #mos_spacing = pdk.get_grule("met1")["min_width"]) + pfet_ref.rotate(90) + nfet_ref.rotate(90) + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) # Routing top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG - top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_W"], pfet_ref.ports["multiplier_0_gate_W"]) # connect inv's output to PMOS's gate - top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_E"], nfet_ref.ports["multiplier_0_gate_E"]) + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_W"]) # "out" of the TG # Add pins and text labels for LVS pins_labels_info = list() # list that contains all port and component information - - # To define the layers + # To define the layers gds_met1 = pdk.get_glayer("met2")[0] gds_met2 = gds_met1+1 gds_met3 = gds_met2+1 @@ -81,3 +73,31 @@ def naive_tg_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_leng #top_level.add(compref) return top_level #top_level.flatten() + +def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): + # To prepare all necessary cells to construct a transmission gate, i.e. + # 1) transmission gate + # 2) Inverter + tg = naive_tg_cell(pdk=pdk, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) + inv = reconfig_inv(pdk=pdk, component_name="gate_ctrl_inv", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="horizontal") + + # Placement and adding ports + top_level = Component(name="tg_with_inv") + tg_ref = prec_ref_center(tg) + inv_ref = prec_ref_center(inv) + top_level.add(tg_ref) + top_level.add(inv_ref) + top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") + top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") + + # Placement + mos_spacing = pdk.util_max_metal_seperation() + tg_ref.movex(evaluate_bbox(inv)[0] + mos_spacing) + + # Routing + #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG + #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG + + return top_level #top_level.flatten() + +tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15).show() From b1d1ae02ffb3c15cbb6fd8bd887260242e5ecb19 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 10 Nov 2024 13:28:10 +0000 Subject: [PATCH 06/21] Add dummy cells to the PMOS-NMOS pair for the TG against the asymmetical layout (form of parallel-gate transistors) --- .../transmission_gate.py | 98 ++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index c2bf6437e..043f12b9a 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -1,3 +1,4 @@ +from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict #from glayout.flow.pdk.gf180_mapped import gf180 from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 from glayout.flow.pdk.mappedpdk import MappedPDK @@ -16,7 +17,7 @@ # My own cell library from inv_lib import reconfig_inv - +''' def naive_tg_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS @@ -98,6 +99,101 @@ def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG + return top_level #top_level.flatten() +''' +def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, nmos_length): + # To prepare all necessary cells to construct a transmission gate, i.e. + # 1) PMOS + # 2) NMOS + pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) + + # Placement and adding ports + top_level = Component(name="TG") + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) + top_level.add(pfet_ref) + top_level.add(nfet_ref) + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + #top_level.add_port( + # name="", center=[0, width / 2], width=width, orientation=180, layer=layer + #) + + # Placement + mos_spacing = pdk.util_max_metal_seperation() + #mos_spacing = pdk.get_grule("met1")["min_width"]) + if flip_config["degree"] != None: + pfet_ref.rotate(flip_config["degree"]) + nfet_ref.rotate(flip_config["degree"]) + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + # Routing + # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG + # a) PMOS.source connected to NMOS.source + # b) PMOS.drain connected to NMOS.drain + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_source_E"]) # "in" of the TG + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_drain_E"]) # "out" of the TG + + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + # To define the layers + gds_met1 = pdk.get_glayer("met2")[0] + gds_met2 = gds_met1+1 + gds_met3 = gds_met2+1 + gds_met4 = gds_met3+1 + gds_met5 = gds_met4+1 + # To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port + tg_din_portLayer = top_level.ports["pmos_multiplier_0_source_W"].layer[0] + tg_dout_portLayer = top_level.ports["pmos_multiplier_0_drain_E"].layer[0] + # To create the pins w/ labels and append to info list + tg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) + tg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy() + tg_din_pin.add_label(text="Vin", layer=(tg_din_portLayer, 5)) + tg_dout_pin.add_label(text="Vout", layer=(tg_dout_portLayer, 5)) + pins_labels_info.append((tg_din_pin, top_level.ports["pmos_multiplier_0_source_W"], None)) + pins_labels_info.append((tg_dout_pin, top_level.ports["pmos_multiplier_0_drain_E"], None)) + + #print(top_level.ports["pmos_multiplier_0_source_W"].name) + #top_level.pprint_ports() + + # Move everythin to position + for comp, prt, alignment in pins_labels_info: + alignment = ('c', 'b') if alignment is None else alignment + compref = align_comp_to_port(comp, prt, alignment=alignment) + #top_level.add(compref) + + return top_level #top_level.flatten() + +def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): + # To prepare all necessary cells to construct a transmission gate, i.e. + # 1) transmission gate + # 2) Inverter + tg = naive_tg_cell(pdk=pdk, flip_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) + inv = reconfig_inv(pdk=pdk, component_name="gate_ctrl_inv", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="horizontal") + + # Instantiation of the essential cells + top_level = Component(name="tg_with_inv") + tg_ref = prec_ref_center(tg) + inv_ref = prec_ref_center(inv) + top_level.add(tg_ref) + top_level.add(inv_ref) + + # Adding the ports + top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") + top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") + + # Placement + mos_spacing = pdk.util_max_metal_seperation() + nwell_min_spacing = pdk.get_grule("nwell")["min_separation"] + inv_cell_width = inv_ref.xsize # or = evaluate_bbox(inv)[0] + tg_ref.movex(inv_cell_width + nwell_min_spacing) + + # Routing + #top_level << smart + #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG + #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG + return top_level #top_level.flatten() tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15).show() From ecabeed291c7171c48ec30b94489a1145a62a1e1 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 10 Nov 2024 15:08:10 +0000 Subject: [PATCH 07/21] Complete routing of the TG w/ an inverter for controlling the gates of the TG's PMOS and NMOS Next step: to add the I/O ports for the upcoming LVS work --- .../transmission_gate_saltychip/inv_lib.py | 12 ++++++------ .../transmission_gate.py | 18 ++++++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py index bd0f3eb87..6a1347ced 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py @@ -15,8 +15,8 @@ def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_w # Create a top level component top_level = Component(component_name) # To prepare one PMOS and one NMOS for the subsequent inverter cell construction - pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) # Instantiation of above PMOS and NMOS under the top level pfet_ref = prec_ref_center(pfet) @@ -24,10 +24,6 @@ def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_w top_level.add(pfet_ref) top_level.add(nfet_ref) - # To add the ports - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - # Placement (relative move) mos_spacing = pdk.util_max_metal_seperation() if(orientation=="horizontal"): @@ -41,4 +37,8 @@ def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_w top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"]) top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"]) + # To add the ports + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + return top_level diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 043f12b9a..f9b1a4f6d 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -105,8 +105,8 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) + pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) # Placement and adding ports top_level = Component(name="TG") @@ -114,11 +114,6 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) top_level.add(nfet_ref) - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - #top_level.add_port( - # name="", center=[0, width / 2], width=width, orientation=180, layer=layer - #) # Placement mos_spacing = pdk.util_max_metal_seperation() @@ -135,6 +130,12 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_source_E"]) # "in" of the TG top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_drain_E"]) # "out" of the TG + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + #top_level.add_port( + # name="", center=[0, width / 2], width=width, orientation=180, layer=layer + #) + # Add pins and text labels for LVS pins_labels_info = list() # list that contains all port and component information # To define the layers @@ -190,7 +191,8 @@ def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length tg_ref.movex(inv_cell_width + nwell_min_spacing) # Routing - #top_level << smart + top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_E"], tg_ref.ports["pmos_multiplier_0_gate_W"]) + top_level << smart_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"]) #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG From 929bf0b1ebb3607cb2ab7f43c010c1b785e3b44c Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 10 Nov 2024 15:22:12 +0000 Subject: [PATCH 08/21] Add the first draft of layout report and GDS w/o I/O port yet --- .../gds/tg_with_inv.gds | Bin 0 -> 60798 bytes .../report/figures/tg_with_inv.png | Bin 0 -> 107783 bytes .../transmission_gate.py | 9 ++++++++- 3 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_inv.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/report/figures/tg_with_inv.png diff --git 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Subject: [PATCH 09/21] Add the external I/O ports for the transmission gate --- .../transmission_gate_saltychip/__init__.py | 2 + .../cell_config.py | 67 ++++++++++++++++++ .../transmission_gate_saltychip/eval.py | 40 +++++++++++ .../gds/tg_with_inv.gds | Bin 60798 -> 61684 bytes .../report/figures/tg_with_inv.png | Bin 107783 -> 99588 bytes .../transmission_gate.py | 22 +++--- 6 files changed, 117 insertions(+), 14 deletions(-) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py index 841af6bae..813e096a6 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py @@ -1,2 +1,4 @@ from glayout.flow.blocks.transmission_gate_saltychip.inv_lib import reconfig_inv from glayout.flow.blocks.transmission_gate_saltychip.transmission_gate import tg_with_inv +from glayout.flow.blocks.transmission_gate_saltychip.cell_config import add_port_lvs +from glayout.flow.blocks.transmission_gate_saltychip.eval import main diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py new file mode 100644 index 000000000..915d85688 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py @@ -0,0 +1,67 @@ +from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +from glayout.flow.pdk.mappedpdk import MappedPDK +from glayout.flow.pdk.util.comp_utils import evaluate_bbox +from gdsfactory import Component +from gdsfactory.components import rectangle +from glayout.flow.primitives.fet import pmos +from glayout.flow.primitives.fet import nmos +from glayout.flow.routing.straight_route import straight_route +from glayout.flow.routing.c_route import c_route +from glayout.flow.routing.L_route import L_route +from glayout.flow.routing.smart_route import smart_route +from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized +from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized +from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port + +def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ]) -> Component: + ''' + To add external I/O ports onto the cell for LVS + + @ args: + # pdk: please refer to the glayout library + # comp: please refer to the glayout library + # port_list: tuple[ dict[str, Union[float, str]] ] specifying new port's corresponding pin size, and + the name of new port and exiting port managed to align with in the given + component, e.g. + ( + { + "new_port": "drain_new", + "new_port_label": "drain_new_label", + "pin_width": 0.5, + "pin_height": 0.5, + "ref_port": "multiplier_0_drain_E" + }, + { + "new_port": "source_new", + "new_port_label": "source_new_label", + "pin_width": 1.5, + "pin_height": 1.5, + "ref_port": "multiplier_0_source_E" + } + ) + + # return: gdsfactory.Component + + @ Limitations: + # So far, only skywater130 process is validated + ''' + + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + print(f"port_list: {port_list}") + for port in port_list: + # To get the layer's data type mapped to the GDS + ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc. + + # To create the pin w/ label where the layer[1] is mapped to 16 + new_port_pin = rectangle(layer=(ref_port_layer, 16), size=(port["pin_width"], port["pin_height"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) + new_port_pin.add_label(text=port["new_port_label"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the "label" datatype in the GDS + + # To align the new port with the designated port existing in the given component + alignment = ('c', 'b') + comp_ref = align_comp_to_port(new_port_pin, comp.ports[ port["ref_port"] ], alignment=alignment) + comp.add(comp_ref) + + return comp \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py new file mode 100644 index 000000000..66b15b77c --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -0,0 +1,40 @@ +import transmission_gate as tg +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +import cell_config as config + +def main(): + tg_inst = tg.tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15) + tg_inst = config.add_port_lvs( + pdk=sky130, + comp=tg_inst, + port_list=[ + { + "new_port": "tg_ctrl", + "new_port_label": "ctrl", + "pin_width": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, + "pin_height": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, + "ref_port": "inv_nmos_multiplier_0_gate_S" + }, + { + "new_port": "tg_din", + "new_port_label": "din", + "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, + "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, + "ref_port": "tg_pmos_multiplier_0_source_W" + }, + { + "new_port": "tg_dout", + "new_port_label": "dout", + "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, + "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, + "ref_port": "tg_nmos_multiplier_0_drain_N" + } + ] + ) + #tg_inst.flatten() + tg_inst.show() + tg_inst.write_gds("gds/tg_with_inv.gds") + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_inv.gds b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_inv.gds index 4f9d91f6cad27cd70607190ca75db6d98c2297ba..0e475572f10bbac3c96f480c5c96fe5822d2c0ea 100644 GIT binary patch delta 871 zcmex&i}}k#<_#Q-^;`@LB0_ATd3lMssVVV>DF!J?DQQUzJOa!N42)9$|NpCEU=d_s zU_n)9YGILev|=WLTNlCwDVS`y}V* z79>)ZlQ`H&`LvL5jI4; zKrP#>RTXHBB4J`|W@wz8Hd(7`%I3IjTUj^ryK@ zzz|iPY-=ktS@*5qYSzVF8d}BQsgYP8R4&uE}?85|E96Yv9@zvUy(>Fp&1Ma~pB2OfFAtOJWYSmFgnoy+9Dt-j1GEDQinQtj6O delta 229 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Subject: [PATCH 10/21] Create a Colab notebook generating and displaying the transmission gate's GDSII image, according to the main layout work in "transmission_gate.py" and "eval.py". --- .../transmission_gate_saltychip/tg_gen.ipynb | 2326 +++++++++++++++++ 1 file changed, 2326 insertions(+) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb new file mode 100644 index 000000000..45d4fc14b --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb @@ -0,0 +1,2326 @@ +{ + "nbformat": 4, + "nbformat_minor": 0, + "metadata": { + "colab": { + "provenance": [], + "include_colab_link": true + }, + "kernelspec": { + "name": "python3", + "display_name": "Python 3" + }, + "language_info": { + "name": "python" + } + }, + "cells": [ + { + "cell_type": "markdown", + "metadata": { + "id": "view-in-github", + "colab_type": "text" + }, + "source": [ + "\"Open" + ] + }, + { + "cell_type": "markdown", + "source": [ + "#Chipathon2024　SaltyChip Group\n", + "##テグさんのトランスミッションゲートをnotebbokで表示されるようにしてみた。\n", + "最初にOpenFASoCをクーロンして、sky130、gf180、gdsfactoryをインストールします。\n", + "micromambaを使ったバイナリ依存klayoutをインストールします。\n", + "\n", + "\n", + "\n", + "* Chipathon2024 GitHub:\n", + "https://github.com/sscs-ose/sscs-ose-chipathon.github.io\n", + "\n", + "\n", + "\n", + "\n", + "\n" + ], + "metadata": { + "id": "o2n-cd6kYdjt" + } + }, + { + "cell_type": "code", + "execution_count": 4, + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "id": "2fBvSrYFYB1K", + "outputId": "90eb55c6-a4e2-42cf-966d-e79c278aaf28" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Cloning into 'OpenFASOC'...\n", + "remote: Enumerating objects: 16501, done.\u001b[K\n", + "remote: Counting objects: 100% (3739/3739), done.\u001b[K\n", + "remote: Compressing objects: 100% (549/549), done.\u001b[K\n", + "remote: Total 16501 (delta 3311), reused 3398 (delta 3185), pack-reused 12762 (from 1)\u001b[K\n", + "Receiving objects: 100% (16501/16501), 410.32 MiB | 20.14 MiB/s, done.\n", + "Resolving deltas: 100% (10104/10104), done.\n", + "Updating files: 100% (1849/1849), done.\n", + "Collecting sky130\n", + " Downloading sky130-0.12.2-py3-none-any.whl.metadata (1.6 kB)\n", + "Collecting gdsfactory~=8.5.2 (from sky130)\n", + " Downloading gdsfactory-8.5.6-py3-none-any.whl.metadata (11 kB)\n", + "Collecting PySpice (from sky130)\n", + " Downloading PySpice-1.5-py2.py3-none-any.whl.metadata (15 kB)\n", + "Requirement already satisfied: jinja2<4 in /usr/local/lib/python3.10/dist-packages (from gdsfactory~=8.5.2->sky130) (3.1.4)\n", + "Collecting loguru<1 (from gdsfactory~=8.5.2->sky130)\n", + " Downloading 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spectate-1.0.1-py2.py3-none-any.whl (11 kB)\n", + "Building wheels for collected packages: flatdict\n", + " Building wheel for flatdict (setup.py) ... \u001b[?25l\u001b[?25hdone\n", + " Created wheel for flatdict: filename=flatdict-4.0.1-py3-none-any.whl size=6928 sha256=cbe7b9ecdeb813ed4b936db444d4d7b1e3115b3811fed30a7561ac5da3fd548a\n", + " Stored in directory: /root/.cache/pip/wheels/71/12/62/88c5bf37619c2d7481eedb8abd0dde6674e88dce45a7805a6f\n", + "Successfully built flatdict\n", + "Installing collected packages: pyglet, flatdict, trimesh, svgutils, spectate, pydantic-core, gdstk, colorama, cmd2, pydantic, prettyprinttree, pydantic-settings, kfactory, ipympl, ipycytoscape, gdsfactory, gf180\n", + " Attempting uninstall: trimesh\n", + " Found existing installation: trimesh 4.4.9\n", + " Uninstalling trimesh-4.4.9:\n", + " Successfully uninstalled trimesh-4.4.9\n", + " Attempting uninstall: pydantic-core\n", + " Found existing installation: pydantic_core 2.20.1\n", + " Uninstalling pydantic_core-2.20.1:\n", + " Successfully uninstalled pydantic_core-2.20.1\n", + " Attempting uninstall: pydantic\n", + " Found existing installation: pydantic 2.8.2\n", + " Uninstalling pydantic-2.8.2:\n", + " Successfully uninstalled pydantic-2.8.2\n", + " Attempting uninstall: pydantic-settings\n", + " Found existing installation: pydantic-settings 2.6.1\n", + " Uninstalling pydantic-settings-2.6.1:\n", + " Successfully uninstalled pydantic-settings-2.6.1\n", + " Attempting uninstall: kfactory\n", + " Found existing installation: kfactory 0.18.4\n", + " Uninstalling kfactory-0.18.4:\n", + " Successfully uninstalled kfactory-0.18.4\n", + " Attempting uninstall: gdsfactory\n", + " Found existing installation: gdsfactory 8.5.6\n", + " Uninstalling gdsfactory-8.5.6:\n", + " Successfully uninstalled gdsfactory-8.5.6\n", + "\u001b[31mERROR: pip's dependency resolver does not currently take into account all the packages that are installed. This behaviour is the source of the following dependency conflicts.\n", + "albumentations 1.4.20 requires pydantic>=2.7.0, but you have pydantic 2.6.4 which is incompatible.\n", + "langchain 0.3.7 requires pydantic<3.0.0,>=2.7.4, but you have pydantic 2.6.4 which is incompatible.\n", + "sky130 0.12.2 requires gdsfactory~=8.5.2, but you have gdsfactory 7.16.0 which is incompatible.\u001b[0m\u001b[31m\n", + "\u001b[0mSuccessfully installed cmd2-2.5.5 colorama-0.4.6 flatdict-4.0.1 gdsfactory-7.16.0 gdstk-0.9.57 gf180-0.1.0 ipycytoscape-1.3.3 ipympl-0.9.4 kfactory-0.11.4 prettyprinttree-2.0.1 pydantic-2.6.4 pydantic-core-2.16.3 pydantic-settings-2.2.1 pyglet-1.5.29 spectate-1.0.1 svgutils-0.3.4 trimesh-4.1.8\n", + "Collecting gdsfactory==7.7.0\n", + " Downloading gdsfactory-7.7.0-py3-none-any.whl.metadata (10 kB)\n", + "Requirement already satisfied: flatdict in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.0.1)\n", + "Requirement already satisfied: gdstk<1 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.9.57)\n", + "Requirement already satisfied: jinja2 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.1.4)\n", + "Requirement already satisfied: loguru<1 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.7.2)\n", + "Requirement already satisfied: matplotlib in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.8.0)\n", + "Requirement already satisfied: numpy in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (1.26.4)\n", + "Requirement already satisfied: omegaconf<3 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.3.0)\n", + "Requirement already satisfied: orjson in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.10.11)\n", + "Requirement already satisfied: pandas in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.2.2)\n", + "Requirement already satisfied: pydantic<3,>=2 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.6.4)\n", + "Requirement already satisfied: pydantic-settings in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.2.1)\n", + "Requirement already satisfied: pydantic-extra-types in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.10.0)\n", + "Requirement already satisfied: pyyaml in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (6.0.2)\n", + "Requirement already satisfied: qrcode in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (8.0)\n", + "Requirement already satisfied: rectpack in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.2.2)\n", + "Requirement already satisfied: rich in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (13.9.4)\n", + "Requirement already satisfied: scipy in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (1.13.1)\n", + "Requirement already satisfied: shapely<3 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.0.6)\n", + "Requirement already satisfied: toolz in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.12.1)\n", + "Requirement already satisfied: tqdm in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.66.6)\n", + "Requirement already satisfied: types-PyYAML in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (6.0.12.20240917)\n", + "Requirement already satisfied: typer in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.13.0)\n", + "Requirement already satisfied: watchdog in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.0.2)\n", + "Requirement already satisfied: typing_extensions in /usr/local/lib/python3.10/dist-packages (from gdstk<1->gdsfactory==7.7.0) (4.12.2)\n", + "Requirement already satisfied: antlr4-python3-runtime==4.9.* in /usr/local/lib/python3.10/dist-packages (from omegaconf<3->gdsfactory==7.7.0) (4.9.3)\n", + "Requirement already satisfied: annotated-types>=0.4.0 in /usr/local/lib/python3.10/dist-packages (from pydantic<3,>=2->gdsfactory==7.7.0) (0.7.0)\n", + "Requirement already satisfied: pydantic-core==2.16.3 in /usr/local/lib/python3.10/dist-packages (from pydantic<3,>=2->gdsfactory==7.7.0) (2.16.3)\n", + "Requirement already satisfied: MarkupSafe>=2.0 in /usr/local/lib/python3.10/dist-packages (from jinja2->gdsfactory==7.7.0) (3.0.2)\n", + "Requirement already satisfied: contourpy>=1.0.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (1.3.0)\n", + "Requirement already satisfied: cycler>=0.10 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (0.12.1)\n", + "Requirement already satisfied: fonttools>=4.22.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (4.54.1)\n", + "Requirement already satisfied: kiwisolver>=1.0.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (1.4.7)\n", + "Requirement already satisfied: packaging>=20.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (24.2)\n", + "Requirement already satisfied: pillow>=6.2.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (11.0.0)\n", + "Requirement already satisfied: pyparsing>=2.3.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (3.2.0)\n", + "Requirement already satisfied: python-dateutil>=2.7 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (2.8.2)\n", + "Requirement already satisfied: pytz>=2020.1 in /usr/local/lib/python3.10/dist-packages (from pandas->gdsfactory==7.7.0) (2024.2)\n", + "Requirement already satisfied: tzdata>=2022.7 in /usr/local/lib/python3.10/dist-packages (from pandas->gdsfactory==7.7.0) (2024.2)\n", + "Requirement already satisfied: python-dotenv>=0.21.0 in /usr/local/lib/python3.10/dist-packages (from pydantic-settings->gdsfactory==7.7.0) (1.0.1)\n", + "Requirement already satisfied: markdown-it-py>=2.2.0 in /usr/local/lib/python3.10/dist-packages (from rich->gdsfactory==7.7.0) (3.0.0)\n", + "Requirement already satisfied: pygments<3.0.0,>=2.13.0 in /usr/local/lib/python3.10/dist-packages (from rich->gdsfactory==7.7.0) (2.18.0)\n", + "Requirement already satisfied: click>=8.0.0 in /usr/local/lib/python3.10/dist-packages (from typer->gdsfactory==7.7.0) (8.1.7)\n", + "Requirement already satisfied: shellingham>=1.3.0 in /usr/local/lib/python3.10/dist-packages (from typer->gdsfactory==7.7.0) (1.5.4)\n", + "Requirement already satisfied: mdurl~=0.1 in /usr/local/lib/python3.10/dist-packages (from markdown-it-py>=2.2.0->rich->gdsfactory==7.7.0) (0.1.2)\n", + "Requirement already satisfied: six>=1.5 in /usr/local/lib/python3.10/dist-packages (from python-dateutil>=2.7->matplotlib->gdsfactory==7.7.0) (1.16.0)\n", + "Downloading gdsfactory-7.7.0-py3-none-any.whl (801 kB)\n", + "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m801.2/801.2 kB\u001b[0m \u001b[31m16.0 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", + "\u001b[?25hInstalling collected packages: gdsfactory\n", + " Attempting uninstall: gdsfactory\n", + " Found existing installation: gdsfactory 7.16.0\n", + " Uninstalling gdsfactory-7.16.0:\n", + " Successfully uninstalled gdsfactory-7.16.0\n", + "\u001b[31mERROR: pip's dependency resolver does not currently take into account all the packages that are installed. This behaviour is the source of the following dependency conflicts.\n", + "gf180 0.1.0 requires gdsfactory<7.17,>=7.16.0, but you have gdsfactory 7.7.0 which is incompatible.\n", + "sky130 0.12.2 requires gdsfactory~=8.5.2, but you have gdsfactory 7.7.0 which is incompatible.\u001b[0m\u001b[31m\n", + "\u001b[0mSuccessfully installed gdsfactory-7.7.0\n", + "bin/micromamba\n", + "env: CONDA_PREFIX=/content/conda-env\n", + "Empty environment created at prefix: /content/conda-env\n", + "\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", + "\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", + "litex-hub/linux-64.. ⣾ \n", + "litex-hub/noarch (.. ⣾ \n", + "main/linux-64 (che.. ⣾ \n", + "main/noarch (check.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", + "litex-hub/linux-64.. ⣾ \n", + "litex-hub/noarch (.. ⣾ \n", + "main/linux-64 (che.. ⣾ \n", + "main/noarch (check.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", + "litex-hub/linux-64.. ⣾ \n", + "litex-hub/noarch (.. ⣾ \n", + "main/linux-64 (che.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.4s\n", + "litex-hub/noarch (.. ⣾ \n", + "main/linux-64 (che.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", + "litex-hub/noarch (.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[0G\u001b[?25h\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", + "\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", + "litex-hub/linux-64 | \n", + "litex-hub/noarch ⣾ \n", + "main/linux-64 ⣾ \n", + "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", + "litex-hub/linux-64 | \n", + "litex-hub/noarch ⣾ \n", + "main/linux-64 ⣾ \n", + "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", + "litex-hub/linux-64 | \n", + "litex-hub/noarch ⣾ \n", + "main/linux-64 ⣾ \n", + "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glitex-hub/noarch \n", + "[+] 0.4s\n", + "litex-hub/linux-64 | \n", + "main/linux-64 ⣾ \n", + "main/noarch 3%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", + "litex-hub/linux-64 | \n", + "main/linux-64 2%\n", + "main/noarch 15%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.6s\n", + "litex-hub/linux-64 | \n", + "main/linux-64 9%\n", + "main/noarch 36%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gmain/noarch \n", + "[+] 0.7s\n", + "litex-hub/linux-64 | \n", + "main/linux-64 11%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.8s\n", + "litex-hub/linux-64 3%\n", + "main/linux-64 42%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.9s\n", + "litex-hub/linux-64 27%\n", + "main/linux-64 83%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gmain/linux-64 \n", + "[+] 1.0s\n", + "litex-hub/linux-64 57%\u001b[2K\u001b[1A\u001b[2K\u001b[0Glitex-hub/linux-64 \n", + "\u001b[?25h\n", + "\u001b[31m\u001b[1merror libmamba\u001b[m Could not lock non-existing path '/root/.mamba/pkgs'\n", + "\n", + "Transaction\n", + "\n", + " Prefix: /content/conda-env\n", + "\n", + " Updating specs:\n", + "\n", + " - klayout\n", + "\n", + "\n", + " Package Version Build Channel Size\n", + "─────────────────────────────────────────────────────────────────────────────────────────\n", + " Install:\n", + "─────────────────────────────────────────────────────────────────────────────────────────\n", + "\n", + " \u001b[32m+ _libgcc_mutex \u001b[0m 0.1 main main 3kB\n", + " \u001b[32m+ _openmp_mutex \u001b[0m 5.1 1_gnu main 21kB\n", + " \u001b[32m+ bzip2 \u001b[0m 1.0.8 h5eee18b_6 main 428kB\n", + " \u001b[32m+ c-ares \u001b[0m 1.19.1 h5eee18b_0 main 116kB\n", + " \u001b[32m+ ca-certificates \u001b[0m 2024.9.24 h06a4308_0 main 140kB\n", + " \u001b[32m+ certifi \u001b[0m 2022.12.7 py37h06a4308_0 main 155kB\n", + " \u001b[32m+ curl \u001b[0m 8.2.1 h37d81fd_0 main 89kB\n", + " \u001b[32m+ dbus \u001b[0m 1.13.18 hb2f20db_0 main 600kB\n", + " \u001b[32m+ expat \u001b[0m 2.6.3 h6a678d5_0 main 201kB\n", + " \u001b[32m+ fontconfig \u001b[0m 2.13.0 h9420a91_0 main 298kB\n", + " \u001b[32m+ freetype \u001b[0m 2.12.1 h4a9f257_0 main 972kB\n", + " \u001b[32m+ glib \u001b[0m 2.78.4 h6a678d5_0 main 499kB\n", + " \u001b[32m+ glib-tools \u001b[0m 2.78.4 h6a678d5_0 main 113kB\n", + " \u001b[32m+ gmp \u001b[0m 6.2.1 h295c915_3 main 822kB\n", + " \u001b[32m+ gst-plugins-base\u001b[0m 1.14.1 h6a678d5_1 main 2MB\n", + " \u001b[32m+ gstreamer \u001b[0m 1.14.1 h5eee18b_1 main 2MB\n", + " \u001b[32m+ icu \u001b[0m 58.2 he6710b0_3 main 24MB\n", + " \u001b[32m+ jpeg \u001b[0m 9e h5eee18b_3 main 284kB\n", + " \u001b[32m+ klayout \u001b[0m 0.28.17_212_gfa14afbbf 20240223_100318_py37 litex-hub 27MB\n", + " \u001b[32m+ krb5 \u001b[0m 1.20.1 h568e23c_1 main 1MB\n", + " \u001b[32m+ ld_impl_linux-64\u001b[0m 2.40 h12ee557_0 main 723kB\n", + " \u001b[32m+ libcurl \u001b[0m 8.2.1 h91b91d3_0 main 386kB\n", + " \u001b[32m+ libedit \u001b[0m 3.1.20230828 h5eee18b_0 main 196kB\n", + " \u001b[32m+ libev \u001b[0m 4.33 h7f8727e_1 main 109kB\n", + " \u001b[32m+ libffi \u001b[0m 3.4.4 h6a678d5_1 main 154kB\n", + " \u001b[32m+ libgcc-ng \u001b[0m 11.2.0 h1234567_1 main 9MB\n", + " \u001b[32m+ libgit2 \u001b[0m 1.6.4 ha637b67_0 main 1MB\n", + " \u001b[32m+ libglib \u001b[0m 2.78.4 hdc74915_0 main 2MB\n", + " \u001b[32m+ libgomp \u001b[0m 11.2.0 h1234567_1 main 573kB\n", + " \u001b[32m+ libiconv \u001b[0m 1.16 h5eee18b_3 main 1MB\n", + " \u001b[32m+ libnghttp2 \u001b[0m 1.52.0 ha637b67_1 main 717kB\n", + " \u001b[32m+ libpng \u001b[0m 1.6.39 h5eee18b_0 main 363kB\n", + " \u001b[32m+ libssh2 \u001b[0m 1.10.0 h37d81fd_2 main 312kB\n", + " \u001b[32m+ libstdcxx-ng \u001b[0m 11.2.0 h1234567_1 main 6MB\n", + " \u001b[32m+ libuuid \u001b[0m 1.41.5 h5eee18b_0 main 29kB\n", + " \u001b[32m+ libxcb \u001b[0m 1.15 h7f8727e_0 main 623kB\n", + " \u001b[32m+ libxml2 \u001b[0m 2.9.9 20220706_155948 litex-hub 1MB\n", + " \u001b[32m+ ncurses \u001b[0m 6.4 h6a678d5_0 main 1MB\n", + " \u001b[32m+ openssl \u001b[0m 1.1.1w h7f8727e_0 main 4MB\n", + " \u001b[32m+ pcre2 \u001b[0m 10.42 hebb0a14_1 main 3MB\n", + " \u001b[32m+ pip \u001b[0m 22.3.1 py37h06a4308_0 main 3MB\n", + " \u001b[32m+ python \u001b[0m 3.7.16 h7a1cb2a_0 main 49MB\n", + " \u001b[32m+ qt \u001b[0m 5.9.7 h5867ecd_1 main 90MB\n", + " \u001b[32m+ readline \u001b[0m 8.2 h5eee18b_0 main 468kB\n", + " \u001b[32m+ ruby \u001b[0m 2.5.1 haf1161a_0 main 5MB\n", + " \u001b[32m+ setuptools \u001b[0m 65.6.3 py37h06a4308_0 main 1MB\n", + " \u001b[32m+ sqlite \u001b[0m 3.45.3 h5eee18b_0 main 2MB\n", + " \u001b[32m+ tk \u001b[0m 8.6.14 h39e8969_0 main 4MB\n", + " \u001b[32m+ wheel \u001b[0m 0.38.4 py37h06a4308_0 main 59kB\n", + " \u001b[32m+ xz \u001b[0m 5.4.6 h5eee18b_1 main 717kB\n", + " \u001b[32m+ yaml \u001b[0m 0.1.7 had09818_2 main 87kB\n", + " \u001b[32m+ zlib \u001b[0m 1.2.13 h5eee18b_1 main 127kB\n", + "\n", + " Summary:\n", + "\n", + " Install: 52 packages\n", + "\n", + " Total download: 249MB\n", + "\n", + "─────────────────────────────────────────────────────────────────────────────────────────\n", + "\n", + "\n", + "\n", + "Transaction starting\n", + "\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", + "Downloading 5%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.4s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.6s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.7s\n", + "Downloading (5) 0%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.8s\n", + "Downloading (5) 1%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.9s\n", + "Downloading (5) 1%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.0s\n", + "Downloading (5) 1%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.1s\n", + "Downloading (5) 3%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.2s\n", + "Downloading (5) 6%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgcc-ng 8.9MB @ 7.4MB/s 1.2s\n", + "[+] 1.3s\n", + "Downloading (5) 10%\n", + "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.4s\n", + "Downloading (5) 13%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.5s\n", + "Downloading (5) 18%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.6s\n", + "Downloading (5) 23%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.7s\n", + "Downloading (5) 31%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.8s\n", + "Downloading (5) 39%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gklayout 26.7MB @ 14.3MB/s 1.8s\n", + "[+] 1.9s\n", + "Downloading (5) 43%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.0s\n", + "Downloading (5) 45%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gicu 23.8MB @ 11.7MB/s 2.0s\n", + "[+] 2.1s\n", + "Downloading (5) 47%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.2s\n", + "Downloading (5) 49%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.3s\n", + "Downloading (5) 52%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibstdcxx-ng 6.4MB @ 4.6MB/s 1.2s\n", + "[+] 2.4s\n", + "Downloading (5) 58%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.5s\n", + "Downloading (5) 61%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.6s\n", + "Downloading (5) 65%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.7s\n", + "Downloading (5) 68%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.8s\n", + "Downloading (5) 70%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpython 48.7MB @ 16.5MB/s 2.8s\n", + "[+] 2.9s\n", + "Downloading (5) 72%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.0s\n", + "Downloading (5) 74%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.1s\n", + "Downloading (5) 75%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.2s\n", + "Downloading (5) 78%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.3s\n", + "Downloading (5) 80%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gopenssl 4.0MB @ 2.9MB/s 1.3s\n", + "ruby 5.3MB @ 3.1MB/s 1.4s\n", + "[+] 3.4s\n", + "Downloading (5) 80%\n", + "Extracting (5) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.5s\n", + "Downloading (5) 80%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.6s\n", + "Downloading (5) 81%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.7s\n", + "Downloading (5) 83%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gtk 3.6MB @ 2.4MB/s 1.4s\n", + "[+] 3.8s\n", + "Downloading (5) 84%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpcre2 3.3MB @ 3.2MB/s 1.0s\n", + "[+] 3.9s\n", + "Downloading (5) 85%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.0s\n", + "Downloading (5) 86%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.1s\n", + "Downloading (5) 87%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.2s\n", + "Downloading (5) 88%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.3s\n", + "Downloading (5) 88%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.4s\n", + "Downloading (5) 89%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.5s\n", + "Downloading (5) 92%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpip 2.8MB @ 2.2MB/s 1.2s\n", + "[+] 4.6s\n", + "Downloading (5) 93%\n", + "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Ggst-plugins-base 2.3MB @ 1.6MB/s 1.3s\n", + "[+] 4.7s\n", + "Downloading (5) 94%\n", + "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gsqlite 1.7MB @ 1.5MB/s 0.9s\n", + "gstreamer 1.7MB @ 1.8MB/s 0.9s\n", + "[+] 4.8s\n", + "Downloading (5) 96%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.9s\n", + "Downloading (5) 96%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.0s\n", + "Downloading (5) 97%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gqt 90.0MB @ 17.8MB/s 5.0s\n", + "[+] 5.1s\n", + "Downloading (5) 97%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.2s\n", + "Downloading (5) 97%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.3s\n", + "Downloading (5) 98%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibglib 1.6MB @ 932.0kB/s 0.9s\n", + "[+] 5.4s\n", + "Downloading (5) 98%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.5s\n", + "Downloading (5) 98%\n", + "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.6s\n", + "Downloading (5) 98%\n", + "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gsetuptools 1.4MB @ 987.1kB/s 1.0s\n", + "libiconv 1.4MB @ 850.5kB/s 1.0s\n", + "krb5 1.4MB @ 849.1kB/s 0.9s\n", + "[+] 5.7s\n", + "Downloading (5) 98%\n", + "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.8s\n", + "Downloading (5) 98%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.9s\n", + "Downloading (5) 99%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibxml2 1.4MB @ 834.9kB/s 0.9s\n", + "[+] 6.0s\n", + "Downloading (5) 98%\n", + "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.1s\n", + "Downloading (5) 98%\n", + "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.2s\n", + "Downloading (5) 99%\n", + "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.3s\n", + "Downloading (5) 99%\n", + "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgit2 1.2MB @ 804.6kB/s 1.0s\n", + "[+] 6.4s\n", + "Downloading (5) 99%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.5s\n", + "Downloading (5) 99%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gncurses 1.2MB @ 937.3kB/s 0.9s\n", + "freetype 972.0kB @ 896.8kB/s 0.9s\n", + "[+] 6.6s\n", + "Downloading (5) 99%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.7s\n", + "Downloading (5) 99%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.8s\n", + "Downloading (5) 99%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Ggmp 822.4kB @ 698.3kB/s 1.1s\n", + "[+] 6.9s\n", + "Downloading (5) 99%\n", + "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gld_impl_linux-64 723.1kB @ 375.9kB/s 1.0s\n", + "[+] 7.0s\n", + "Downloading (5) 99%\n", + "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.1s\n", + "Downloading (5) 99%\n", + "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.2s\n", + "Downloading (5) 99%\n", + "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibxcb 623.5kB @ 577.3kB/s 0.7s\n", + "libnghttp2 716.6kB @ 539.0kB/s 0.8s\n", + "xz 716.9kB @ 446.2kB/s 0.9s\n", + "[+] 7.3s\n", + "Downloading (5) 99%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.4s\n", + "Downloading (5) 99%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.5s\n", + "Downloading (5) 99%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.6s\n", + "Downloading (5) 99%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.7s\n", + "Downloading (5) 99%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.8s\n", + "Downloading (5) 100%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgomp 573.2kB @ 429.0kB/s 0.9s\n", + "[+] 7.9s\n", + "Downloading (5) 100%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gdbus 600.2kB @ 313.4kB/s 1.1s\n", + "[+] 8.0s\n", + "Downloading (5) 100%\n", + "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.1s\n", + "Downloading (5) 100%\n", + "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gglib 499.0kB @ 409.8kB/s 0.9s\n", + "readline 467.7kB @ 420.7kB/s 0.9s\n", + "bzip2 427.5kB @ 433.5kB/s 0.9s\n", + "[+] 8.2s\n", + "Downloading (5) 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.3s\n", + "Downloading (5) 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.4s\n", + "Downloading (5) 100%\n", + "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.5s\n", + "Downloading (5) 100%\n", + "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.6s\n", + "Downloading (5) 100%\n", + "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibssh2 311.8kB @ ??.?MB/s 0.5s\n", + "[+] 8.7s\n", + "Downloading (5) 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibpng 362.6kB @ 468.9kB/s 0.8s\n", + "[+] 8.8s\n", + "Downloading (5) 100%\n", + "Extracting (31) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gfontconfig 297.6kB @ 429.9kB/s 0.7s\n", + "libcurl 386.4kB @ 406.6kB/s 1.0s\n", + "[+] 8.9s\n", + "Downloading (5) 100%\n", + "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gjpeg 283.5kB @ 240.5kB/s 0.7s\n", + "[+] 9.0s\n", + "Downloading (5) 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.1s\n", + "Downloading (5) 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.2s\n", + "Downloading (5) 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.3s\n", + "Downloading (5) 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.4s\n", + "Downloading (5) 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gexpat 200.8kB @ 178.1kB/s 0.8s\n", + "[+] 9.5s\n", + "Downloading (5) 100%\n", + "Extracting (35) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibffi 154.0kB @ 111.1kB/s 0.7s\n", + "libedit 195.8kB @ 243.1kB/s 0.8s\n", + "[+] 9.6s\n", + "Downloading (5) 100%\n", + "Extracting (37) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gcertifi 155.3kB @ 150.2kB/s 0.8s\n", + "ca-certificates 139.9kB @ 91.3kB/s 0.7s\n", + "[+] 9.7s\n", + "Downloading (5) 100%\n", + "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.8s\n", + "Downloading (5) 100%\n", + "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.9s\n", + "Downloading (5) 100%\n", + "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gglib-tools 112.6kB @ 275.5kB/s 0.4s\n", + "[+] 10.0s\n", + "Downloading (5) 100%\n", + "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.1s\n", + "Downloading (5) 100%\n", + "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gzlib 127.1kB @ 105.1kB/s 0.7s\n", + "c-ares 116.3kB @ 115.3kB/s 0.7s\n", + "[+] 10.2s\n", + "Downloading (5) 100%\n", + "Extracting (41) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.3s\n", + "Downloading (5) 100%\n", + "Extracting (42) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.4s\n", + "Downloading (5) 100%\n", + "Extracting (42) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gyaml 87.1kB @ ??.?MB/s 0.4s\n", + "libev 108.9kB @ 77.3kB/s 0.8s\n", + "curl 88.8kB @ 80.9kB/s 0.8s\n", + "[+] 10.5s\n", + "Downloading (4) 100%\n", + "Extracting (45) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gwheel 58.7kB @ 79.1kB/s 0.4s\n", + "[+] 10.6s\n", + "Downloading (3) 100%\n", + "Extracting (46) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.7s\n", + "Downloading (3) 100%\n", + "Extracting (46) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibuuid 29.2kB @ 53.0kB/s 0.6s\n", + "[+] 10.8s\n", + "Downloading (2) 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G_libgcc_mutex 3.1kB @ 8.2kB/s 0.4s\n", + "[+] 10.9s\n", + "Downloading (1) 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.0s\n", + "Downloading (1) 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G_openmp_mutex 20.8kB @ 34.4kB/s 0.6s\n", + "[+] 11.1s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.2s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.3s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.4s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.5s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.6s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.7s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.8s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.9s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.0s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.1s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.2s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.3s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.4s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.5s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.6s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.7s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.8s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.9s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.0s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.1s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.2s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.3s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.4s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.5s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.6s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.7s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.8s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.9s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.0s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.1s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.2s\n", + "Downloading 100%\n", + "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.3s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.4s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.5s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.6s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.7s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.8s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.9s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.0s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.1s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.2s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.3s\n", + "Downloading 100%\n", + "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.4s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.5s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.6s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.7s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.8s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.9s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.0s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.1s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.2s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.3s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.4s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.5s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.6s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.7s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.8s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.9s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.0s\n", + "Downloading 100%\n", + "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.1s\n", + "Downloading 100%\n", + "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.2s\n", + "Downloading 100%\n", + "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.3s\n", + "Downloading 100%\n", + "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.4s\n", + "Downloading 100%\n", + "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.5s\n", + "Downloading 100%\n", + "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.6s\n", + "Downloading 100%\n", + "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.7s\n", + "Downloading 100%\n", + "Extracting (38) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.8s\n", + "Downloading 100%\n", + "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.9s\n", + "Downloading 100%\n", + "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.0s\n", + "Downloading 100%\n", + "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.1s\n", + "Downloading 100%\n", + "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.2s\n", + "Downloading 100%\n", + "Extracting (35) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.3s\n", + "Downloading 100%\n", + "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.4s\n", + "Downloading 100%\n", + "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.5s\n", + "Downloading 100%\n", + "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.6s\n", + "Downloading 100%\n", + "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.7s\n", + "Downloading 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.8s\n", + "Downloading 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.9s\n", + "Downloading 100%\n", + "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.0s\n", + "Downloading 100%\n", + "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.1s\n", + "Downloading 100%\n", + "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.2s\n", + "Downloading 100%\n", + "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.3s\n", + "Downloading 100%\n", + "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.4s\n", + "Downloading 100%\n", + "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.5s\n", + "Downloading 100%\n", + "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.6s\n", + "Downloading 100%\n", + "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.7s\n", + "Downloading 100%\n", + "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.8s\n", + "Downloading 100%\n", + "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.9s\n", + "Downloading 100%\n", + "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.0s\n", + "Downloading 100%\n", + "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.1s\n", + "Downloading 100%\n", + "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.2s\n", + "Downloading 100%\n", + "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.3s\n", + "Downloading 100%\n", + "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.4s\n", + "Downloading 100%\n", + "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.5s\n", + "Downloading 100%\n", + "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.6s\n", + "Downloading 100%\n", + "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.7s\n", + "Downloading 100%\n", + "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.8s\n", + "Downloading 100%\n", + "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.9s\n", + "Downloading 100%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.0s\n", + "Downloading 100%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.1s\n", + "Downloading 100%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.2s\n", + "Downloading 100%\n", + "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.3s\n", + "Downloading 100%\n", + "Extracting (20) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.4s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.5s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.6s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.7s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.8s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.9s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.0s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.1s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.2s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.3s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.4s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.5s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.6s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.7s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.8s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.9s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.0s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.1s\n", + "Downloading 100%\n", + "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.2s\n", + "Downloading 100%\n", + "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.4s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.5s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.6s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.7s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.8s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.9s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.0s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.1s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.2s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.3s\n", + "Downloading 100%\n", + "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.4s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.5s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.6s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.7s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.8s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.9s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.0s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.1s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.2s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.3s\n", + "Downloading 100%\n", + "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.4s\n", + "Downloading 100%\n", + "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.5s\n", + "Downloading 100%\n", + "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.6s\n", + "Downloading 100%\n", + "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.7s\n", + "Downloading 100%\n", + "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.8s\n", + "Downloading 100%\n", + "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.9s\n", + "Downloading 100%\n", + "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.0s\n", + "Downloading 100%\n", + "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.1s\n", + "Downloading 100%\n", + "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.2s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.3s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.4s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.5s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.6s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.7s\n", + "Downloading 100%\n", + "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.8s\n", + "Downloading 100%\n", + "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.9s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.0s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.1s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.2s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.3s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.4s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.5s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.6s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.7s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.8s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.9s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.0s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.1s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.2s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.3s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.4s\n", + "Downloading 100%\n", + "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.5s\n", + "Downloading 100%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.6s\n", + "Downloading 100%\n", + "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.7s\n", + "Downloading 100%\n", + "Extracting (6) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.8s\n", + "Downloading 100%\n", + "Extracting (5) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.9s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.0s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.1s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.2s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.3s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.4s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.5s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.6s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.7s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.8s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.9s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.0s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.1s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.2s\n", + "Downloading 100%\n", + "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.3s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.4s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.5s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.6s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.7s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.8s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.9s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.0s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.1s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.2s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.3s\n", + "Downloading 100%\n", + "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.4s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.5s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.6s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.7s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.8s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.9s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.0s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.1s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.2s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.3s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.4s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.5s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.6s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.7s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.8s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.9s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.0s\n", + "Downloading 100%\n", + "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.1s\n", + "Downloading 100%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.2s\n", + "Downloading 100%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.3s\n", + "Downloading 100%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.4s\n", + "Downloading 100%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.5s\n", + "Downloading 100%\n", + "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 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klayout-0.28.17_212_gfa14afbbf-20240223_100318_py37\n", + "\n", + "Transaction finished\n", + "\n" + ] + } + ], + "source": [ + "# Setup the environment for the OpenFASOC GDSFactory generator\n", + "# You only need to run this block once!\n", + "\n", + "# Clone OpenFASoC\n", + "!git clone https://github.com/idea-fasoc/OpenFASOC\n", + "# Install python dependencies\n", + "!pip install sky130\n", + "!pip install gf180 prettyprinttree svgutils\n", + "!pip install gdsfactory==7.7.0\n", + "\n", + "import pathlib\n", + "import os\n", + "# Install KLayout (via conda)\n", + "!curl -Ls https://micro.mamba.pm/api/micromamba/linux-64/latest | tar -xvj bin/micromamba\n", + "conda_prefix_path = pathlib.Path('conda-env')\n", + "CONDA_PREFIX = str(conda_prefix_path.resolve())\n", + "%env CONDA_PREFIX={CONDA_PREFIX}\n", + "\n", + "!bin/micromamba create --yes --prefix $CONDA_PREFIX\n", + "# Install from the litex-hub channel\n", + "!bin/micromamba install --yes --prefix $CONDA_PREFIX \\\n", + " --channel litex-hub \\\n", + " --channel main \\\n", + " klayout" + ] + }, + { + "cell_type": "markdown", + "source": [ + " klayoutバイナリをシステムパスに追加し、GLayoutディレクトリに移動します。\n", + "（カーネルを再起動する度に実行する必要があります。）\n", + "\n", + "\n" + ], + "metadata": { + "id": "zjJ2eUWiaUbR" + } + }, + { + "cell_type": "code", + "source": [ + "# Setup the environment for the OpenFASOC GDSFactory generator\n", + "\n", + "# Adding micro-mamba binary directory to the PATH\n", + "# This directory contains Klayout\n", + "import pathlib\n", + "import os\n", + "conda_prefix_path = pathlib.Path('conda-env')\n", + "CONDA_PREFIX = str(conda_prefix_path.resolve())\n", + "\n", + "%env CONDA_PREFIX={CONDA_PREFIX}\n", + "# Add conda packages to the PATH\n", + "PATH = os.environ['PATH']\n", + "%env PATH={PATH}:{CONDA_PREFIX}/bin\n", + "\n", + "%cd /content/OpenFASOC/openfasoc/generators/glayout\n" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "xMUPna-sakFn", + "outputId": "eb5a0f92-3f32-4664-f938-b1afcf380066" + }, + "execution_count": 5, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "env: CONDA_PREFIX=/content/conda-env\n", + "env: PATH=/opt/bin:/usr/local/nvidia/bin:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/tools/node/bin:/tools/google-cloud-sdk/bin:/content/conda-env/bin:/content/conda-env/bin\n", + "/content/OpenFASOC/openfasoc/generators/glayout\n" + ] + } + ] + }, + { + "cell_type": "markdown", + "source": [], + "metadata": { + "id": "sVWvV2Pwg9Ew" + } + }, + { + "cell_type": "markdown", + "source": [ + "# cell_config.py" + ], + "metadata": { + "id": "471iz7QIa3Iw" + } + }, + { + "cell_type": "code", + "source": [ + "from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict\n", + "#from glayout.flow.pdk.gf180_mapped import gf180\n", + "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", + "from glayout.flow.pdk.mappedpdk import MappedPDK\n", + "from glayout.flow.pdk.util.comp_utils import evaluate_bbox\n", + "from gdsfactory import Component\n", + "from gdsfactory.components import rectangle\n", + "from glayout.flow.primitives.fet import pmos\n", + "from glayout.flow.primitives.fet import nmos\n", + "from glayout.flow.routing.straight_route import straight_route\n", + "from glayout.flow.routing.c_route import c_route\n", + "from glayout.flow.routing.L_route import L_route\n", + "from glayout.flow.routing.smart_route import smart_route\n", + "from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized\n", + "from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized\n", + "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port\n", + "\n", + "def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ]) -> Component:\n", + "\t'''\n", + " To add external I/O ports onto the cell for LVS\n", + "\n", + "\t@ args:\n", + " \t# pdk: please refer to the glayout library\n", + " \t# comp: please refer to the glayout library\n", + " \t# port_list: tuple[ dict[str, Union[float, str]] ] specifying new port's corresponding pin size, and\n", + "\t\t\t\t\t the name of new port and exiting port managed to align with in the given\n", + "\t\t\t\t\t component, e.g.\n", + "\t\t\t\t\t \t(\n", + "\t\t\t\t\t\t\t{\n", + "\t\t\t\t\t\t\t\t\"new_port\": \"drain_new\",\n", + "\t\t\t\t\t\t\t\t\"new_port_label\": \"drain_new_label\",\n", + "\t\t\t\t\t\t\t\t\"pin_width\": 0.5,\n", + "\t\t\t\t\t\t\t\t\"pin_height\": 0.5,\n", + "\t\t\t\t\t\t\t\t\"ref_port\": \"multiplier_0_drain_E\"\n", + "\t\t\t\t\t\t\t},\n", + "\t\t\t\t\t\t\t{\n", + "\t\t\t\t\t\t\t\t\"new_port\": \"source_new\",\n", + "\t\t\t\t\t\t\t\t\"new_port_label\": \"source_new_label\",\n", + "\t\t\t\t\t\t\t\t\"pin_width\": 1.5,\n", + "\t\t\t\t\t\t\t\t\"pin_height\": 1.5,\n", + "\t\t\t\t\t\t\t\t\"ref_port\": \"multiplier_0_source_E\"\n", + "\t\t\t\t\t\t\t}\n", + "\t\t\t\t\t\t)\n", + "\n", + "\t\t# return: gdsfactory.Component\n", + "\n", + "\t@ Limitations:\n", + "\t\t# So far, only skywater130 process is validated\n", + "\t'''\n", + "\n", + "\t# Add pins and text labels for LVS\n", + "\tpins_labels_info = list() # list that contains all port and component information\n", + "\tprint(f\"port_list: {port_list}\")\n", + "\tfor port in port_list:\n", + "\t\t# To get the layer's data type mapped to the GDS\n", + "\t\tref_port_layer = comp.ports[ port[\"ref_port\"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc.\n", + "\n", + "\t\t# To create the pin w/ label where the layer[1] is mapped to 16\n", + "\t\tnew_port_pin = rectangle(layer=(ref_port_layer, 16), size=(port[\"pin_width\"], port[\"pin_height\"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0)\n", + "\t\tnew_port_pin.add_label(text=port[\"new_port_label\"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the \"label\" datatype in the GDS\n", + "\n", + "\t\t# To align the new port with the designated port existing in the given component\n", + "\t\talignment = ('c', 'b')\n", + "\t\tcomp_ref = align_comp_to_port(new_port_pin, comp.ports[ port[\"ref_port\"] ], alignment=alignment)\n", + "\t\tcomp.add(comp_ref)\n", + "\n", + "\treturn comp\n", + "\n" + ], + "metadata": { + "id": "fWFYNrTUa_7n" + }, + "execution_count": 6, + "outputs": [] + }, + { + "cell_type": "markdown", + "source": [ + "# inv_lib.py" + ], + "metadata": { + "id": "s0MLpq3xcaO4" + } + }, + { + "cell_type": "code", + "source": [ + "#from glayout.flow.pdk.gf180_mapped import gf180\n", + "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", + "from glayout.flow.pdk.mappedpdk import MappedPDK\n", + "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port\n", + "from gdsfactory import Component\n", + "from gdsfactory.components import rectangle\n", + "from glayout.flow.primitives.fet import pmos\n", + "from glayout.flow.primitives.fet import nmos\n", + "from glayout.flow.routing.straight_route import straight_route\n", + "from glayout.flow.routing.c_route import c_route\n", + "from glayout.flow.routing.L_route import L_route\n", + "from glayout.flow.routing.smart_route import smart_route\n", + "\n", + "def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation):\n", + "\t# Create a top level component\n", + "\ttop_level = Component(component_name)\n", + "\t# To prepare one PMOS and one NMOS for the subsequent inverter cell construction\n", + "\tpfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length)\n", + "\tnfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length)\n", + "\n", + "\t# Instantiation of above PMOS and NMOS under the top level\n", + "\tpfet_ref = prec_ref_center(pfet)\n", + "\tnfet_ref = prec_ref_center(nfet)\n", + "\ttop_level.add(pfet_ref)\n", + "\ttop_level.add(nfet_ref)\n", + "\n", + "\t# Placement (relative move)\n", + "\tmos_spacing = pdk.util_max_metal_seperation()\n", + "\tif(orientation==\"horizontal\"):\n", + "\t\tpfet_ref.rotate(90)\n", + "\t\tnfet_ref.rotate(90)\n", + "\telse:\n", + "\t\tpass\n", + "\tpfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing)\n", + "\n", + "\t# Routing\n", + "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_drain_E\"], nfet_ref.ports[\"multiplier_0_drain_E\"])\n", + "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_gate_W\"], nfet_ref.ports[\"multiplier_0_gate_W\"])\n", + "\n", + "\t# To add the ports\n", + "\ttop_level.add_ports(pfet_ref.get_ports_list(), prefix=\"pmos_\")\n", + "\ttop_level.add_ports(nfet_ref.get_ports_list(), prefix=\"nmos_\")\n", + "\n", + "\treturn top_level" + ], + "metadata": { + "id": "VZoH8lTCcecm" + }, + "execution_count": 7, + "outputs": [] + }, + { + "cell_type": "markdown", + "source": [ + "# transmission_gate.py" + ], + "metadata": { + "id": "ZQOZALxpcgFc" + } + }, + { + "cell_type": "code", + "source": [ + "from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict\n", + "#from glayout.flow.pdk.gf180_mapped import gf180\n", + "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", + "from glayout.flow.pdk.mappedpdk import MappedPDK\n", + "from glayout.flow.pdk.util.comp_utils import evaluate_bbox\n", + "from gdsfactory import Component\n", + "from gdsfactory.components import rectangle\n", + "from glayout.flow.primitives.fet import pmos\n", + "from glayout.flow.primitives.fet import nmos\n", + "from glayout.flow.routing.straight_route import straight_route\n", + "from glayout.flow.routing.c_route import c_route\n", + "from glayout.flow.routing.L_route import L_route\n", + "from glayout.flow.routing.smart_route import smart_route\n", + "from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized\n", + "from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized\n", + "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port\n", + "\n", + "# My own cell library\n", + "#from inv_lib import reconfig_inv\n", + "#import cell_config as config\n", + "\n", + "def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, nmos_length):\n", + "\t# To prepare all necessary cells to construct a transmission gate, i.e.\n", + "\t# 1) PMOS\n", + "\t# 2) NMOS\n", + "\tpfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length)\n", + "\tnfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length)\n", + "\n", + "\t# Placement and adding ports\n", + "\ttop_level = Component(name=\"TG\")\n", + "\tpfet_ref = prec_ref_center(pfet)\n", + "\tnfet_ref = prec_ref_center(nfet)\n", + "\ttop_level.add(pfet_ref)\n", + "\ttop_level.add(nfet_ref)\n", + "\n", + "\t# Placement\n", + "\tmos_spacing = pdk.util_max_metal_seperation()\n", + "\t#mos_spacing = pdk.get_grule(\"met1\")[\"min_width\"])\n", + "\tif flip_config[\"degree\"] != None:\n", + "\t\tpfet_ref.rotate(flip_config[\"degree\"])\n", + "\t\tnfet_ref.rotate(flip_config[\"degree\"])\n", + "\tpfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing)\n", + "\n", + "\t# Routing\n", + "\t# To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG\n", + "\t# a) PMOS.source connected to NMOS.source\n", + "\t# b) PMOS.drain connected to NMOS.drain\n", + "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_source_E\"], nfet_ref.ports[\"multiplier_0_source_E\"]) # \"in\" of the TG\n", + "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_drain_W\"], nfet_ref.ports[\"multiplier_0_drain_E\"]) # \"out\" of the TG\n", + "\n", + "\ttop_level.add_ports(pfet_ref.get_ports_list(), prefix=\"pmos_\")\n", + "\ttop_level.add_ports(nfet_ref.get_ports_list(), prefix=\"nmos_\")\n", + "\t#top_level.add_port(\n", + "\t#\tname=\"\", center=[0, width / 2], width=width, orientation=180, layer=layer\n", + "\t#)\n", + "\n", + "\t# Add pins and text labels for LVS\n", + "\tpins_labels_info = list() # list that contains all port and component information\n", + "\t# To define the layers\n", + "\tgds_met1 = pdk.get_glayer(\"met2\")[0]\n", + "\tgds_met2 = gds_met1+1\n", + "\tgds_met3 = gds_met2+1\n", + "\tgds_met4 = gds_met3+1\n", + "\tgds_met5 = gds_met4+1\n", + "\t# To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port\n", + "\ttg_din_portLayer = top_level.ports[\"pmos_multiplier_0_source_W\"].layer[0]\n", + "\ttg_dout_portLayer = top_level.ports[\"pmos_multiplier_0_drain_E\"].layer[0]\n", + "\t# To create the pins w/ labels and append to info list\n", + "\ttg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0)\n", + "\ttg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy()\n", + "\ttg_din_pin.add_label(text=\"Vin\", layer=(tg_din_portLayer, 5))\n", + "\ttg_dout_pin.add_label(text=\"Vout\", layer=(tg_dout_portLayer, 5))\n", + "\tpins_labels_info.append((tg_din_pin, top_level.ports[\"pmos_multiplier_0_source_W\"], None))\n", + "\tpins_labels_info.append((tg_dout_pin, top_level.ports[\"pmos_multiplier_0_drain_E\"], None))\n", + "\n", + "\t#print(top_level.ports[\"pmos_multiplier_0_source_W\"].name)\n", + "\t#top_level.pprint_ports()\n", + "\n", + "\t# Move everythin to position\n", + "\tfor comp, prt, alignment in pins_labels_info:\n", + "\t\talignment = ('c', 'b') if alignment is None else alignment\n", + "\t\tcompref = align_comp_to_port(comp, prt, alignment=alignment)\n", + "\t\t#top_level.add(compref)\n", + "\n", + "\treturn top_level #top_level.flatten()\n", + "\n", + "def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length):\n", + "\t# To prepare all necessary cells to construct a transmission gate, i.e.\n", + "\t# 1) transmission gate\n", + "\t# 2) Inverter\n", + "\ttg = naive_tg_cell(pdk=pdk, flip_config={\"degree\": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length)\n", + "\tinv = reconfig_inv(pdk=pdk, component_name=\"gate_ctrl_inv\", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation=\"horizontal\")\n", + "\n", + "\t# Instantiation of the essential cells\n", + "\ttop_level = Component(name=\"tg_with_inv\")\n", + "\ttg_ref = prec_ref_center(tg)\n", + "\tinv_ref = prec_ref_center(inv)\n", + "\ttop_level.add(tg_ref)\n", + "\ttop_level.add(inv_ref)\n", + "\n", + "\t# Placement\n", + "\tmos_spacing = pdk.util_max_metal_seperation()\n", + "\tnwell_min_spacing = pdk.get_grule(\"nwell\")[\"min_separation\"]\n", + "\tinv_cell_width = inv_ref.xsize # or = evaluate_bbox(inv)[0]\n", + "\ttg_ref.movex(inv_cell_width + nwell_min_spacing)\n", + "\n", + "\t# Routing\n", + "\t# 1) PMOS of the TG is switched on/off by the inverter's output\n", + "\t# 2) NMOS of the TG is switched on/off by an external control signal connected to inverter's input port as well\n", + "\ttop_level << smart_route(pdk, inv_ref.ports[\"pmos_multiplier_0_drain_E\"], tg_ref.ports[\"pmos_multiplier_0_gate_W\"])\n", + "\ttop_level << smart_route(pdk, inv_ref.ports[\"nmos_multiplier_0_gate_S\"], tg_ref.ports[\"nmos_multiplier_0_gate_S\"])\n", + "\n", + "\t# Adding the ports\n", + "\ttop_level.add_ports(tg_ref.get_ports_list(), prefix=\"tg_\")\n", + "\ttop_level.add_ports(inv_ref.get_ports_list(), prefix=\"inv_\")\n", + "\n", + "\treturn top_level\n" + ], + "metadata": { + "id": "f9zRFCm6cl4N" + }, + "execution_count": 13, + "outputs": [] + }, + { + "cell_type": "markdown", + "source": [ + "# eval.py" + ], + "metadata": { + "id": "VLrreUmkcrg_" + } + }, + { + "cell_type": "code", + "source": [ + "#from glayout.flow.pdk.gf180_mapped import gf180\n", + "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", + "import gdstk\n", + "import svgutils.transform as sg\n", + "import IPython.display\n", + "from IPython.display import clear_output\n", + "\n", + "def display_gds(gds_file, image_filename: str, scale = 3):\n", + " # Generate an SVG image\n", + " top_level_cell = gdstk.read_gds(gds_file).top_level()[0]\n", + " top_level_cell.write_svg(image_filename)\n", + " # Scale the image for displaying\n", + " fig = sg.fromfile(image_filename)\n", + " fig.set_size((str(float(fig.width) * scale), str(float(fig.height) * scale)))\n", + " fig.save(image_filename)\n", + "\n", + " # Display the image\n", + " IPython.display.display(IPython.display.SVG(image_filename))\n", + "\n", + "def main():\n", + " tg_inst = tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15)\n", + " tg_inst = add_port_lvs(\n", + " pdk=sky130,\n", + " comp=tg_inst,\n", + " port_list=[\n", + " {\n", + " \"new_port\": \"tg_ctrl\",\n", + " \"new_port_label\": \"ctrl\",\n", + " \"pin_width\": tg_inst.ports[\"inv_nmos_multiplier_0_gate_S\"].width,\n", + " \"pin_height\": tg_inst.ports[\"inv_nmos_multiplier_0_gate_S\"].width,\n", + " \"ref_port\": \"inv_nmos_multiplier_0_gate_S\"\n", + " },\n", + " {\n", + " \"new_port\": \"tg_din\",\n", + " \"new_port_label\": \"din\",\n", + " \"pin_width\": 0.3,\n", + " \"pin_height\": 0.3,\n", + " \"ref_port\": \"tg_pmos_multiplier_0_source_W\"\n", + " },\n", + " {\n", + " \"new_port\": \"tg_dout\",\n", + " \"new_port_label\": \"dout\",\n", + " \"pin_width\": 0.3,\n", + " \"pin_height\": 0.3,\n", + " \"ref_port\": \"tg_nmos_multiplier_0_drain_N\"\n", + " }\n", + "\t ]\n", + "\t)\n", + " #tg_inst.flatten()\n", + " #tg_inst.show()\n", + " tg_inst.write_gds(\"tg_with_inv.gds\")\n", + " display_gds(gds_file=\"tg_with_inv.gds\", image_filename=\"tg_with_inv.svg\", scale=5)\n", + "\n", + "if __name__ == \"__main__\":\n", + " main()" + ], + "metadata": { + "id": "K3JfrIUWctcI", + "outputId": "b69ca1d4-6318-4a8c-b46c-47f42343f65d", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + } + }, + "execution_count": 25, + "outputs": [ + { + "output_type": "stream", + "name": "stderr", + "text": [ + ":51: UserWarning: Unnamed cells, 7 in 'tg_with_inv$6'\n", + " tg_inst.write_gds(\"tg_with_inv.gds\")\n", + "\u001b[32m2024-11-14 02:40:11.852\u001b[0m | \u001b[1mINFO \u001b[0m | \u001b[36mgdsfactory.component\u001b[0m:\u001b[36m_write_library\u001b[0m:\u001b[36m1851\u001b[0m - \u001b[1mWrote to 'tg_with_inv.gds'\u001b[0m\n" + ] + }, + { + "output_type": "stream", + "name": "stdout", + "text": [ + "port_list: [{'new_port': 'tg_ctrl', 'new_port_label': 'ctrl', 'pin_width': 0.33, 'pin_height': 0.33, 'ref_port': 'inv_nmos_multiplier_0_gate_S'}, {'new_port': 'tg_din', 'new_port_label': 'din', 'pin_width': 0.3, 'pin_height': 0.3, 'ref_port': 'tg_pmos_multiplier_0_source_W'}, {'new_port': 'tg_dout', 'new_port_label': 'dout', 'pin_width': 0.3, 'pin_height': 0.3, 'ref_port': 'tg_nmos_multiplier_0_drain_N'}]\n" + ] + }, + { + "output_type": "display_data", + "data": { + "text/plain": [ + "" + ], + "image/svg+xml": "\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\ndout\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nctrl\n\n\n\ndin\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n" + }, + "metadata": {} + } + ] + }, + { + "cell_type": "markdown", + "source": [ + "\n", + "\n", + "---\n", + "\n", + "\n", + "# トランスミッションゲートを表示させます。\n" + ], + "metadata": { + "id": "VTXMiC1nbFTu" + } + }, + { + "cell_type": "markdown", + "source": [ + "Geminiによると・・・\n", + "生成されたGDSファイルに名前のないセルがあるという警告が表示されているようです。この警告はgdsfactoryから発生し、「TG$2」セル内に明示的な名前が割り当てられていないコンポーネントがあることを示しています。\n", + "\n", + "すぐに問題が発生するわけではありませんが、整理とデバッグを改善するために、すべてのコンポーネントに名前を付けることをお勧めします。コンポーネントを作成するときに name 引数を指定することで、コンポーネントに名前を付けることができます。\n", + "\n", + "たとえば、transmissionGate_cell 関数では、pfet および nfet インスタンスに名前を付けることができます。\n", + "\n", + "\n", + "pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=width, length=length, name=\"pmos_instance\")\n", + "nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=width, length=length, name=\"nmos_instance\")\n", + "Use code with caution\n", + "これにより、GDSファイルがより読みやすくなり、扱いやすくなります。\n", + "\n", + "・・・らしいです" + ], + "metadata": { + "id": "xyQej3g8pIMq" + } + } + ] +} \ No newline at end of file From 477ff15663e0edcebde4221a0786e8e570061a2a Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Thu, 14 Nov 2024 17:13:19 +0000 Subject: [PATCH 11/21] Add functions to automatically insert the external I/O ports on the target Pcell --- .../cell_config.py | 77 +++++++++++++++---- .../transmission_gate_saltychip/eval.py | 17 ++-- 2 files changed, 72 insertions(+), 22 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py index 915d85688..06dfedb6c 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py @@ -15,7 +15,25 @@ from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port -def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ]) -> Component: +def add_wire(comp, xsize=2, ysize=1, layer=(68, 20), label="new_wire", center=(0, 0), position_offset=(1.4, 1.4)): + c = Component() + c.add_polygon( + [ + (center[0]-position_offset[0], center[1]-position_offset[1]), + (center[0]+position_offset[0], center[1]-position_offset[1]), + (center[0]+position_offset[0], center[1]-position_offset[1]-ysize), + (center[0]-position_offset[0], center[1]-position_offset[1]-ysize) + ], + layer=layer + ) + comp.add_port(name=f"{label}_W", center=[0, ysize / 2], width=ysize, orientation=0, layer=layer) + comp.add_port(name=f"{label}_E", center=[xsize, ysize / 2], width=ysize, orientation=0, layer=layer) + c.add_label(text=f"{label}_W", position=(c.x-xsize/2, c.y), layer=layer) + c.add_label(text=f"{label}_E", position=(c.x+xsize/2, c.y), layer=layer) + + return c + +def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: ''' To add external I/O ports onto the cell for LVS @@ -41,27 +59,58 @@ def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Uni "ref_port": "multiplier_0_source_E" } ) + # port_feature: a "dict"-type primitive specifying the feature of the new port, e.g. + {"port_type":"pin", "layer":None} -> To create a rectangle as the new port + {"port_type":"wire", "layer":"met1"} -> To extend the existing port by a wire only # return: gdsfactory.Component @ Limitations: # So far, only skywater130 process is validated ''' + + if port_feature["port_type"] == "pin": + port_type = 0 + elif port_feature["port_type"] == "wire": + new_port_layer = pdk.get_glayer(port_feature["layer"]) + port_type = 1 + wire_width = comp.xsize + wire_height = pdk.get_grule(port_feature["layer"])["min_width"] + new_port_center = comp.center + new_port_position_offset = (comp.xsize/2, comp.ysize/2+pdk.util_max_metal_seperation()) + wire_spacing = pdk.get_grule(port_feature["layer"])["min_separation"]+wire_height + port_cnt = 0 + else: + raise ValueError("The port type must be either pin or wire") + + if port_type == 0: # port of which features pin-added type + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + print(f"port_list: {port_list}") + for port in port_list: + # To get the layer's data type mapped to the GDS + ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc. - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - print(f"port_list: {port_list}") - for port in port_list: - # To get the layer's data type mapped to the GDS - ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc. + # To create the pin w/ a label where the layer[1] is mapped to 16 + new_port = rectangle(layer=(ref_port_layer, 16), size=(port["pin_width"], port["pin_height"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) + new_port.add_label(text=port["new_port_label"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the "label" datatype in the GDS - # To create the pin w/ label where the layer[1] is mapped to 16 - new_port_pin = rectangle(layer=(ref_port_layer, 16), size=(port["pin_width"], port["pin_height"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) - new_port_pin.add_label(text=port["new_port_label"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the "label" datatype in the GDS + # To align the new port with the designated port existing in the given component + alignment = ('c', 'b') + comp_ref = align_comp_to_port(new_port, comp.ports[ port["ref_port"] ], alignment=alignment) + comp.add(comp_ref) - # To align the new port with the designated port existing in the given component - alignment = ('c', 'b') - comp_ref = align_comp_to_port(new_port_pin, comp.ports[ port["ref_port"] ], alignment=alignment) - comp.add(comp_ref) + else: # port_type=1, i.e. port of which features wire_only + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + print(f"port_list: {port_list}") + for port in port_list: + # To create the pin where the layer[1] is mapped to 16 + new_port = add_wire(comp=comp, xsize=wire_width, ysize=wire_height, layer=new_port_layer, label=port["new_port_label"], center=new_port_center, position_offset=new_port_position_offset) + new_port_ref = comp.add_ref(new_port) + new_port_ref.movey(-wire_spacing*port_cnt) + comp << smart_route(pdk, comp.ports.get(port["ref_port"]), comp.ports.get(port["new_port"]+"_E")) + + port_cnt = port_cnt + 1 # Increment the index indicating the new port return comp \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 66b15b77c..72a32a73a 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -10,31 +10,32 @@ def main(): comp=tg_inst, port_list=[ { - "new_port": "tg_ctrl", - "new_port_label": "ctrl", + "new_port": "Vctrl", + "new_port_label": "Vctrl", "pin_width": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, "pin_height": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, "ref_port": "inv_nmos_multiplier_0_gate_S" }, { - "new_port": "tg_din", - "new_port_label": "din", + "new_port": "Vin", + "new_port_label": "Vin", "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, "ref_port": "tg_pmos_multiplier_0_source_W" }, { - "new_port": "tg_dout", - "new_port_label": "dout", + "new_port": "Vout", + "new_port_label": "Vout", "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, "ref_port": "tg_nmos_multiplier_0_drain_N" } - ] + ], + port_feature = {"port_type":"wire", "layer":"met2"} # met2 is actually mapped to met1 in sky130 proceess ) #tg_inst.flatten() tg_inst.show() - tg_inst.write_gds("gds/tg_with_inv.gds") + #tg_inst.write_gds("gds/tg_with_inv.gds") if __name__ == "__main__": main() \ No newline at end of file From e034352e3932fe751c3b24edf7668ff8b8e93d8a Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Fri, 15 Nov 2024 14:07:44 +0000 Subject: [PATCH 12/21] Add the ToDo list for the PR draft submission --- .../transmission_gate_saltychip/README.md | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md index 4049e2a20..22bafe394 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md @@ -8,3 +8,29 @@ | inv_lib.py | Layout generation of inverter for controlling the transmission gate's PMOS and NMOS | | | transmission_gate.py | Layout generation of a transmission gate | The layout is still under construction | | mimcap_array.py | Layout generation of a 8x8 MIM capacitor array | Transmission gate combined with a MIM capacitor array is the aim in this project | + +--- + +Submission of PR Draft (deadline: 24/11/2024) + +- ToDo list +- Transmission gate + - [x] Layout + - [ ] Add ports w/ labels onto the layout (for the subsequent LVS) + - [ ] DRC of the layout w/o error (Magic) + - [ ] DRC of the layout w/o error (Klayout) + - [ ] Create the baseline schematic of the created component + - [ ] LVS w/o error + - [ ] Document about the PCell specification + - [ ] PEX and create the testbench + - [ ] Verification gets passed +- MIMI capacitor array + - [x] Layout + - [ ] Add ports w/ labels onto the layout (for the subsequent LVS) + - [ ] DRC of the layout w/o error (Magic) + - [ ] DRC of the layout w/o error (Klayout) + - [ ] Create the baseline schematic of the created component + - [ ] LVS w/o error + - [ ] Document about the PCell specification + - [ ] PEX and create the testbench + - [ ] Verification gets passed \ No newline at end of file From 94561b630cc44a17f17aa200ee8c374b9bdd1a43 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 17 Nov 2024 08:26:51 +0000 Subject: [PATCH 13/21] Change the route layer inside the transmission gate --- .../cell_config.py | 137 +++++++++++------- .../transmission_gate_saltychip/eval.py | 42 +++--- .../transmission_gate_saltychip/inv_lib.py | 4 +- .../transmission_gate.py | 6 +- 4 files changed, 115 insertions(+), 74 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py index 06dfedb6c..41b1ea28a 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py @@ -7,6 +7,7 @@ from gdsfactory.components import rectangle from glayout.flow.primitives.fet import pmos from glayout.flow.primitives.fet import nmos +from glayout.flow.primitives.via_gen import via_stack from glayout.flow.routing.straight_route import straight_route from glayout.flow.routing.c_route import c_route from glayout.flow.routing.L_route import L_route @@ -15,24 +16,94 @@ from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port -def add_wire(comp, xsize=2, ysize=1, layer=(68, 20), label="new_wire", center=(0, 0), position_offset=(1.4, 1.4)): +# Status: W.I.P. +def add_wire(comp, xsize=2, ysize=1, layer=(68, 20), port_label="new_wire", center=(0, 0), position_offset=(1.4, 1.4)): c = Component() + wire_leftBottom_pos = (center[0]-position_offset[0], center[1]-position_offset[1]) + wire_rightBottom_pos = (center[0]+position_offset[0], center[1]-position_offset[1]) + wire_rightTop_pos = (center[0]+position_offset[0], center[1]-position_offset[1]-ysize) + wire_leftTop_pos = (center[0]-position_offset[0], center[1]-position_offset[1]-ysize) c.add_polygon( [ - (center[0]-position_offset[0], center[1]-position_offset[1]), - (center[0]+position_offset[0], center[1]-position_offset[1]), - (center[0]+position_offset[0], center[1]-position_offset[1]-ysize), - (center[0]-position_offset[0], center[1]-position_offset[1]-ysize) + wire_leftBottom_pos, + wire_rightBottom_pos, + wire_rightTop_pos, + wire_leftTop_pos ], layer=layer ) - comp.add_port(name=f"{label}_W", center=[0, ysize / 2], width=ysize, orientation=0, layer=layer) - comp.add_port(name=f"{label}_E", center=[xsize, ysize / 2], width=ysize, orientation=0, layer=layer) - c.add_label(text=f"{label}_W", position=(c.x-xsize/2, c.y), layer=layer) - c.add_label(text=f"{label}_E", position=(c.x+xsize/2, c.y), layer=layer) - + + port_W_pos = (c.x-xsize/2, c.y) + port_E_pos = (c.x+xsize/2, c.y) + c.add_port(name=f"{port_label}_W", center=port_W_pos, width=ysize, orientation=0, layer=layer) + c.add_port(name=f"{port_label}_E", center=port_E_pos, width=ysize, orientation=0, layer=layer) + c.add_label(text=f"{port_label}_W", position=port_W_pos, layer=layer) + c.add_label(text=f"{port_label}_E", position=port_E_pos, layer=layer) return c +def port_with_pin(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + for port in port_list: + ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # To get the layer's data type mapped to the GDS. + # [0]: layer mapping, [1]: pin, drawing, label, net, etc. + print(f"Port: {port}") + + # To create the pin w/ a label + new_port_layer = pdk.get_glayer(port_feature["layer"]) + new_port_layerPin = (new_port_layer[0], 16) # layer[1]=16 mapped to the "pin" datatype in the GDS + new_port_layerLabel = (new_port_layer[0], 5) # layer[1]=5 mapped to the "label" datatype in the GDS + new_port_layerDraw = pdk.get_glayer(port_feature["layer"]) + + new_pin_width = pdk.get_grule(port_feature["layer"])["min_width"] + new_port = rectangle(layer=new_port_layerPin, size=(new_pin_width, new_pin_width),centered=True).copy() # To set rectangle's centroid to the relative (0, 0) + new_port.add_label(text=port["new_port_label"], layer=new_port_layerLabel) + + # To align the new port with the designated port existing in the given component + alignment = port["ref_port_align"] + comp_ref = align_comp_to_port(custom_comp=new_port, align_to=comp.ports[ port["ref_port"] ], alignment=alignment) + comp.add(comp_ref) + comp_ref.movex(port["new_port_move"][0]) + comp_ref.movey(port["new_port_move"][1]) + + if port["new_port_via"] == True: + new_port_via = via_stack(pdk=pdk, glayer1=port["new_port_via_layers"][0], glayer2=port["new_port_via_layers"][1]) + new_port_via_ref = comp.add_ref(new_port_via) + new_port_via_ref.movex(comp_ref.center[0]) + new_port_via_ref.movey(comp_ref.center[1]) + + # To register the new port as an external I/O port of the top-level component + comp.add_port(name=port["new_port"], center=new_port.center, width=new_pin_width, orientation=0, layer=new_port_layerDraw) + + return comp + +def port_with_wire(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: + new_port_layer = pdk.get_glayer(port_feature["layer"]) + wire_width = comp.xsize + wire_height = pdk.get_grule(port_feature["layer"])["min_width"] + new_port_center = comp.center + new_port_position_offset = (comp.xsize/2, comp.ysize/2+pdk.util_max_metal_seperation()) + wire_spacing = pdk.get_grule(port_feature["layer"])["min_separation"]+wire_height + port_cnt = 0 + + # Add pins and text labels for LVS + pins_labels_info = list() # list that contains all port and component information + print(f"port_list: {port_list}") + for port in port_list: + # To create the pin where the layer[1] is mapped to 16 + connect_pos = port["connect_pos"] if "connect_pos" in port else "W" + new_wire = add_wire(comp=comp, xsize=wire_width, ysize=wire_height, layer=new_port_layer, port_label=port["new_port_label"], center=new_port_center, position_offset=new_port_position_offset) + new_wire_ref = comp.add_ref(new_wire) + new_wire_ref.movey(-wire_spacing*port_cnt) + comp.add_ports(new_wire_ref.get_ports_list()) # To register all the ports in the wire to the underlying component + edge0 = comp.ports.get(port["ref_port"]) + edge1 = comp.ports.get(port["new_port"]+f"_{connect_pos}") + comp << smart_route(pdk, edge0, edge1) + + port_cnt = port_cnt + 1 # Increment the index indicating the new port + + return comp + def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: ''' To add external I/O ports onto the cell for LVS @@ -47,16 +118,16 @@ def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Uni { "new_port": "drain_new", "new_port_label": "drain_new_label", - "pin_width": 0.5, - "pin_height": 0.5, + "pin_width": 0.5, # -> Only being used when "port_feature": "pin" + "pin_height": 0.5, # -> Only being used when "port_feature": "pin" "ref_port": "multiplier_0_drain_E" }, { "new_port": "source_new", "new_port_label": "source_new_label", - "pin_width": 1.5, - "pin_height": 1.5, - "ref_port": "multiplier_0_source_E" + "ref_port": "multiplier_0_source_E", + "connect_pos": "W" # -> for all connect_pos in {W, E} where the + # connect_pos will be set to "W" if connect_pos=None } ) # port_feature: a "dict"-type primitive specifying the feature of the new port, e.g. @@ -72,45 +143,13 @@ def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Uni if port_feature["port_type"] == "pin": port_type = 0 elif port_feature["port_type"] == "wire": - new_port_layer = pdk.get_glayer(port_feature["layer"]) port_type = 1 - wire_width = comp.xsize - wire_height = pdk.get_grule(port_feature["layer"])["min_width"] - new_port_center = comp.center - new_port_position_offset = (comp.xsize/2, comp.ysize/2+pdk.util_max_metal_seperation()) - wire_spacing = pdk.get_grule(port_feature["layer"])["min_separation"]+wire_height - port_cnt = 0 else: raise ValueError("The port type must be either pin or wire") if port_type == 0: # port of which features pin-added type - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - print(f"port_list: {port_list}") - for port in port_list: - # To get the layer's data type mapped to the GDS - ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc. - - # To create the pin w/ a label where the layer[1] is mapped to 16 - new_port = rectangle(layer=(ref_port_layer, 16), size=(port["pin_width"], port["pin_height"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) - new_port.add_label(text=port["new_port_label"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the "label" datatype in the GDS - - # To align the new port with the designated port existing in the given component - alignment = ('c', 'b') - comp_ref = align_comp_to_port(new_port, comp.ports[ port["ref_port"] ], alignment=alignment) - comp.add(comp_ref) - + port_with_pin(pdk=pdk, comp=comp, port_list=port_list, port_feature=port_feature) else: # port_type=1, i.e. port of which features wire_only - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - print(f"port_list: {port_list}") - for port in port_list: - # To create the pin where the layer[1] is mapped to 16 - new_port = add_wire(comp=comp, xsize=wire_width, ysize=wire_height, layer=new_port_layer, label=port["new_port_label"], center=new_port_center, position_offset=new_port_position_offset) - new_port_ref = comp.add_ref(new_port) - new_port_ref.movey(-wire_spacing*port_cnt) - comp << smart_route(pdk, comp.ports.get(port["ref_port"]), comp.ports.get(port["new_port"]+"_E")) - - port_cnt = port_cnt + 1 # Increment the index indicating the new port + port_with_wire(pdk=pdk, comp=comp, port_list=port_list, port_feature=port_feature) return comp \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 72a32a73a..0576b7653 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -3,8 +3,10 @@ from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 import cell_config as config +TARGET_PDK = sky130 + def main(): - tg_inst = tg.tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15) + tg_inst = tg.tg_with_inv(pdk=TARGET_PDK, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15) tg_inst = config.add_port_lvs( pdk=sky130, comp=tg_inst, @@ -12,26 +14,26 @@ def main(): { "new_port": "Vctrl", "new_port_label": "Vctrl", - "pin_width": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, - "pin_height": tg_inst.ports["inv_nmos_multiplier_0_gate_S"].width, - "ref_port": "inv_nmos_multiplier_0_gate_S" - }, - { - "new_port": "Vin", - "new_port_label": "Vin", - "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, - "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_source_S"].width, - "ref_port": "tg_pmos_multiplier_0_source_W" - }, - { - "new_port": "Vout", - "new_port_label": "Vout", - "pin_width": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, - "pin_height": 0.3,#tg_inst.ports["tg_nmos_multiplier_0_drain_S"].width, - "ref_port": "tg_nmos_multiplier_0_drain_N" - } + "new_port_via": True, + "new_port_via_layers": ("met1", "met2"), + "new_port_move": (0, -TARGET_PDK.get_grule("mcon")["min_separation"]), + "ref_port": "inv_nmos_multiplier_0_gate_E", + "ref_port_align": ("c", "b"), + "connect_pos": "W" # To connce the ref_port to the "west" side of the new port + }#, + #{ + # "new_port": "Vin", + # "new_port_label": "Vin", + # "ref_port": "tg_pmos_multiplier_0_source_W" + #}, + #{ + # "new_port": "Vout", + # "new_port_label": "Vout", + # "ref_port": "tg_nmos_multiplier_0_drain_W", + # "connect_pos": "E" # To connect the ref_port to the "east" side of the new port + #} ], - port_feature = {"port_type":"wire", "layer":"met2"} # met2 is actually mapped to met1 in sky130 proceess + port_feature = {"port_type":"pin", "layer":"met1"} # met1 is actually mapped to li1 in sky130 proceess ) #tg_inst.flatten() tg_inst.show() diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py index 6a1347ced..1692dabbe 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py @@ -34,8 +34,8 @@ def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_w pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) # Routing - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"]) - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"]) + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met1") # connected by li1 + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"] , glayer1="met1") # connected by li1 # To add the ports top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 654e4a93f..06b0313d3 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -129,8 +129,8 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG # a) PMOS.source connected to NMOS.source # b) PMOS.drain connected to NMOS.drain - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_source_E"]) # "in" of the TG - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_drain_E"]) # "out" of the TG + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # "in" of the TG + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met1") # "out" of the TG top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") @@ -192,7 +192,7 @@ def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length # 1) PMOS of the TG is switched on/off by the inverter's output # 2) NMOS of the TG is switched on/off by an external control signal connected to inverter's input port as well top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_E"], tg_ref.ports["pmos_multiplier_0_gate_W"]) - top_level << smart_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"]) + top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"]) # Adding the ports top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") From 6d8e8befd101fed744edae19bee0168763320150 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 17 Nov 2024 08:32:09 +0000 Subject: [PATCH 14/21] Add the external pins for the LVS process --- .../blocks/transmission_gate_saltychip/transmission_gate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 06b0313d3..5757be092 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -192,7 +192,7 @@ def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length # 1) PMOS of the TG is switched on/off by the inverter's output # 2) NMOS of the TG is switched on/off by an external control signal connected to inverter's input port as well top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_E"], tg_ref.ports["pmos_multiplier_0_gate_W"]) - top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"]) + top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"], glayer1="met3") # Adding the ports top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") From c75a0a5540f14fad6c478eb8c7f1c224d034831e Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 17 Nov 2024 14:45:27 +0000 Subject: [PATCH 15/21] Team: Salty Chip, Chipathon2024 Fix the DRC error by removing the deep N-well on the NMOS of the inv cell which is used as the control component for the underlying transmission gate --- .../cell_config.py | 155 -- .../transmission_gate_saltychip/eval.py | 50 +- .../transmission_gate_saltychip/inv_lib.py | 44 - .../reconfig_inv.py | 76 + .../transmission_gate_saltychip/tg_gen.ipynb | 2326 ----------------- .../transmission_gate.py | 144 +- 6 files changed, 113 insertions(+), 2682 deletions(-) delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py delete mode 100755 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py create mode 100755 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py deleted file mode 100644 index 41b1ea28a..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/cell_config.py +++ /dev/null @@ -1,155 +0,0 @@ -from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict -#from glayout.flow.pdk.gf180_mapped import gf180 -from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 -from glayout.flow.pdk.mappedpdk import MappedPDK -from glayout.flow.pdk.util.comp_utils import evaluate_bbox -from gdsfactory import Component -from gdsfactory.components import rectangle -from glayout.flow.primitives.fet import pmos -from glayout.flow.primitives.fet import nmos -from glayout.flow.primitives.via_gen import via_stack -from glayout.flow.routing.straight_route import straight_route -from glayout.flow.routing.c_route import c_route -from glayout.flow.routing.L_route import L_route -from glayout.flow.routing.smart_route import smart_route -from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized -from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized -from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port - -# Status: W.I.P. -def add_wire(comp, xsize=2, ysize=1, layer=(68, 20), port_label="new_wire", center=(0, 0), position_offset=(1.4, 1.4)): - c = Component() - wire_leftBottom_pos = (center[0]-position_offset[0], center[1]-position_offset[1]) - wire_rightBottom_pos = (center[0]+position_offset[0], center[1]-position_offset[1]) - wire_rightTop_pos = (center[0]+position_offset[0], center[1]-position_offset[1]-ysize) - wire_leftTop_pos = (center[0]-position_offset[0], center[1]-position_offset[1]-ysize) - c.add_polygon( - [ - wire_leftBottom_pos, - wire_rightBottom_pos, - wire_rightTop_pos, - wire_leftTop_pos - ], - layer=layer - ) - - port_W_pos = (c.x-xsize/2, c.y) - port_E_pos = (c.x+xsize/2, c.y) - c.add_port(name=f"{port_label}_W", center=port_W_pos, width=ysize, orientation=0, layer=layer) - c.add_port(name=f"{port_label}_E", center=port_E_pos, width=ysize, orientation=0, layer=layer) - c.add_label(text=f"{port_label}_W", position=port_W_pos, layer=layer) - c.add_label(text=f"{port_label}_E", position=port_E_pos, layer=layer) - return c - -def port_with_pin(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - for port in port_list: - ref_port_layer = comp.ports[ port["ref_port"] ].layer[0] # To get the layer's data type mapped to the GDS. - # [0]: layer mapping, [1]: pin, drawing, label, net, etc. - print(f"Port: {port}") - - # To create the pin w/ a label - new_port_layer = pdk.get_glayer(port_feature["layer"]) - new_port_layerPin = (new_port_layer[0], 16) # layer[1]=16 mapped to the "pin" datatype in the GDS - new_port_layerLabel = (new_port_layer[0], 5) # layer[1]=5 mapped to the "label" datatype in the GDS - new_port_layerDraw = pdk.get_glayer(port_feature["layer"]) - - new_pin_width = pdk.get_grule(port_feature["layer"])["min_width"] - new_port = rectangle(layer=new_port_layerPin, size=(new_pin_width, new_pin_width),centered=True).copy() # To set rectangle's centroid to the relative (0, 0) - new_port.add_label(text=port["new_port_label"], layer=new_port_layerLabel) - - # To align the new port with the designated port existing in the given component - alignment = port["ref_port_align"] - comp_ref = align_comp_to_port(custom_comp=new_port, align_to=comp.ports[ port["ref_port"] ], alignment=alignment) - comp.add(comp_ref) - comp_ref.movex(port["new_port_move"][0]) - comp_ref.movey(port["new_port_move"][1]) - - if port["new_port_via"] == True: - new_port_via = via_stack(pdk=pdk, glayer1=port["new_port_via_layers"][0], glayer2=port["new_port_via_layers"][1]) - new_port_via_ref = comp.add_ref(new_port_via) - new_port_via_ref.movex(comp_ref.center[0]) - new_port_via_ref.movey(comp_ref.center[1]) - - # To register the new port as an external I/O port of the top-level component - comp.add_port(name=port["new_port"], center=new_port.center, width=new_pin_width, orientation=0, layer=new_port_layerDraw) - - return comp - -def port_with_wire(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: - new_port_layer = pdk.get_glayer(port_feature["layer"]) - wire_width = comp.xsize - wire_height = pdk.get_grule(port_feature["layer"])["min_width"] - new_port_center = comp.center - new_port_position_offset = (comp.xsize/2, comp.ysize/2+pdk.util_max_metal_seperation()) - wire_spacing = pdk.get_grule(port_feature["layer"])["min_separation"]+wire_height - port_cnt = 0 - - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - print(f"port_list: {port_list}") - for port in port_list: - # To create the pin where the layer[1] is mapped to 16 - connect_pos = port["connect_pos"] if "connect_pos" in port else "W" - new_wire = add_wire(comp=comp, xsize=wire_width, ysize=wire_height, layer=new_port_layer, port_label=port["new_port_label"], center=new_port_center, position_offset=new_port_position_offset) - new_wire_ref = comp.add_ref(new_wire) - new_wire_ref.movey(-wire_spacing*port_cnt) - comp.add_ports(new_wire_ref.get_ports_list()) # To register all the ports in the wire to the underlying component - edge0 = comp.ports.get(port["ref_port"]) - edge1 = comp.ports.get(port["new_port"]+f"_{connect_pos}") - comp << smart_route(pdk, edge0, edge1) - - port_cnt = port_cnt + 1 # Increment the index indicating the new port - - return comp - -def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ], port_feature: dict[str, str]) -> Component: - ''' - To add external I/O ports onto the cell for LVS - - @ args: - # pdk: please refer to the glayout library - # comp: please refer to the glayout library - # port_list: tuple[ dict[str, Union[float, str]] ] specifying new port's corresponding pin size, and - the name of new port and exiting port managed to align with in the given - component, e.g. - ( - { - "new_port": "drain_new", - "new_port_label": "drain_new_label", - "pin_width": 0.5, # -> Only being used when "port_feature": "pin" - "pin_height": 0.5, # -> Only being used when "port_feature": "pin" - "ref_port": "multiplier_0_drain_E" - }, - { - "new_port": "source_new", - "new_port_label": "source_new_label", - "ref_port": "multiplier_0_source_E", - "connect_pos": "W" # -> for all connect_pos in {W, E} where the - # connect_pos will be set to "W" if connect_pos=None - } - ) - # port_feature: a "dict"-type primitive specifying the feature of the new port, e.g. - {"port_type":"pin", "layer":None} -> To create a rectangle as the new port - {"port_type":"wire", "layer":"met1"} -> To extend the existing port by a wire only - - # return: gdsfactory.Component - - @ Limitations: - # So far, only skywater130 process is validated - ''' - - if port_feature["port_type"] == "pin": - port_type = 0 - elif port_feature["port_type"] == "wire": - port_type = 1 - else: - raise ValueError("The port type must be either pin or wire") - - if port_type == 0: # port of which features pin-added type - port_with_pin(pdk=pdk, comp=comp, port_list=port_list, port_feature=port_feature) - else: # port_type=1, i.e. port of which features wire_only - port_with_wire(pdk=pdk, comp=comp, port_list=port_list, port_feature=port_feature) - - return comp \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 0576b7653..5720c73ae 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -1,43 +1,29 @@ import transmission_gate as tg #from glayout.flow.pdk.gf180_mapped import gf180 from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 -import cell_config as config +import reconfig_inv as reconfig_inv TARGET_PDK = sky130 def main(): - tg_inst = tg.tg_with_inv(pdk=TARGET_PDK, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15) - tg_inst = config.add_port_lvs( - pdk=sky130, - comp=tg_inst, - port_list=[ - { - "new_port": "Vctrl", - "new_port_label": "Vctrl", - "new_port_via": True, - "new_port_via_layers": ("met1", "met2"), - "new_port_move": (0, -TARGET_PDK.get_grule("mcon")["min_separation"]), - "ref_port": "inv_nmos_multiplier_0_gate_E", - "ref_port_align": ("c", "b"), - "connect_pos": "W" # To connce the ref_port to the "west" side of the new port - }#, - #{ - # "new_port": "Vin", - # "new_port_label": "Vin", - # "ref_port": "tg_pmos_multiplier_0_source_W" - #}, - #{ - # "new_port": "Vout", - # "new_port_label": "Vout", - # "ref_port": "tg_nmos_multiplier_0_drain_W", - # "connect_pos": "E" # To connect the ref_port to the "east" side of the new port - #} - ], - port_feature = {"port_type":"pin", "layer":"met1"} # met1 is actually mapped to li1 in sky130 proceess + gate_ctrl_inv = reconfig_inv.reconfig_inv( + pdk=TARGET_PDK, + component_name="gate_ctrl_inv", + pmos_width=1, + pmos_length=0.15, + nmos_width=1, + nmos_length=0.15, + orientation="horizontal" ) - #tg_inst.flatten() - tg_inst.show() - #tg_inst.write_gds("gds/tg_with_inv.gds") + gate_ctrl_inv.show() + gate_ctrl_inv.write_gds("/home/tsengs0/gate_ctrl_inv.gds") + + magic_drc_result = sky130.drc_magic( + layout=gate_ctrl_inv, + design_name=gate_ctrl_inv.name#, + #output_file=f"{absolute_path}/{gate_ctrl_inv.name}.rpt" + ) + print("Magic DRC result: \n", magic_drc_result) if __name__ == "__main__": main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py deleted file mode 100755 index 1692dabbe..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/inv_lib.py +++ /dev/null @@ -1,44 +0,0 @@ -#from glayout.flow.pdk.gf180_mapped import gf180 -from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 -from glayout.flow.pdk.mappedpdk import MappedPDK -from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port -from gdsfactory import Component -from gdsfactory.components import rectangle -from glayout.flow.primitives.fet import pmos -from glayout.flow.primitives.fet import nmos -from glayout.flow.routing.straight_route import straight_route -from glayout.flow.routing.c_route import c_route -from glayout.flow.routing.L_route import L_route -from glayout.flow.routing.smart_route import smart_route - -def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation): - # Create a top level component - top_level = Component(component_name) - # To prepare one PMOS and one NMOS for the subsequent inverter cell construction - pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) - - # Instantiation of above PMOS and NMOS under the top level - pfet_ref = prec_ref_center(pfet) - nfet_ref = prec_ref_center(nfet) - top_level.add(pfet_ref) - top_level.add(nfet_ref) - - # Placement (relative move) - mos_spacing = pdk.util_max_metal_seperation() - if(orientation=="horizontal"): - pfet_ref.rotate(90) - nfet_ref.rotate(90) - else: - pass - pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - - # Routing - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met1") # connected by li1 - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"] , glayer1="met1") # connected by li1 - - # To add the ports - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - - return top_level diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py new file mode 100755 index 000000000..93ccdc341 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py @@ -0,0 +1,76 @@ +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +from glayout.flow.pdk.mappedpdk import MappedPDK +from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port +from gdsfactory import Component +from gdsfactory.components import rectangle +from glayout.flow.primitives.fet import pmos +from glayout.flow.primitives.fet import nmos +from glayout.flow.routing.straight_route import straight_route +from glayout.flow.routing.c_route import c_route +from glayout.flow.routing.L_route import L_route +from glayout.flow.routing.smart_route import smart_route + +#@cell +def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation): + # Create a top level component + top_level = Component(component_name) + # To prepare one PMOS and one NMOS for the subsequent inverter cell construction + pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) + pfet.name="pmos" + nfet.name="nmos" + + # Instantiation of above PMOS and NMOS under the top level + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) + top_level.add(pfet_ref) + top_level.add(nfet_ref) + + # Placement (relative move) + mos_spacing = pdk.util_max_metal_seperation(metal_levels=("met1", "met2", "met3", "met4", "met5")) + if(orientation=="horizontal"): + pfet_ref.rotate(90) + nfet_ref.rotate(90) + else: + pass + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + # Routing + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # connected by li1 + input_route = top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"] , glayer1="met2") # connected by li1 + + # To add the ports + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the inverter + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_E"), None)) + # --- Port: Y, i.e. output of the inverver + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) + # --- Port: VDD + VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VDD_pin.add_label(text="VDD", layer=met1_label) + pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) + # --- Port: VSS + VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VSS_pin.add_label(text="VSS", layer=met1_label) + pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) + + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) + + return top_level diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb deleted file mode 100644 index 45d4fc14b..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/tg_gen.ipynb +++ /dev/null @@ -1,2326 +0,0 @@ -{ - "nbformat": 4, - "nbformat_minor": 0, - "metadata": { - "colab": { - "provenance": [], - "include_colab_link": true - }, - "kernelspec": { - "name": "python3", - "display_name": "Python 3" - }, - "language_info": { - "name": "python" - } - }, - "cells": [ - { - "cell_type": "markdown", - "metadata": { - "id": "view-in-github", - "colab_type": "text" - }, - "source": [ - "\"Open" - ] - }, - { - "cell_type": "markdown", - "source": [ - "#Chipathon2024　SaltyChip Group\n", - "##テグさんのトランスミッションゲートをnotebbokで表示されるようにしてみた。\n", - "最初にOpenFASoCをクーロンして、sky130、gf180、gdsfactoryをインストールします。\n", - "micromambaを使ったバイナリ依存klayoutをインストールします。\n", - "\n", - "\n", - "\n", - "* Chipathon2024 GitHub:\n", - "https://github.com/sscs-ose/sscs-ose-chipathon.github.io\n", - "\n", - "\n", - "\n", - "\n", - "\n" - ], - "metadata": { - "id": "o2n-cd6kYdjt" - } - }, - { - "cell_type": "code", - "execution_count": 4, - "metadata": { - "colab": { - "base_uri": "https://localhost:8080/", - "height": 1000 - }, - "id": "2fBvSrYFYB1K", - "outputId": "90eb55c6-a4e2-42cf-966d-e79c278aaf28" - }, - "outputs": [ - { - "output_type": "stream", - "name": "stdout", - "text": [ - "Cloning into 'OpenFASOC'...\n", - "remote: Enumerating objects: 16501, done.\u001b[K\n", - "remote: Counting objects: 100% (3739/3739), done.\u001b[K\n", - "remote: Compressing objects: 100% (549/549), done.\u001b[K\n", - "remote: Total 16501 (delta 3311), reused 3398 (delta 3185), pack-reused 12762 (from 1)\u001b[K\n", - "Receiving objects: 100% (16501/16501), 410.32 MiB | 20.14 MiB/s, done.\n", - "Resolving deltas: 100% (10104/10104), done.\n", - "Updating files: 100% (1849/1849), done.\n", - "Collecting sky130\n", - " Downloading sky130-0.12.2-py3-none-any.whl.metadata (1.6 kB)\n", - "Collecting gdsfactory~=8.5.2 (from sky130)\n", - " Downloading gdsfactory-8.5.6-py3-none-any.whl.metadata (11 kB)\n", - "Collecting PySpice (from sky130)\n", - " Downloading PySpice-1.5-py2.py3-none-any.whl.metadata (15 kB)\n", - "Requirement already satisfied: jinja2<4 in /usr/local/lib/python3.10/dist-packages (from gdsfactory~=8.5.2->sky130) (3.1.4)\n", - "Collecting loguru<1 (from gdsfactory~=8.5.2->sky130)\n", - " Downloading loguru-0.7.2-py3-none-any.whl.metadata (23 kB)\n", - "Requirement already satisfied: matplotlib<4 in /usr/local/lib/python3.10/dist-packages (from gdsfactory~=8.5.2->sky130) (3.8.0)\n", - "Requirement already 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"Requirement already satisfied: pycparser in /usr/local/lib/python3.10/dist-packages (from cffi>=1.0.1->argon2-cffi-bindings->argon2-cffi->notebook>=4.4.1->widgetsnbextension~=3.6.0->ipywidgets->gdsfactory<7.17,>=7.16.0->gf180) (2.22)\n", - "Requirement already satisfied: anyio<4,>=3.1.0 in /usr/local/lib/python3.10/dist-packages (from jupyter-server<3,>=1.8->notebook-shim>=0.2.3->nbclassic>=0.4.7->notebook>=4.4.1->widgetsnbextension~=3.6.0->ipywidgets->gdsfactory<7.17,>=7.16.0->gf180) (3.7.1)\n", - "Requirement already satisfied: websocket-client in /usr/local/lib/python3.10/dist-packages (from jupyter-server<3,>=1.8->notebook-shim>=0.2.3->nbclassic>=0.4.7->notebook>=4.4.1->widgetsnbextension~=3.6.0->ipywidgets->gdsfactory<7.17,>=7.16.0->gf180) (1.8.0)\n", - "Requirement already satisfied: sniffio>=1.1 in /usr/local/lib/python3.10/dist-packages (from anyio<4,>=3.1.0->jupyter-server<3,>=1.8->notebook-shim>=0.2.3->nbclassic>=0.4.7->notebook>=4.4.1->widgetsnbextension~=3.6.0->ipywidgets->gdsfactory<7.17,>=7.16.0->gf180) (1.3.1)\n", - "Requirement already satisfied: exceptiongroup in /usr/local/lib/python3.10/dist-packages (from anyio<4,>=3.1.0->jupyter-server<3,>=1.8->notebook-shim>=0.2.3->nbclassic>=0.4.7->notebook>=4.4.1->widgetsnbextension~=3.6.0->ipywidgets->gdsfactory<7.17,>=7.16.0->gf180) (1.2.2)\n", - "Downloading gf180-0.1.0-py3-none-any.whl (135 kB)\n", - "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m135.6/135.6 kB\u001b[0m \u001b[31m8.8 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", - "\u001b[?25hDownloading PrettyPrintTree-2.0.1-py3-none-any.whl (14 kB)\n", - "Downloading svgutils-0.3.4-py3-none-any.whl (10 kB)\n", - "Downloading gdsfactory-7.16.0-py3-none-any.whl (834 kB)\n", - "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m834.2/834.2 kB\u001b[0m \u001b[31m33.1 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", - "\u001b[?25hDownloading cmd2-2.5.5-py3-none-any.whl (151 kB)\n", - "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m151.3/151.3 kB\u001b[0m \u001b[31m12.7 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", - 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"\u001b[?25hDownloading spectate-1.0.1-py2.py3-none-any.whl (11 kB)\n", - "Building wheels for collected packages: flatdict\n", - " Building wheel for flatdict (setup.py) ... \u001b[?25l\u001b[?25hdone\n", - " Created wheel for flatdict: filename=flatdict-4.0.1-py3-none-any.whl size=6928 sha256=cbe7b9ecdeb813ed4b936db444d4d7b1e3115b3811fed30a7561ac5da3fd548a\n", - " Stored in directory: /root/.cache/pip/wheels/71/12/62/88c5bf37619c2d7481eedb8abd0dde6674e88dce45a7805a6f\n", - "Successfully built flatdict\n", - "Installing collected packages: pyglet, flatdict, trimesh, svgutils, spectate, pydantic-core, gdstk, colorama, cmd2, pydantic, prettyprinttree, pydantic-settings, kfactory, ipympl, ipycytoscape, gdsfactory, gf180\n", - " Attempting uninstall: trimesh\n", - " Found existing installation: trimesh 4.4.9\n", - " Uninstalling trimesh-4.4.9:\n", - " Successfully uninstalled trimesh-4.4.9\n", - " Attempting uninstall: pydantic-core\n", - " Found existing installation: pydantic_core 2.20.1\n", - " Uninstalling pydantic_core-2.20.1:\n", - " Successfully uninstalled pydantic_core-2.20.1\n", - " Attempting uninstall: pydantic\n", - " Found existing installation: pydantic 2.8.2\n", - " Uninstalling pydantic-2.8.2:\n", - " Successfully uninstalled pydantic-2.8.2\n", - " Attempting uninstall: pydantic-settings\n", - " Found existing installation: pydantic-settings 2.6.1\n", - " Uninstalling pydantic-settings-2.6.1:\n", - " Successfully uninstalled pydantic-settings-2.6.1\n", - " Attempting uninstall: kfactory\n", - " Found existing installation: kfactory 0.18.4\n", - " Uninstalling kfactory-0.18.4:\n", - " Successfully uninstalled kfactory-0.18.4\n", - " Attempting uninstall: gdsfactory\n", - " Found existing installation: gdsfactory 8.5.6\n", - " Uninstalling gdsfactory-8.5.6:\n", - " Successfully uninstalled gdsfactory-8.5.6\n", - "\u001b[31mERROR: pip's dependency resolver does not currently take into account all the packages that are installed. This behaviour is the source of the following dependency conflicts.\n", - "albumentations 1.4.20 requires pydantic>=2.7.0, but you have pydantic 2.6.4 which is incompatible.\n", - "langchain 0.3.7 requires pydantic<3.0.0,>=2.7.4, but you have pydantic 2.6.4 which is incompatible.\n", - "sky130 0.12.2 requires gdsfactory~=8.5.2, but you have gdsfactory 7.16.0 which is incompatible.\u001b[0m\u001b[31m\n", - "\u001b[0mSuccessfully installed cmd2-2.5.5 colorama-0.4.6 flatdict-4.0.1 gdsfactory-7.16.0 gdstk-0.9.57 gf180-0.1.0 ipycytoscape-1.3.3 ipympl-0.9.4 kfactory-0.11.4 prettyprinttree-2.0.1 pydantic-2.6.4 pydantic-core-2.16.3 pydantic-settings-2.2.1 pyglet-1.5.29 spectate-1.0.1 svgutils-0.3.4 trimesh-4.1.8\n", - "Collecting gdsfactory==7.7.0\n", - " Downloading gdsfactory-7.7.0-py3-none-any.whl.metadata (10 kB)\n", - "Requirement already satisfied: flatdict in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.0.1)\n", - "Requirement already satisfied: gdstk<1 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.9.57)\n", - "Requirement already satisfied: jinja2 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.1.4)\n", - "Requirement already satisfied: loguru<1 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.7.2)\n", - "Requirement already satisfied: matplotlib in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.8.0)\n", - "Requirement already satisfied: numpy in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (1.26.4)\n", - "Requirement already satisfied: omegaconf<3 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.3.0)\n", - "Requirement already satisfied: orjson in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (3.10.11)\n", - "Requirement already satisfied: pandas in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.2.2)\n", - "Requirement already satisfied: pydantic<3,>=2 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.6.4)\n", - "Requirement already satisfied: pydantic-settings in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.2.1)\n", - "Requirement already satisfied: pydantic-extra-types in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.10.0)\n", - "Requirement already satisfied: pyyaml in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (6.0.2)\n", - "Requirement already satisfied: qrcode in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (8.0)\n", - "Requirement already satisfied: rectpack in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.2.2)\n", - "Requirement already satisfied: rich in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (13.9.4)\n", - "Requirement already satisfied: scipy in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (1.13.1)\n", - "Requirement already satisfied: shapely<3 in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (2.0.6)\n", - "Requirement already satisfied: toolz in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.12.1)\n", - "Requirement already satisfied: tqdm in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.66.6)\n", - "Requirement already satisfied: types-PyYAML in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (6.0.12.20240917)\n", - "Requirement already satisfied: typer in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (0.13.0)\n", - "Requirement already satisfied: watchdog in /usr/local/lib/python3.10/dist-packages (from gdsfactory==7.7.0) (4.0.2)\n", - "Requirement already satisfied: typing_extensions in /usr/local/lib/python3.10/dist-packages (from gdstk<1->gdsfactory==7.7.0) (4.12.2)\n", - "Requirement already satisfied: antlr4-python3-runtime==4.9.* in /usr/local/lib/python3.10/dist-packages (from omegaconf<3->gdsfactory==7.7.0) (4.9.3)\n", - "Requirement already satisfied: annotated-types>=0.4.0 in /usr/local/lib/python3.10/dist-packages (from pydantic<3,>=2->gdsfactory==7.7.0) (0.7.0)\n", - "Requirement already satisfied: pydantic-core==2.16.3 in /usr/local/lib/python3.10/dist-packages (from pydantic<3,>=2->gdsfactory==7.7.0) (2.16.3)\n", - "Requirement already satisfied: MarkupSafe>=2.0 in /usr/local/lib/python3.10/dist-packages (from jinja2->gdsfactory==7.7.0) (3.0.2)\n", - "Requirement already satisfied: contourpy>=1.0.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (1.3.0)\n", - "Requirement already satisfied: cycler>=0.10 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (0.12.1)\n", - "Requirement already satisfied: fonttools>=4.22.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (4.54.1)\n", - "Requirement already satisfied: kiwisolver>=1.0.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (1.4.7)\n", - "Requirement already satisfied: packaging>=20.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (24.2)\n", - "Requirement already satisfied: pillow>=6.2.0 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (11.0.0)\n", - "Requirement already satisfied: pyparsing>=2.3.1 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (3.2.0)\n", - "Requirement already satisfied: python-dateutil>=2.7 in /usr/local/lib/python3.10/dist-packages (from matplotlib->gdsfactory==7.7.0) (2.8.2)\n", - "Requirement already satisfied: pytz>=2020.1 in /usr/local/lib/python3.10/dist-packages (from pandas->gdsfactory==7.7.0) (2024.2)\n", - "Requirement already satisfied: tzdata>=2022.7 in /usr/local/lib/python3.10/dist-packages (from pandas->gdsfactory==7.7.0) (2024.2)\n", - "Requirement already satisfied: python-dotenv>=0.21.0 in /usr/local/lib/python3.10/dist-packages (from pydantic-settings->gdsfactory==7.7.0) (1.0.1)\n", - "Requirement already satisfied: markdown-it-py>=2.2.0 in /usr/local/lib/python3.10/dist-packages (from rich->gdsfactory==7.7.0) (3.0.0)\n", - "Requirement already satisfied: pygments<3.0.0,>=2.13.0 in /usr/local/lib/python3.10/dist-packages (from rich->gdsfactory==7.7.0) (2.18.0)\n", - "Requirement already satisfied: click>=8.0.0 in /usr/local/lib/python3.10/dist-packages (from typer->gdsfactory==7.7.0) (8.1.7)\n", - "Requirement already satisfied: shellingham>=1.3.0 in /usr/local/lib/python3.10/dist-packages (from typer->gdsfactory==7.7.0) (1.5.4)\n", - "Requirement already satisfied: mdurl~=0.1 in /usr/local/lib/python3.10/dist-packages (from markdown-it-py>=2.2.0->rich->gdsfactory==7.7.0) (0.1.2)\n", - "Requirement already satisfied: six>=1.5 in /usr/local/lib/python3.10/dist-packages (from python-dateutil>=2.7->matplotlib->gdsfactory==7.7.0) (1.16.0)\n", - "Downloading gdsfactory-7.7.0-py3-none-any.whl (801 kB)\n", - "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m801.2/801.2 kB\u001b[0m \u001b[31m16.0 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", - "\u001b[?25hInstalling collected packages: gdsfactory\n", - " Attempting uninstall: gdsfactory\n", - " Found existing installation: gdsfactory 7.16.0\n", - " Uninstalling gdsfactory-7.16.0:\n", - " Successfully uninstalled gdsfactory-7.16.0\n", - "\u001b[31mERROR: pip's dependency resolver does not currently take into account all the packages that are installed. This behaviour is the source of the following dependency conflicts.\n", - "gf180 0.1.0 requires gdsfactory<7.17,>=7.16.0, but you have gdsfactory 7.7.0 which is incompatible.\n", - "sky130 0.12.2 requires gdsfactory~=8.5.2, but you have gdsfactory 7.7.0 which is incompatible.\u001b[0m\u001b[31m\n", - "\u001b[0mSuccessfully installed gdsfactory-7.7.0\n", - "bin/micromamba\n", - "env: CONDA_PREFIX=/content/conda-env\n", - "Empty environment created at prefix: /content/conda-env\n", - "\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", - "\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", - "litex-hub/linux-64.. ⣾ \n", - "litex-hub/noarch (.. ⣾ \n", - "main/linux-64 (che.. ⣾ \n", - "main/noarch (check.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", - "litex-hub/linux-64.. ⣾ \n", - "litex-hub/noarch (.. ⣾ \n", - "main/linux-64 (che.. ⣾ \n", - "main/noarch (check.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", - "litex-hub/linux-64.. ⣾ \n", - "litex-hub/noarch (.. ⣾ \n", - "main/linux-64 (che.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.4s\n", - "litex-hub/noarch (.. ⣾ \n", - "main/linux-64 (che.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", - "litex-hub/noarch (.. ⣾ \u001b[2K\u001b[1A\u001b[2K\u001b[0G\u001b[?25h\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", - "\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", - "litex-hub/linux-64 | \n", - "litex-hub/noarch ⣾ \n", - "main/linux-64 ⣾ \n", - "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", - "litex-hub/linux-64 | \n", - "litex-hub/noarch ⣾ \n", - "main/linux-64 ⣾ \n", - "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", - "litex-hub/linux-64 | \n", - "litex-hub/noarch ⣾ \n", - "main/linux-64 ⣾ \n", - "main/noarch | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glitex-hub/noarch \n", - "[+] 0.4s\n", - "litex-hub/linux-64 | \n", - "main/linux-64 ⣾ \n", - "main/noarch 3%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", - "litex-hub/linux-64 | \n", - "main/linux-64 2%\n", - "main/noarch 15%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.6s\n", - "litex-hub/linux-64 | \n", - "main/linux-64 9%\n", - "main/noarch 36%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gmain/noarch \n", - "[+] 0.7s\n", - "litex-hub/linux-64 | \n", - "main/linux-64 11%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.8s\n", - "litex-hub/linux-64 3%\n", - "main/linux-64 42%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.9s\n", - "litex-hub/linux-64 27%\n", - "main/linux-64 83%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gmain/linux-64 \n", - "[+] 1.0s\n", - "litex-hub/linux-64 57%\u001b[2K\u001b[1A\u001b[2K\u001b[0Glitex-hub/linux-64 \n", - "\u001b[?25h\n", - "\u001b[31m\u001b[1merror libmamba\u001b[m Could not lock non-existing path '/root/.mamba/pkgs'\n", - "\n", - "Transaction\n", - "\n", - " Prefix: /content/conda-env\n", - "\n", - " Updating specs:\n", - "\n", - " - klayout\n", - "\n", - "\n", - " Package Version Build Channel Size\n", - "─────────────────────────────────────────────────────────────────────────────────────────\n", - " Install:\n", - "─────────────────────────────────────────────────────────────────────────────────────────\n", - "\n", - " \u001b[32m+ _libgcc_mutex \u001b[0m 0.1 main main 3kB\n", - " \u001b[32m+ _openmp_mutex \u001b[0m 5.1 1_gnu main 21kB\n", - " \u001b[32m+ bzip2 \u001b[0m 1.0.8 h5eee18b_6 main 428kB\n", - " \u001b[32m+ c-ares \u001b[0m 1.19.1 h5eee18b_0 main 116kB\n", - " \u001b[32m+ ca-certificates \u001b[0m 2024.9.24 h06a4308_0 main 140kB\n", - " \u001b[32m+ certifi \u001b[0m 2022.12.7 py37h06a4308_0 main 155kB\n", - " \u001b[32m+ curl \u001b[0m 8.2.1 h37d81fd_0 main 89kB\n", - " \u001b[32m+ dbus \u001b[0m 1.13.18 hb2f20db_0 main 600kB\n", - " \u001b[32m+ expat \u001b[0m 2.6.3 h6a678d5_0 main 201kB\n", - " \u001b[32m+ fontconfig \u001b[0m 2.13.0 h9420a91_0 main 298kB\n", - " \u001b[32m+ freetype \u001b[0m 2.12.1 h4a9f257_0 main 972kB\n", - " \u001b[32m+ glib \u001b[0m 2.78.4 h6a678d5_0 main 499kB\n", - " \u001b[32m+ glib-tools \u001b[0m 2.78.4 h6a678d5_0 main 113kB\n", - " \u001b[32m+ gmp \u001b[0m 6.2.1 h295c915_3 main 822kB\n", - " \u001b[32m+ gst-plugins-base\u001b[0m 1.14.1 h6a678d5_1 main 2MB\n", - " \u001b[32m+ gstreamer \u001b[0m 1.14.1 h5eee18b_1 main 2MB\n", - " \u001b[32m+ icu \u001b[0m 58.2 he6710b0_3 main 24MB\n", - " \u001b[32m+ jpeg \u001b[0m 9e h5eee18b_3 main 284kB\n", - " \u001b[32m+ klayout \u001b[0m 0.28.17_212_gfa14afbbf 20240223_100318_py37 litex-hub 27MB\n", - " \u001b[32m+ krb5 \u001b[0m 1.20.1 h568e23c_1 main 1MB\n", - " \u001b[32m+ ld_impl_linux-64\u001b[0m 2.40 h12ee557_0 main 723kB\n", - " \u001b[32m+ libcurl \u001b[0m 8.2.1 h91b91d3_0 main 386kB\n", - " \u001b[32m+ libedit \u001b[0m 3.1.20230828 h5eee18b_0 main 196kB\n", - " \u001b[32m+ libev \u001b[0m 4.33 h7f8727e_1 main 109kB\n", - " \u001b[32m+ libffi \u001b[0m 3.4.4 h6a678d5_1 main 154kB\n", - " \u001b[32m+ libgcc-ng \u001b[0m 11.2.0 h1234567_1 main 9MB\n", - " \u001b[32m+ libgit2 \u001b[0m 1.6.4 ha637b67_0 main 1MB\n", - " \u001b[32m+ libglib \u001b[0m 2.78.4 hdc74915_0 main 2MB\n", - " \u001b[32m+ libgomp \u001b[0m 11.2.0 h1234567_1 main 573kB\n", - " \u001b[32m+ libiconv \u001b[0m 1.16 h5eee18b_3 main 1MB\n", - " \u001b[32m+ libnghttp2 \u001b[0m 1.52.0 ha637b67_1 main 717kB\n", - " \u001b[32m+ libpng \u001b[0m 1.6.39 h5eee18b_0 main 363kB\n", - " \u001b[32m+ libssh2 \u001b[0m 1.10.0 h37d81fd_2 main 312kB\n", - " \u001b[32m+ libstdcxx-ng \u001b[0m 11.2.0 h1234567_1 main 6MB\n", - " \u001b[32m+ libuuid \u001b[0m 1.41.5 h5eee18b_0 main 29kB\n", - " \u001b[32m+ libxcb \u001b[0m 1.15 h7f8727e_0 main 623kB\n", - " \u001b[32m+ libxml2 \u001b[0m 2.9.9 20220706_155948 litex-hub 1MB\n", - " \u001b[32m+ ncurses \u001b[0m 6.4 h6a678d5_0 main 1MB\n", - " \u001b[32m+ openssl \u001b[0m 1.1.1w h7f8727e_0 main 4MB\n", - " \u001b[32m+ pcre2 \u001b[0m 10.42 hebb0a14_1 main 3MB\n", - " \u001b[32m+ pip \u001b[0m 22.3.1 py37h06a4308_0 main 3MB\n", - " \u001b[32m+ python \u001b[0m 3.7.16 h7a1cb2a_0 main 49MB\n", - " \u001b[32m+ qt \u001b[0m 5.9.7 h5867ecd_1 main 90MB\n", - " \u001b[32m+ readline \u001b[0m 8.2 h5eee18b_0 main 468kB\n", - " \u001b[32m+ ruby \u001b[0m 2.5.1 haf1161a_0 main 5MB\n", - " \u001b[32m+ setuptools \u001b[0m 65.6.3 py37h06a4308_0 main 1MB\n", - " \u001b[32m+ sqlite \u001b[0m 3.45.3 h5eee18b_0 main 2MB\n", - " \u001b[32m+ tk \u001b[0m 8.6.14 h39e8969_0 main 4MB\n", - " \u001b[32m+ wheel \u001b[0m 0.38.4 py37h06a4308_0 main 59kB\n", - " \u001b[32m+ xz \u001b[0m 5.4.6 h5eee18b_1 main 717kB\n", - " \u001b[32m+ yaml \u001b[0m 0.1.7 had09818_2 main 87kB\n", - " \u001b[32m+ zlib \u001b[0m 1.2.13 h5eee18b_1 main 127kB\n", - "\n", - " Summary:\n", - "\n", - " Install: 52 packages\n", - "\n", - " Total download: 249MB\n", - "\n", - "─────────────────────────────────────────────────────────────────────────────────────────\n", - "\n", - "\n", - "\n", - "Transaction starting\n", - "\u001b[?25l\u001b[2K\u001b[0G[+] 0.0s\n", - "Downloading 5%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.1s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.2s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.3s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.4s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.5s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.6s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.7s\n", - "Downloading (5) 0%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.8s\n", - "Downloading (5) 1%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 0.9s\n", - "Downloading (5) 1%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.0s\n", - "Downloading (5) 1%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.1s\n", - "Downloading (5) 3%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.2s\n", - "Downloading (5) 6%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgcc-ng 8.9MB @ 7.4MB/s 1.2s\n", - "[+] 1.3s\n", - "Downloading (5) 10%\n", - "Extracting 0%\u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.4s\n", - "Downloading (5) 13%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.5s\n", - "Downloading (5) 18%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.6s\n", - "Downloading (5) 23%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.7s\n", - "Downloading (5) 31%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 1.8s\n", - "Downloading (5) 39%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gklayout 26.7MB @ 14.3MB/s 1.8s\n", - "[+] 1.9s\n", - "Downloading (5) 43%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.0s\n", - "Downloading (5) 45%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gicu 23.8MB @ 11.7MB/s 2.0s\n", - "[+] 2.1s\n", - "Downloading (5) 47%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.2s\n", - "Downloading (5) 49%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.3s\n", - "Downloading (5) 52%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibstdcxx-ng 6.4MB @ 4.6MB/s 1.2s\n", - "[+] 2.4s\n", - "Downloading (5) 58%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.5s\n", - "Downloading (5) 61%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.6s\n", - "Downloading (5) 65%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.7s\n", - "Downloading (5) 68%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 2.8s\n", - "Downloading (5) 70%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpython 48.7MB @ 16.5MB/s 2.8s\n", - "[+] 2.9s\n", - "Downloading (5) 72%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.0s\n", - "Downloading (5) 74%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.1s\n", - "Downloading (5) 75%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.2s\n", - "Downloading (5) 78%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.3s\n", - "Downloading (5) 80%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gopenssl 4.0MB @ 2.9MB/s 1.3s\n", - "ruby 5.3MB @ 3.1MB/s 1.4s\n", - "[+] 3.4s\n", - "Downloading (5) 80%\n", - "Extracting (5) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.5s\n", - "Downloading (5) 80%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.6s\n", - "Downloading (5) 81%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 3.7s\n", - "Downloading (5) 83%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gtk 3.6MB @ 2.4MB/s 1.4s\n", - "[+] 3.8s\n", - "Downloading (5) 84%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpcre2 3.3MB @ 3.2MB/s 1.0s\n", - "[+] 3.9s\n", - "Downloading (5) 85%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.0s\n", - "Downloading (5) 86%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.1s\n", - "Downloading (5) 87%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.2s\n", - "Downloading (5) 88%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.3s\n", - "Downloading (5) 88%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.4s\n", - "Downloading (5) 89%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.5s\n", - "Downloading (5) 92%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gpip 2.8MB @ 2.2MB/s 1.2s\n", - "[+] 4.6s\n", - "Downloading (5) 93%\n", - "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Ggst-plugins-base 2.3MB @ 1.6MB/s 1.3s\n", - "[+] 4.7s\n", - "Downloading (5) 94%\n", - "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gsqlite 1.7MB @ 1.5MB/s 0.9s\n", - "gstreamer 1.7MB @ 1.8MB/s 0.9s\n", - "[+] 4.8s\n", - "Downloading (5) 96%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 4.9s\n", - "Downloading (5) 96%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.0s\n", - "Downloading (5) 97%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gqt 90.0MB @ 17.8MB/s 5.0s\n", - "[+] 5.1s\n", - "Downloading (5) 97%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.2s\n", - "Downloading (5) 97%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.3s\n", - "Downloading (5) 98%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibglib 1.6MB @ 932.0kB/s 0.9s\n", - "[+] 5.4s\n", - "Downloading (5) 98%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.5s\n", - "Downloading (5) 98%\n", - "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.6s\n", - "Downloading (5) 98%\n", - "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gsetuptools 1.4MB @ 987.1kB/s 1.0s\n", - "libiconv 1.4MB @ 850.5kB/s 1.0s\n", - "krb5 1.4MB @ 849.1kB/s 0.9s\n", - "[+] 5.7s\n", - "Downloading (5) 98%\n", - "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.8s\n", - "Downloading (5) 98%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 5.9s\n", - "Downloading (5) 99%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibxml2 1.4MB @ 834.9kB/s 0.9s\n", - "[+] 6.0s\n", - "Downloading (5) 98%\n", - "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.1s\n", - "Downloading (5) 98%\n", - "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.2s\n", - "Downloading (5) 99%\n", - "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.3s\n", - "Downloading (5) 99%\n", - "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgit2 1.2MB @ 804.6kB/s 1.0s\n", - "[+] 6.4s\n", - "Downloading (5) 99%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.5s\n", - "Downloading (5) 99%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gncurses 1.2MB @ 937.3kB/s 0.9s\n", - "freetype 972.0kB @ 896.8kB/s 0.9s\n", - "[+] 6.6s\n", - "Downloading (5) 99%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.7s\n", - "Downloading (5) 99%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 6.8s\n", - "Downloading (5) 99%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Ggmp 822.4kB @ 698.3kB/s 1.1s\n", - "[+] 6.9s\n", - "Downloading (5) 99%\n", - "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gld_impl_linux-64 723.1kB @ 375.9kB/s 1.0s\n", - "[+] 7.0s\n", - "Downloading (5) 99%\n", - "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.1s\n", - "Downloading (5) 99%\n", - "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.2s\n", - "Downloading (5) 99%\n", - "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibxcb 623.5kB @ 577.3kB/s 0.7s\n", - "libnghttp2 716.6kB @ 539.0kB/s 0.8s\n", - "xz 716.9kB @ 446.2kB/s 0.9s\n", - "[+] 7.3s\n", - "Downloading (5) 99%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.4s\n", - "Downloading (5) 99%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.5s\n", - "Downloading (5) 99%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.6s\n", - "Downloading (5) 99%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.7s\n", - "Downloading (5) 99%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 7.8s\n", - "Downloading (5) 100%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibgomp 573.2kB @ 429.0kB/s 0.9s\n", - "[+] 7.9s\n", - "Downloading (5) 100%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gdbus 600.2kB @ 313.4kB/s 1.1s\n", - "[+] 8.0s\n", - "Downloading (5) 100%\n", - "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.1s\n", - "Downloading (5) 100%\n", - "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gglib 499.0kB @ 409.8kB/s 0.9s\n", - "readline 467.7kB @ 420.7kB/s 0.9s\n", - "bzip2 427.5kB @ 433.5kB/s 0.9s\n", - "[+] 8.2s\n", - "Downloading (5) 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.3s\n", - "Downloading (5) 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.4s\n", - "Downloading (5) 100%\n", - "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.5s\n", - "Downloading (5) 100%\n", - "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 8.6s\n", - "Downloading (5) 100%\n", - "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibssh2 311.8kB @ ??.?MB/s 0.5s\n", - "[+] 8.7s\n", - "Downloading (5) 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibpng 362.6kB @ 468.9kB/s 0.8s\n", - "[+] 8.8s\n", - "Downloading (5) 100%\n", - "Extracting (31) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gfontconfig 297.6kB @ 429.9kB/s 0.7s\n", - "libcurl 386.4kB @ 406.6kB/s 1.0s\n", - "[+] 8.9s\n", - "Downloading (5) 100%\n", - "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gjpeg 283.5kB @ 240.5kB/s 0.7s\n", - "[+] 9.0s\n", - "Downloading (5) 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.1s\n", - "Downloading (5) 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.2s\n", - "Downloading (5) 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.3s\n", - "Downloading (5) 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.4s\n", - "Downloading (5) 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gexpat 200.8kB @ 178.1kB/s 0.8s\n", - "[+] 9.5s\n", - "Downloading (5) 100%\n", - "Extracting (35) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibffi 154.0kB @ 111.1kB/s 0.7s\n", - "libedit 195.8kB @ 243.1kB/s 0.8s\n", - "[+] 9.6s\n", - "Downloading (5) 100%\n", - "Extracting (37) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gcertifi 155.3kB @ 150.2kB/s 0.8s\n", - "ca-certificates 139.9kB @ 91.3kB/s 0.7s\n", - "[+] 9.7s\n", - "Downloading (5) 100%\n", - "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.8s\n", - "Downloading (5) 100%\n", - "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 9.9s\n", - "Downloading (5) 100%\n", - "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gglib-tools 112.6kB @ 275.5kB/s 0.4s\n", - "[+] 10.0s\n", - "Downloading (5) 100%\n", - "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.1s\n", - "Downloading (5) 100%\n", - "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gzlib 127.1kB @ 105.1kB/s 0.7s\n", - "c-ares 116.3kB @ 115.3kB/s 0.7s\n", - "[+] 10.2s\n", - "Downloading (5) 100%\n", - "Extracting (41) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.3s\n", - "Downloading (5) 100%\n", - "Extracting (42) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.4s\n", - "Downloading (5) 100%\n", - "Extracting (42) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gyaml 87.1kB @ ??.?MB/s 0.4s\n", - "libev 108.9kB @ 77.3kB/s 0.8s\n", - "curl 88.8kB @ 80.9kB/s 0.8s\n", - "[+] 10.5s\n", - "Downloading (4) 100%\n", - "Extracting (45) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Gwheel 58.7kB @ 79.1kB/s 0.4s\n", - "[+] 10.6s\n", - "Downloading (3) 100%\n", - "Extracting (46) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 10.7s\n", - "Downloading (3) 100%\n", - "Extracting (46) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0Glibuuid 29.2kB @ 53.0kB/s 0.6s\n", - "[+] 10.8s\n", - "Downloading (2) 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G_libgcc_mutex 3.1kB @ 8.2kB/s 0.4s\n", - "[+] 10.9s\n", - "Downloading (1) 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.0s\n", - "Downloading (1) 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G_openmp_mutex 20.8kB @ 34.4kB/s 0.6s\n", - "[+] 11.1s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.2s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.3s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.4s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.5s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.6s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.7s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.8s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 11.9s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.0s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.1s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.2s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.3s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.4s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.5s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.6s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.7s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.8s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 12.9s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.0s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.1s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.2s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.3s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.4s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.5s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.6s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.7s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.8s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 13.9s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.0s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.1s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.2s\n", - "Downloading 100%\n", - "Extracting (49) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.3s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.4s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.5s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.6s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.7s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.8s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 14.9s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.0s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.1s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.2s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.3s\n", - "Downloading 100%\n", - "Extracting (48) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.4s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.5s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.6s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.7s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.8s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 15.9s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.0s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.1s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.2s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.3s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.4s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.5s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.6s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.7s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.8s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 16.9s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.0s\n", - "Downloading 100%\n", - "Extracting (47) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.1s\n", - "Downloading 100%\n", - "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.2s\n", - "Downloading 100%\n", - "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.3s\n", - "Downloading 100%\n", - "Extracting (44) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.4s\n", - "Downloading 100%\n", - "Extracting (40) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.5s\n", - "Downloading 100%\n", - "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.6s\n", - "Downloading 100%\n", - "Extracting (39) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.7s\n", - "Downloading 100%\n", - "Extracting (38) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.8s\n", - "Downloading 100%\n", - "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 17.9s\n", - "Downloading 100%\n", - "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.0s\n", - "Downloading 100%\n", - "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.1s\n", - "Downloading 100%\n", - "Extracting (36) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.2s\n", - "Downloading 100%\n", - "Extracting (35) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.3s\n", - "Downloading 100%\n", - "Extracting (34) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.4s\n", - "Downloading 100%\n", - "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.5s\n", - "Downloading 100%\n", - "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.6s\n", - "Downloading 100%\n", - "Extracting (33) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.7s\n", - "Downloading 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.8s\n", - "Downloading 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 18.9s\n", - "Downloading 100%\n", - "Extracting (30) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.0s\n", - "Downloading 100%\n", - "Extracting (29) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.1s\n", - "Downloading 100%\n", - "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.2s\n", - "Downloading 100%\n", - "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.3s\n", - "Downloading 100%\n", - "Extracting (28) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.4s\n", - "Downloading 100%\n", - "Extracting (27) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.5s\n", - "Downloading 100%\n", - "Extracting (26) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.6s\n", - "Downloading 100%\n", - "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.7s\n", - "Downloading 100%\n", - "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.8s\n", - "Downloading 100%\n", - "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 19.9s\n", - "Downloading 100%\n", - "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.0s\n", - "Downloading 100%\n", - "Extracting (25) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.1s\n", - "Downloading 100%\n", - "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.2s\n", - "Downloading 100%\n", - "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.3s\n", - "Downloading 100%\n", - "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.4s\n", - "Downloading 100%\n", - "Extracting (24) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.5s\n", - "Downloading 100%\n", - "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.6s\n", - "Downloading 100%\n", - "Extracting (23) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.7s\n", - "Downloading 100%\n", - "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.8s\n", - "Downloading 100%\n", - "Extracting (22) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 20.9s\n", - "Downloading 100%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.0s\n", - "Downloading 100%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.1s\n", - "Downloading 100%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.2s\n", - "Downloading 100%\n", - "Extracting (21) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.3s\n", - "Downloading 100%\n", - "Extracting (20) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.4s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.5s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.6s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.7s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.8s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 21.9s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.0s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.1s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.2s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.3s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.4s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.5s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.6s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.7s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.8s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 22.9s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.0s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.1s\n", - "Downloading 100%\n", - "Extracting (19) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.2s\n", - "Downloading 100%\n", - "Extracting (18) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 23.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 24.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 25.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 26.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 27.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 28.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 29.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 30.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 31.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 32.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 33.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 34.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.4s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.5s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.6s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.7s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.8s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 35.9s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.0s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.1s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.2s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.3s\n", - "Downloading 100%\n", - "Extracting (17) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.4s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.5s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.6s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.7s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.8s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 36.9s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.0s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.1s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.2s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.3s\n", - "Downloading 100%\n", - "Extracting (16) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.4s\n", - "Downloading 100%\n", - "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.5s\n", - "Downloading 100%\n", - "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.6s\n", - "Downloading 100%\n", - "Extracting (15) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.7s\n", - "Downloading 100%\n", - "Extracting (14) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.8s\n", - "Downloading 100%\n", - "Extracting (13) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 37.9s\n", - "Downloading 100%\n", - "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.0s\n", - "Downloading 100%\n", - "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.1s\n", - "Downloading 100%\n", - "Extracting (12) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.2s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.3s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.4s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.5s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.6s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.7s\n", - "Downloading 100%\n", - "Extracting (11) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.8s\n", - "Downloading 100%\n", - "Extracting (10) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 38.9s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.0s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.1s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.2s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.3s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.4s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.5s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.6s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.7s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.8s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 39.9s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.0s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.1s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.2s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.3s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.4s\n", - "Downloading 100%\n", - "Extracting (9) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.5s\n", - "Downloading 100%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.6s\n", - "Downloading 100%\n", - "Extracting (7) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.7s\n", - "Downloading 100%\n", - "Extracting (6) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.8s\n", - "Downloading 100%\n", - "Extracting (5) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 40.9s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.0s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.1s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.2s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.3s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.4s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.5s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.6s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.7s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.8s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 41.9s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.0s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.1s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.2s\n", - "Downloading 100%\n", - "Extracting (4) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.3s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.4s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.5s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.6s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.7s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.8s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 42.9s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.0s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.1s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.2s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.3s\n", - "Downloading 100%\n", - "Extracting (3) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.4s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.5s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.6s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.7s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.8s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 43.9s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.0s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.1s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.2s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.3s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.4s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.5s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.6s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.7s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.8s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 44.9s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.0s\n", - "Downloading 100%\n", - "Extracting (2) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.1s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.2s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.3s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.4s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.5s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.6s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.7s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.8s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 45.9s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.0s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.1s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.2s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.3s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.4s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.5s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.6s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.7s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.8s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 46.9s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.0s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.1s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.2s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.3s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.4s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.5s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.6s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.7s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.8s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 47.9s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G[+] 48.0s\n", - "Downloading 100%\n", - "Extracting (1) | \u001b[2K\u001b[1A\u001b[2K\u001b[1A\u001b[2K\u001b[0G\u001b[?25hLinking _libgcc_mutex-0.1-main\n", - "Linking libstdcxx-ng-11.2.0-h1234567_1\n", - "Linking ld_impl_linux-64-2.40-h12ee557_0\n", - "Linking ca-certificates-2024.9.24-h06a4308_0\n", - "Linking libgomp-11.2.0-h1234567_1\n", - "Linking _openmp_mutex-5.1-1_gnu\n", - "Linking libgcc-ng-11.2.0-h1234567_1\n", - "Linking yaml-0.1.7-had09818_2\n", - "Linking libuuid-1.41.5-h5eee18b_0\n", - "Linking gmp-6.2.1-h295c915_3\n", - "Linking ncurses-6.4-h6a678d5_0\n", - "Linking bzip2-1.0.8-h5eee18b_6\n", - "Linking libev-4.33-h7f8727e_1\n", - "Linking c-ares-1.19.1-h5eee18b_0\n", - "Linking libiconv-1.16-h5eee18b_3\n", - "Linking libffi-3.4.4-h6a678d5_1\n", - "Linking xz-5.4.6-h5eee18b_1\n", - "Linking zlib-1.2.13-h5eee18b_1\n", - "Linking openssl-1.1.1w-h7f8727e_0\n", - "Linking libxcb-1.15-h7f8727e_0\n", - "Linking jpeg-9e-h5eee18b_3\n", - "Linking icu-58.2-he6710b0_3\n", - "Linking expat-2.6.3-h6a678d5_0\n", - "Linking libedit-3.1.20230828-h5eee18b_0\n", - "Linking readline-8.2-h5eee18b_0\n", - "Linking tk-8.6.14-h39e8969_0\n", - "Linking pcre2-10.42-hebb0a14_1\n", - "Linking libpng-1.6.39-h5eee18b_0\n", - "Linking libssh2-1.10.0-h37d81fd_2\n", - "Linking libnghttp2-1.52.0-ha637b67_1\n", - "Linking krb5-1.20.1-h568e23c_1\n", - "Linking sqlite-3.45.3-h5eee18b_0\n", - "Linking ruby-2.5.1-haf1161a_0\n", - "Linking libglib-2.78.4-hdc74915_0\n", - "Linking freetype-2.12.1-h4a9f257_0\n", - "Linking libcurl-8.2.1-h91b91d3_0\n", - "Linking python-3.7.16-h7a1cb2a_0\n", - "Linking wheel-0.38.4-py37h06a4308_0\n", - "Linking glib-tools-2.78.4-h6a678d5_0\n", - "Linking curl-8.2.1-h37d81fd_0\n", - "Linking certifi-2022.12.7-py37h06a4308_0\n", - "Linking libgit2-1.6.4-ha637b67_0\n", - "Linking setuptools-65.6.3-py37h06a4308_0\n", - "Linking pip-22.3.1-py37h06a4308_0\n", - "Linking glib-2.78.4-h6a678d5_0\n", - "Linking gstreamer-1.14.1-h5eee18b_1\n", - "Linking dbus-1.13.18-hb2f20db_0\n", - "Linking gst-plugins-base-1.14.1-h6a678d5_1\n", - "Linking libxml2-2.9.9-20220706_155948\n", - "Linking fontconfig-2.13.0-h9420a91_0\n", - "Linking qt-5.9.7-h5867ecd_1\n", - "Linking klayout-0.28.17_212_gfa14afbbf-20240223_100318_py37\n", - "\n", - "Transaction finished\n", - "\n" - ] - } - ], - "source": [ - "# Setup the environment for the OpenFASOC GDSFactory generator\n", - "# You only need to run this block once!\n", - "\n", - "# Clone OpenFASoC\n", - "!git clone https://github.com/idea-fasoc/OpenFASOC\n", - "# Install python dependencies\n", - "!pip install sky130\n", - "!pip install gf180 prettyprinttree svgutils\n", - "!pip install gdsfactory==7.7.0\n", - "\n", - "import pathlib\n", - "import os\n", - "# Install KLayout (via conda)\n", - "!curl -Ls https://micro.mamba.pm/api/micromamba/linux-64/latest | tar -xvj bin/micromamba\n", - "conda_prefix_path = pathlib.Path('conda-env')\n", - "CONDA_PREFIX = str(conda_prefix_path.resolve())\n", - "%env CONDA_PREFIX={CONDA_PREFIX}\n", - "\n", - "!bin/micromamba create --yes --prefix $CONDA_PREFIX\n", - "# Install from the litex-hub channel\n", - "!bin/micromamba install --yes --prefix $CONDA_PREFIX \\\n", - " --channel litex-hub \\\n", - " --channel main \\\n", - " klayout" - ] - }, - { - "cell_type": "markdown", - "source": [ - " klayoutバイナリをシステムパスに追加し、GLayoutディレクトリに移動します。\n", - "（カーネルを再起動する度に実行する必要があります。）\n", - "\n", - "\n" - ], - "metadata": { - "id": "zjJ2eUWiaUbR" - } - }, - { - "cell_type": "code", - "source": [ - "# Setup the environment for the OpenFASOC GDSFactory generator\n", - "\n", - "# Adding micro-mamba binary directory to the PATH\n", - "# This directory contains Klayout\n", - "import pathlib\n", - "import os\n", - "conda_prefix_path = pathlib.Path('conda-env')\n", - "CONDA_PREFIX = str(conda_prefix_path.resolve())\n", - "\n", - "%env CONDA_PREFIX={CONDA_PREFIX}\n", - "# Add conda packages to the PATH\n", - "PATH = os.environ['PATH']\n", - "%env PATH={PATH}:{CONDA_PREFIX}/bin\n", - "\n", - "%cd /content/OpenFASOC/openfasoc/generators/glayout\n" - ], - "metadata": { - "colab": { - "base_uri": "https://localhost:8080/" - }, - "id": "xMUPna-sakFn", - "outputId": "eb5a0f92-3f32-4664-f938-b1afcf380066" - }, - "execution_count": 5, - "outputs": [ - { - "output_type": "stream", - "name": "stdout", - "text": [ - "env: CONDA_PREFIX=/content/conda-env\n", - "env: PATH=/opt/bin:/usr/local/nvidia/bin:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/tools/node/bin:/tools/google-cloud-sdk/bin:/content/conda-env/bin:/content/conda-env/bin\n", - "/content/OpenFASOC/openfasoc/generators/glayout\n" - ] - } - ] - }, - { - "cell_type": "markdown", - "source": [], - "metadata": { - "id": "sVWvV2Pwg9Ew" - } - }, - { - "cell_type": "markdown", - "source": [ - "# cell_config.py" - ], - "metadata": { - "id": "471iz7QIa3Iw" - } - }, - { - "cell_type": "code", - "source": [ - "from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict\n", - "#from glayout.flow.pdk.gf180_mapped import gf180\n", - "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", - "from glayout.flow.pdk.mappedpdk import MappedPDK\n", - "from glayout.flow.pdk.util.comp_utils import evaluate_bbox\n", - "from gdsfactory import Component\n", - "from gdsfactory.components import rectangle\n", - "from glayout.flow.primitives.fet import pmos\n", - "from glayout.flow.primitives.fet import nmos\n", - "from glayout.flow.routing.straight_route import straight_route\n", - "from glayout.flow.routing.c_route import c_route\n", - "from glayout.flow.routing.L_route import L_route\n", - "from glayout.flow.routing.smart_route import smart_route\n", - "from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized\n", - "from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized\n", - "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port\n", - "\n", - "def add_port_lvs(pdk: MappedPDK, comp: Component, port_list: list[ dict[str, Union[float, str]] ]) -> Component:\n", - "\t'''\n", - " To add external I/O ports onto the cell for LVS\n", - "\n", - "\t@ args:\n", - " \t# pdk: please refer to the glayout library\n", - " \t# comp: please refer to the glayout library\n", - " \t# port_list: tuple[ dict[str, Union[float, str]] ] specifying new port's corresponding pin size, and\n", - "\t\t\t\t\t the name of new port and exiting port managed to align with in the given\n", - "\t\t\t\t\t component, e.g.\n", - "\t\t\t\t\t \t(\n", - "\t\t\t\t\t\t\t{\n", - "\t\t\t\t\t\t\t\t\"new_port\": \"drain_new\",\n", - "\t\t\t\t\t\t\t\t\"new_port_label\": \"drain_new_label\",\n", - "\t\t\t\t\t\t\t\t\"pin_width\": 0.5,\n", - "\t\t\t\t\t\t\t\t\"pin_height\": 0.5,\n", - "\t\t\t\t\t\t\t\t\"ref_port\": \"multiplier_0_drain_E\"\n", - "\t\t\t\t\t\t\t},\n", - "\t\t\t\t\t\t\t{\n", - "\t\t\t\t\t\t\t\t\"new_port\": \"source_new\",\n", - "\t\t\t\t\t\t\t\t\"new_port_label\": \"source_new_label\",\n", - "\t\t\t\t\t\t\t\t\"pin_width\": 1.5,\n", - "\t\t\t\t\t\t\t\t\"pin_height\": 1.5,\n", - "\t\t\t\t\t\t\t\t\"ref_port\": \"multiplier_0_source_E\"\n", - "\t\t\t\t\t\t\t}\n", - "\t\t\t\t\t\t)\n", - "\n", - "\t\t# return: gdsfactory.Component\n", - "\n", - "\t@ Limitations:\n", - "\t\t# So far, only skywater130 process is validated\n", - "\t'''\n", - "\n", - "\t# Add pins and text labels for LVS\n", - "\tpins_labels_info = list() # list that contains all port and component information\n", - "\tprint(f\"port_list: {port_list}\")\n", - "\tfor port in port_list:\n", - "\t\t# To get the layer's data type mapped to the GDS\n", - "\t\tref_port_layer = comp.ports[ port[\"ref_port\"] ].layer[0] # [0]: layer mapping, [1]: pin, drawing, label, net, etc.\n", - "\n", - "\t\t# To create the pin w/ label where the layer[1] is mapped to 16\n", - "\t\tnew_port_pin = rectangle(layer=(ref_port_layer, 16), size=(port[\"pin_width\"], port[\"pin_height\"]),centered=True).copy() # True set rectangle's centroid to the relative (0, 0)\n", - "\t\tnew_port_pin.add_label(text=port[\"new_port_label\"], layer=(ref_port_layer, 5)) # layer[1]=5 mapped to the \"label\" datatype in the GDS\n", - "\n", - "\t\t# To align the new port with the designated port existing in the given component\n", - "\t\talignment = ('c', 'b')\n", - "\t\tcomp_ref = align_comp_to_port(new_port_pin, comp.ports[ port[\"ref_port\"] ], alignment=alignment)\n", - "\t\tcomp.add(comp_ref)\n", - "\n", - "\treturn comp\n", - "\n" - ], - "metadata": { - "id": "fWFYNrTUa_7n" - }, - "execution_count": 6, - "outputs": [] - }, - { - "cell_type": "markdown", - "source": [ - "# inv_lib.py" - ], - "metadata": { - "id": "s0MLpq3xcaO4" - } - }, - { - "cell_type": "code", - "source": [ - "#from glayout.flow.pdk.gf180_mapped import gf180\n", - "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", - "from glayout.flow.pdk.mappedpdk import MappedPDK\n", - "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port\n", - "from gdsfactory import Component\n", - "from gdsfactory.components import rectangle\n", - "from glayout.flow.primitives.fet import pmos\n", - "from glayout.flow.primitives.fet import nmos\n", - "from glayout.flow.routing.straight_route import straight_route\n", - "from glayout.flow.routing.c_route import c_route\n", - "from glayout.flow.routing.L_route import L_route\n", - "from glayout.flow.routing.smart_route import smart_route\n", - "\n", - "def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation):\n", - "\t# Create a top level component\n", - "\ttop_level = Component(component_name)\n", - "\t# To prepare one PMOS and one NMOS for the subsequent inverter cell construction\n", - "\tpfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length)\n", - "\tnfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length)\n", - "\n", - "\t# Instantiation of above PMOS and NMOS under the top level\n", - "\tpfet_ref = prec_ref_center(pfet)\n", - "\tnfet_ref = prec_ref_center(nfet)\n", - "\ttop_level.add(pfet_ref)\n", - "\ttop_level.add(nfet_ref)\n", - "\n", - "\t# Placement (relative move)\n", - "\tmos_spacing = pdk.util_max_metal_seperation()\n", - "\tif(orientation==\"horizontal\"):\n", - "\t\tpfet_ref.rotate(90)\n", - "\t\tnfet_ref.rotate(90)\n", - "\telse:\n", - "\t\tpass\n", - "\tpfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing)\n", - "\n", - "\t# Routing\n", - "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_drain_E\"], nfet_ref.ports[\"multiplier_0_drain_E\"])\n", - "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_gate_W\"], nfet_ref.ports[\"multiplier_0_gate_W\"])\n", - "\n", - "\t# To add the ports\n", - "\ttop_level.add_ports(pfet_ref.get_ports_list(), prefix=\"pmos_\")\n", - "\ttop_level.add_ports(nfet_ref.get_ports_list(), prefix=\"nmos_\")\n", - "\n", - "\treturn top_level" - ], - "metadata": { - "id": "VZoH8lTCcecm" - }, - "execution_count": 7, - "outputs": [] - }, - { - "cell_type": "markdown", - "source": [ - "# transmission_gate.py" - ], - "metadata": { - "id": "ZQOZALxpcgFc" - } - }, - { - "cell_type": "code", - "source": [ - "from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict\n", - "#from glayout.flow.pdk.gf180_mapped import gf180\n", - "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", - "from glayout.flow.pdk.mappedpdk import MappedPDK\n", - "from glayout.flow.pdk.util.comp_utils import evaluate_bbox\n", - "from gdsfactory import Component\n", - "from gdsfactory.components import rectangle\n", - "from glayout.flow.primitives.fet import pmos\n", - "from glayout.flow.primitives.fet import nmos\n", - "from glayout.flow.routing.straight_route import straight_route\n", - "from glayout.flow.routing.c_route import c_route\n", - "from glayout.flow.routing.L_route import L_route\n", - "from glayout.flow.routing.smart_route import smart_route\n", - "from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized\n", - "from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized\n", - "from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port\n", - "\n", - "# My own cell library\n", - "#from inv_lib import reconfig_inv\n", - "#import cell_config as config\n", - "\n", - "def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, nmos_length):\n", - "\t# To prepare all necessary cells to construct a transmission gate, i.e.\n", - "\t# 1) PMOS\n", - "\t# 2) NMOS\n", - "\tpfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length)\n", - "\tnfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length)\n", - "\n", - "\t# Placement and adding ports\n", - "\ttop_level = Component(name=\"TG\")\n", - "\tpfet_ref = prec_ref_center(pfet)\n", - "\tnfet_ref = prec_ref_center(nfet)\n", - "\ttop_level.add(pfet_ref)\n", - "\ttop_level.add(nfet_ref)\n", - "\n", - "\t# Placement\n", - "\tmos_spacing = pdk.util_max_metal_seperation()\n", - "\t#mos_spacing = pdk.get_grule(\"met1\")[\"min_width\"])\n", - "\tif flip_config[\"degree\"] != None:\n", - "\t\tpfet_ref.rotate(flip_config[\"degree\"])\n", - "\t\tnfet_ref.rotate(flip_config[\"degree\"])\n", - "\tpfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing)\n", - "\n", - "\t# Routing\n", - "\t# To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG\n", - "\t# a) PMOS.source connected to NMOS.source\n", - "\t# b) PMOS.drain connected to NMOS.drain\n", - "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_source_E\"], nfet_ref.ports[\"multiplier_0_source_E\"]) # \"in\" of the TG\n", - "\ttop_level << smart_route(pdk, pfet_ref.ports[\"multiplier_0_drain_W\"], nfet_ref.ports[\"multiplier_0_drain_E\"]) # \"out\" of the TG\n", - "\n", - "\ttop_level.add_ports(pfet_ref.get_ports_list(), prefix=\"pmos_\")\n", - "\ttop_level.add_ports(nfet_ref.get_ports_list(), prefix=\"nmos_\")\n", - "\t#top_level.add_port(\n", - "\t#\tname=\"\", center=[0, width / 2], width=width, orientation=180, layer=layer\n", - "\t#)\n", - "\n", - "\t# Add pins and text labels for LVS\n", - "\tpins_labels_info = list() # list that contains all port and component information\n", - "\t# To define the layers\n", - "\tgds_met1 = pdk.get_glayer(\"met2\")[0]\n", - "\tgds_met2 = gds_met1+1\n", - "\tgds_met3 = gds_met2+1\n", - "\tgds_met4 = gds_met3+1\n", - "\tgds_met5 = gds_met4+1\n", - "\t# To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port\n", - "\ttg_din_portLayer = top_level.ports[\"pmos_multiplier_0_source_W\"].layer[0]\n", - "\ttg_dout_portLayer = top_level.ports[\"pmos_multiplier_0_drain_E\"].layer[0]\n", - "\t# To create the pins w/ labels and append to info list\n", - "\ttg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0)\n", - "\ttg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy()\n", - "\ttg_din_pin.add_label(text=\"Vin\", layer=(tg_din_portLayer, 5))\n", - "\ttg_dout_pin.add_label(text=\"Vout\", layer=(tg_dout_portLayer, 5))\n", - "\tpins_labels_info.append((tg_din_pin, top_level.ports[\"pmos_multiplier_0_source_W\"], None))\n", - "\tpins_labels_info.append((tg_dout_pin, top_level.ports[\"pmos_multiplier_0_drain_E\"], None))\n", - "\n", - "\t#print(top_level.ports[\"pmos_multiplier_0_source_W\"].name)\n", - "\t#top_level.pprint_ports()\n", - "\n", - "\t# Move everythin to position\n", - "\tfor comp, prt, alignment in pins_labels_info:\n", - "\t\talignment = ('c', 'b') if alignment is None else alignment\n", - "\t\tcompref = align_comp_to_port(comp, prt, alignment=alignment)\n", - "\t\t#top_level.add(compref)\n", - "\n", - "\treturn top_level #top_level.flatten()\n", - "\n", - "def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length):\n", - "\t# To prepare all necessary cells to construct a transmission gate, i.e.\n", - "\t# 1) transmission gate\n", - "\t# 2) Inverter\n", - "\ttg = naive_tg_cell(pdk=pdk, flip_config={\"degree\": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length)\n", - "\tinv = reconfig_inv(pdk=pdk, component_name=\"gate_ctrl_inv\", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation=\"horizontal\")\n", - "\n", - "\t# Instantiation of the essential cells\n", - "\ttop_level = Component(name=\"tg_with_inv\")\n", - "\ttg_ref = prec_ref_center(tg)\n", - "\tinv_ref = prec_ref_center(inv)\n", - "\ttop_level.add(tg_ref)\n", - "\ttop_level.add(inv_ref)\n", - "\n", - "\t# Placement\n", - "\tmos_spacing = pdk.util_max_metal_seperation()\n", - "\tnwell_min_spacing = pdk.get_grule(\"nwell\")[\"min_separation\"]\n", - "\tinv_cell_width = inv_ref.xsize # or = evaluate_bbox(inv)[0]\n", - "\ttg_ref.movex(inv_cell_width + nwell_min_spacing)\n", - "\n", - "\t# Routing\n", - "\t# 1) PMOS of the TG is switched on/off by the inverter's output\n", - "\t# 2) NMOS of the TG is switched on/off by an external control signal connected to inverter's input port as well\n", - "\ttop_level << smart_route(pdk, inv_ref.ports[\"pmos_multiplier_0_drain_E\"], tg_ref.ports[\"pmos_multiplier_0_gate_W\"])\n", - "\ttop_level << smart_route(pdk, inv_ref.ports[\"nmos_multiplier_0_gate_S\"], tg_ref.ports[\"nmos_multiplier_0_gate_S\"])\n", - "\n", - "\t# Adding the ports\n", - "\ttop_level.add_ports(tg_ref.get_ports_list(), prefix=\"tg_\")\n", - "\ttop_level.add_ports(inv_ref.get_ports_list(), prefix=\"inv_\")\n", - "\n", - "\treturn top_level\n" - ], - "metadata": { - "id": "f9zRFCm6cl4N" - }, - "execution_count": 13, - "outputs": [] - }, - { - "cell_type": "markdown", - "source": [ - "# eval.py" - ], - "metadata": { - "id": "VLrreUmkcrg_" - } - }, - { - "cell_type": "code", - "source": [ - "#from glayout.flow.pdk.gf180_mapped import gf180\n", - "from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130\n", - "import gdstk\n", - "import svgutils.transform as sg\n", - "import IPython.display\n", - "from IPython.display import clear_output\n", - "\n", - "def display_gds(gds_file, image_filename: str, scale = 3):\n", - " # Generate an SVG image\n", - " top_level_cell = gdstk.read_gds(gds_file).top_level()[0]\n", - " top_level_cell.write_svg(image_filename)\n", - " # Scale the image for displaying\n", - " fig = sg.fromfile(image_filename)\n", - " fig.set_size((str(float(fig.width) * scale), str(float(fig.height) * scale)))\n", - " fig.save(image_filename)\n", - "\n", - " # Display the image\n", - " IPython.display.display(IPython.display.SVG(image_filename))\n", - "\n", - "def main():\n", - " tg_inst = tg_with_inv(pdk=sky130, pmos_width=1, pmos_length=0.15, nmos_width=1, nmos_length=0.15)\n", - " tg_inst = add_port_lvs(\n", - " pdk=sky130,\n", - " comp=tg_inst,\n", - " port_list=[\n", - " {\n", - " \"new_port\": \"tg_ctrl\",\n", - " \"new_port_label\": \"ctrl\",\n", - " \"pin_width\": tg_inst.ports[\"inv_nmos_multiplier_0_gate_S\"].width,\n", - " \"pin_height\": tg_inst.ports[\"inv_nmos_multiplier_0_gate_S\"].width,\n", - " \"ref_port\": \"inv_nmos_multiplier_0_gate_S\"\n", - " },\n", - " {\n", - " \"new_port\": \"tg_din\",\n", - " \"new_port_label\": \"din\",\n", - " \"pin_width\": 0.3,\n", - " \"pin_height\": 0.3,\n", - " \"ref_port\": \"tg_pmos_multiplier_0_source_W\"\n", - " },\n", - " {\n", - " \"new_port\": \"tg_dout\",\n", - " \"new_port_label\": \"dout\",\n", - " \"pin_width\": 0.3,\n", - " \"pin_height\": 0.3,\n", - " \"ref_port\": \"tg_nmos_multiplier_0_drain_N\"\n", - " }\n", - "\t ]\n", - "\t)\n", - " #tg_inst.flatten()\n", - " #tg_inst.show()\n", - " tg_inst.write_gds(\"tg_with_inv.gds\")\n", - " display_gds(gds_file=\"tg_with_inv.gds\", image_filename=\"tg_with_inv.svg\", scale=5)\n", - "\n", - "if __name__ == \"__main__\":\n", - " main()" - ], - "metadata": { - "id": "K3JfrIUWctcI", - "outputId": "b69ca1d4-6318-4a8c-b46c-47f42343f65d", - "colab": { - "base_uri": "https://localhost:8080/", - "height": 1000 - } - }, - "execution_count": 25, - "outputs": [ - { - "output_type": "stream", - "name": "stderr", - "text": [ - ":51: UserWarning: Unnamed cells, 7 in 'tg_with_inv$6'\n", - " tg_inst.write_gds(\"tg_with_inv.gds\")\n", - "\u001b[32m2024-11-14 02:40:11.852\u001b[0m | \u001b[1mINFO \u001b[0m | \u001b[36mgdsfactory.component\u001b[0m:\u001b[36m_write_library\u001b[0m:\u001b[36m1851\u001b[0m - \u001b[1mWrote to 'tg_with_inv.gds'\u001b[0m\n" - ] - }, - { - "output_type": "stream", - "name": "stdout", - "text": [ - "port_list: [{'new_port': 'tg_ctrl', 'new_port_label': 'ctrl', 'pin_width': 0.33, 'pin_height': 0.33, 'ref_port': 'inv_nmos_multiplier_0_gate_S'}, {'new_port': 'tg_din', 'new_port_label': 'din', 'pin_width': 0.3, 'pin_height': 0.3, 'ref_port': 'tg_pmos_multiplier_0_source_W'}, {'new_port': 'tg_dout', 'new_port_label': 'dout', 'pin_width': 0.3, 'pin_height': 0.3, 'ref_port': 'tg_nmos_multiplier_0_drain_N'}]\n" - ] - }, - { - "output_type": "display_data", - "data": { - "text/plain": [ - "" - ], - "image/svg+xml": "\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\ndout\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nctrl\n\n\n\ndin\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n" - }, - "metadata": {} - } - ] - }, - { - "cell_type": "markdown", - "source": [ - "\n", - "\n", - "---\n", - "\n", - "\n", - "# トランスミッションゲートを表示させます。\n" - ], - "metadata": { - "id": "VTXMiC1nbFTu" - } - }, - { - "cell_type": "markdown", - "source": [ - "Geminiによると・・・\n", - "生成されたGDSファイルに名前のないセルがあるという警告が表示されているようです。この警告はgdsfactoryから発生し、「TG$2」セル内に明示的な名前が割り当てられていないコンポーネントがあることを示しています。\n", - "\n", - "すぐに問題が発生するわけではありませんが、整理とデバッグを改善するために、すべてのコンポーネントに名前を付けることをお勧めします。コンポーネントを作成するときに name 引数を指定することで、コンポーネントに名前を付けることができます。\n", - "\n", - "たとえば、transmissionGate_cell 関数では、pfet および nfet インスタンスに名前を付けることができます。\n", - "\n", - "\n", - "pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=width, length=length, name=\"pmos_instance\")\n", - "nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=width, length=length, name=\"nmos_instance\")\n", - "Use code with caution\n", - "これにより、GDSファイルがより読みやすくなり、扱いやすくなります。\n", - "\n", - "・・・らしいです" - ], - "metadata": { - "id": "xyQej3g8pIMq" - } - } - ] -} \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 5757be092..f7e2fbc48 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -16,94 +16,19 @@ from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port # My own cell library -from inv_lib import reconfig_inv -import cell_config as config - -''' -def naive_tg_cell(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): - # To prepare all necessary cells to construct a transmission gate, i.e. - # 1) PMOS - # 2) NMOS - pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) - - # Placement and adding ports - top_level = Component(name="TG") - pfet_ref = prec_ref_center(pfet) - nfet_ref = prec_ref_center(nfet) - top_level.add(pfet_ref) - top_level.add(nfet_ref) - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - - # Placement - mos_spacing = pdk.util_max_metal_seperation() - #mos_spacing = pdk.get_grule("met1")["min_width"]) - pfet_ref.rotate(90) - nfet_ref.rotate(90) - pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - - # Routing - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_W"]) # "out" of the TG - - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - # To define the layers - gds_met1 = pdk.get_glayer("met2")[0] - gds_met2 = gds_met1+1 - gds_met3 = gds_met2+1 - gds_met4 = gds_met3+1 - gds_met5 = gds_met4+1 - # To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port - tg_din_portLayer = top_level.ports["pmos_multiplier_0_source_W"].layer[0] - tg_dout_portLayer = top_level.ports["pmos_multiplier_0_drain_E"].layer[0] - # To create the pins w/ labels and append to info list - tg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) - tg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy() - tg_din_pin.add_label(text="Vin", layer=(tg_din_portLayer, 5)) - tg_dout_pin.add_label(text="Vout", layer=(tg_dout_portLayer, 5)) - pins_labels_info.append((tg_din_pin, top_level.ports["pmos_multiplier_0_source_W"], None)) - pins_labels_info.append((tg_dout_pin, top_level.ports["pmos_multiplier_0_drain_E"], None)) - - #print(top_level.ports["pmos_multiplier_0_source_W"].name) - #top_level.pprint_ports() - - # Move everythin to position - for comp, prt, alignment in pins_labels_info: - alignment = ('c', 'b') if alignment is None else alignment - compref = align_comp_to_port(comp, prt, alignment=alignment) - #top_level.add(compref) - - return top_level #top_level.flatten() - -def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): - # To prepare all necessary cells to construct a transmission gate, i.e. - # 1) transmission gate - # 2) Inverter - tg = naive_tg_cell(pdk=pdk, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) - inv = reconfig_inv(pdk=pdk, component_name="gate_ctrl_inv", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="horizontal") - - # Placement and adding ports - top_level = Component(name="tg_with_inv") - tg_ref = prec_ref_center(tg) - inv_ref = prec_ref_center(inv) - top_level.add(tg_ref) - top_level.add(inv_ref) - top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") - top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") - - # Placement - mos_spacing = pdk.util_max_metal_seperation() - tg_ref.movex(evaluate_bbox(inv)[0] + mos_spacing) - - # Routing - #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_source_W"], nfet_ref.ports["multiplier_0_drain_W"]) # "in" of the TG - #top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"]) # "out" of the TG - - return top_level #top_level.flatten() -''' -def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, nmos_length): +from reconfig_inv import reconfig_inv + +#@cell +def tg_cell( + pdk: MappedPDK, + flip_config: + dict[str, Union[int, str]], + pmos_width, + pmos_length, + nmos_width, + nmos_length, + **kwargs +) -> Component: # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS @@ -111,7 +36,7 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) # Placement and adding ports - top_level = Component(name="TG") + top_level = Component(name="tg_1b") pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) @@ -119,7 +44,6 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ # Placement mos_spacing = pdk.util_max_metal_seperation() - #mos_spacing = pdk.get_grule("met1")["min_width"]) if flip_config["degree"] != None: pfet_ref.rotate(flip_config["degree"]) nfet_ref.rotate(flip_config["degree"]) @@ -130,49 +54,19 @@ def naive_tg_cell(pdk: MappedPDK, flip_config: dict[str, Union[int, str]], pmos_ # a) PMOS.source connected to NMOS.source # b) PMOS.drain connected to NMOS.drain top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # "in" of the TG - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met1") # "out" of the TG + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met3") # "out" of the TG top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - #top_level.add_port( - # name="", center=[0, width / 2], width=width, orientation=180, layer=layer - #) - - # Add pins and text labels for LVS - pins_labels_info = list() # list that contains all port and component information - # To define the layers - gds_met1 = pdk.get_glayer("met2")[0] - gds_met2 = gds_met1+1 - gds_met3 = gds_met2+1 - gds_met4 = gds_met3+1 - gds_met5 = gds_met4+1 - # To get the respective layers of the underlying TG's PMOS.source port PMOS.drain port - tg_din_portLayer = top_level.ports["pmos_multiplier_0_source_W"].layer[0] - tg_dout_portLayer = top_level.ports["pmos_multiplier_0_drain_E"].layer[0] - # To create the pins w/ labels and append to info list - tg_din_pin = rectangle(layer=(tg_din_portLayer, 16), size=(1, 1),centered=True).copy() # True set rectangle's centroid to the relative (0, 0) - tg_dout_pin = rectangle(layer=(tg_dout_portLayer, 16), size=(1, 1), centered=True).copy() - tg_din_pin.add_label(text="Vin", layer=(tg_din_portLayer, 5)) - tg_dout_pin.add_label(text="Vout", layer=(tg_dout_portLayer, 5)) - pins_labels_info.append((tg_din_pin, top_level.ports["pmos_multiplier_0_source_W"], None)) - pins_labels_info.append((tg_dout_pin, top_level.ports["pmos_multiplier_0_drain_E"], None)) - - #print(top_level.ports["pmos_multiplier_0_source_W"].name) - #top_level.pprint_ports() - # Move everythin to position - for comp, prt, alignment in pins_labels_info: - alignment = ('c', 'b') if alignment is None else alignment - compref = align_comp_to_port(comp, prt, alignment=alignment) - #top_level.add(compref) - - return top_level #top_level.flatten() + return top_level -def tg_with_inv(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): +#@cell +def tg_with_ctrl(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): # To prepare all necessary cells to construct a transmission gate, i.e. # 1) transmission gate # 2) Inverter - tg = naive_tg_cell(pdk=pdk, flip_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) + tg = tg_cell(pdk=pdk, flip_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) inv = reconfig_inv(pdk=pdk, component_name="gate_ctrl_inv", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="horizontal") # Instantiation of the essential cells From cc695acec0735a37bf259fef6814026dd3747021 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Mon, 18 Nov 2024 15:34:35 +0000 Subject: [PATCH 16/21] Team: Salty Chip, Chipathon2024 Modify the PCell of the transmission gate composed of a basic TG cell and INV cell. The Magis DRC per basic cell and that of the top-level block have been performed w/o error --- .../transmission_gate_saltychip/eval.py | 71 +++++++++-- .../gds/gate_ctrl_inv.gds | Bin 0 -> 33536 bytes .../transmission_gate_saltychip/gds/tg.gds | Bin 0 -> 33566 bytes .../gds/tg_with_ctrl.gds | Bin 0 -> 67638 bytes .../gds/tg_with_inv.gds | Bin 61684 -> 0 bytes .../reconfig_inv.py | 67 ++++++----- .../transmission_gate.py | 111 ++++++++++++++++-- 7 files changed, 203 insertions(+), 46 deletions(-) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/gate_ctrl_inv.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_ctrl.gds delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_inv.gds diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 5720c73ae..c06f44f8f 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -1,29 +1,82 @@ -import transmission_gate as tg +import subprocess #from glayout.flow.pdk.gf180_mapped import gf180 from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 import reconfig_inv as reconfig_inv +import transmission_gate as tg TARGET_PDK = sky130 +PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) +GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" -def main(): +pmos_width = 1 +pmos_length = 0.15 +nmos_width = 1 +nmos_length = 0.15 + +def basic_tg_eval(): + tg_dut = tg.tg_cell( + pdk=TARGET_PDK, + component_name="tg", + flip_config={"degree": 270}, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length + ) + + tg_dut.show() + tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") + magic_drc_result = sky130.drc_magic( + layout=tg_dut, + design_name=tg_dut.name#, + #output_file=f"{absolute_path}/{tg.name}.rpt" + ) + print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) + print("--------------------------------------") + +def gate_ctrl_inv_eval(): gate_ctrl_inv = reconfig_inv.reconfig_inv( pdk=TARGET_PDK, component_name="gate_ctrl_inv", - pmos_width=1, - pmos_length=0.15, - nmos_width=1, - nmos_length=0.15, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, orientation="horizontal" ) gate_ctrl_inv.show() - gate_ctrl_inv.write_gds("/home/tsengs0/gate_ctrl_inv.gds") - + gate_ctrl_inv.write_gds(f"{GDS_DIR}/{gate_ctrl_inv.name}.gds") magic_drc_result = sky130.drc_magic( layout=gate_ctrl_inv, design_name=gate_ctrl_inv.name#, #output_file=f"{absolute_path}/{gate_ctrl_inv.name}.rpt" ) - print("Magic DRC result: \n", magic_drc_result) + print(f"Magic DRC result ({gate_ctrl_inv.name}): \n", magic_drc_result) + print("--------------------------------------") + +def tg_with_ctrl_eval(): + tg_dut = tg.tg_with_ctrl( + pdk=TARGET_PDK, + component_name="tg_with_ctrl", + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length + ) + tg_dut.show() + tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") + magic_drc_result = sky130.drc_magic( + layout=tg_dut, + design_name=tg_dut.name#, + #output_file=f"{absolute_path}/{tg_dut.name}.rpt" + ) + print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) + print("--------------------------------------") + +def main(): + basic_tg_eval() + gate_ctrl_inv_eval() + tg_with_ctrl_eval() if __name__ == "__main__": main() \ No newline at end of file diff --git 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z=hIBvTfcuHPW^@BRN}L|)|hMBKGX5b*FUe|ud!QvoTff&+P*2Qf9QXsnSxnAu3e>D z^;kjaCwrHEI##mZk7f#H-BuKoehUww-_cn=QRfcV6_l>^^49Th7BlUN{g-j#N%C>c znfNsP74J>kTlZi5cjCV>^I3R+_onTw`!D{x@YgX$)cC!xpzW>w5C0wbGtMPy+32E)(n*wV_ZPIiOTXdkFUCLe zT|z$TBuY1(bD6eB{fhG^jxRb_qs~N++otWY{-9sFS4y5l`oG3$83xNF4#`xRjRA_a|oa)GGeEt~!m$UEQa_YFI7S>0$x2Bne{*}`U z*DPIp;j&drf`1x8j_RJX*!6w3?wO4FCMyLNtdw{LQ?;4s%JXPCG?9M%RZuNfv DLAm1N diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py index 93ccdc341..8c9a255ee 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py @@ -12,7 +12,17 @@ from glayout.flow.routing.smart_route import smart_route #@cell -def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_width, nmos_length, orientation): +def reconfig_inv( + pdk: MappedPDK, + component_name, + pmos_width, + pmos_length, + nmos_width, + nmos_length, + orientation, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: # Create a top level component top_level = Component(component_name) # To prepare one PMOS and one NMOS for the subsequent inverter cell construction @@ -44,33 +54,34 @@ def reconfig_inv(pdk: MappedPDK, component_name, pmos_width, pmos_length, nmos_w top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - # Add pins w/ labels for LVS - top_level.unlock() - pin_info = list() # list that contains all port and component information - met1_pin=(pdk.get_glayer("met1")[0], 20) - met1_label=(pdk.get_glayer("met1")[0], 5) - port_size = (0.24, 0.24) - # --- Port: A, i.e. input of the inverter - A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_E"), None)) - # --- Port: Y, i.e. output of the inverver - Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) - # --- Port: VDD - VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VDD_pin.add_label(text="VDD", layer=met1_label) - pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) - # --- Port: VSS - VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VSS_pin.add_label(text="VSS", layer=met1_label) - pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) + if add_pin == True: + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the inverter + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_E"), None)) + # --- Port: Y, i.e. output of the inverver + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) + # --- Port: VDD + VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VDD_pin.add_label(text="VDD", layer=met1_label) + pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) + # --- Port: VSS + VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VSS_pin.add_label(text="VSS", layer=met1_label) + pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) - # Move everythin to position - for comp, prt, alignment in pin_info: - alignment = ('c', 'b') if alignment is None else alignment - comp_ref = align_comp_to_port(comp, prt, alignment=alignment) - top_level.add(comp_ref) + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) return top_level diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index f7e2fbc48..d77a4a147 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -21,22 +21,24 @@ #@cell def tg_cell( pdk: MappedPDK, + component_name: str, flip_config: dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, nmos_length, + add_pin: bool = True, # For LVS **kwargs ) -> Component: # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) + pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) # Placement and adding ports - top_level = Component(name="tg_1b") + top_level = Component(name=component_name) pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) @@ -54,23 +56,81 @@ def tg_cell( # a) PMOS.source connected to NMOS.source # b) PMOS.drain connected to NMOS.drain top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # "in" of the TG - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_W"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met3") # "out" of the TG + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met2") # "out" of the TG + # Add the ports aligned with the basic PMOS and NMOS top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + if add_pin == True: + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the transmission gate + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"nmos_drain_S"), None)) + # --- Port: Y, i.e. output of the transmission gate + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"pmos_drain_S"), None)) + # --- Port: C, i.e. gate control to the NMOS + C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + C_pin.add_label(text="C", layer=met1_label) + pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_N"), None)) + # --- Port: CBAR, i.e. gate control to the PMOS + CBAR_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + CBAR_pin.add_label(text="CBAR", layer=met1_label) + pin_info.append((CBAR_pin, top_level.ports.get(f"pmos_gate_N"), None)) + + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) + return top_level #@cell -def tg_with_ctrl(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_length): +def tg_with_ctrl( + pdk: MappedPDK, + component_name: str, + pmos_width, + pmos_length, + nmos_width, + nmos_length, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: # To prepare all necessary cells to construct a transmission gate, i.e. # 1) transmission gate # 2) Inverter - tg = tg_cell(pdk=pdk, flip_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length) - inv = reconfig_inv(pdk=pdk, component_name="gate_ctrl_inv", pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, orientation="horizontal") + tg = tg_cell( + pdk=pdk, + component_name="tg", + flip_config={"degree": 270}, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + add_pin=False + ) + inv = reconfig_inv( + pdk=pdk, + component_name="gate_ctrl_inv", + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + orientation="horizontal", + add_pin=False + ) # Instantiation of the essential cells - top_level = Component(name="tg_with_inv") + top_level = Component(name=component_name) tg_ref = prec_ref_center(tg) inv_ref = prec_ref_center(inv) top_level.add(tg_ref) @@ -91,6 +151,39 @@ def tg_with_ctrl(pdk: MappedPDK, pmos_width, pmos_length, nmos_width, nmos_lengt # Adding the ports top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") + + if add_pin == True: + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the transmission gate + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"tg_nmos_drain_S"), None)) + # --- Port: Y, i.e. output of the transmission gate + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"tg_pmos_drain_S"), None)) + # --- Port: C, i.e. gate control to the NMOS + C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + C_pin.add_label(text="C", layer=met1_label) + pin_info.append((C_pin, top_level.ports.get(f"inv_nmos_gate_N"), None)) + # --- Port: VDD + VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VDD_pin.add_label(text="VDD", layer=met1_label) + pin_info.append((VDD_pin, top_level.ports.get(f"inv_pmos_drain_E"), None)) + # --- Port: VSS + VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VSS_pin.add_label(text="VSS", layer=met1_label) + pin_info.append((VSS_pin, top_level.ports.get(f"inv_nmos_source_W"), ('r', 't'))) - return top_level + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) + return top_level From 84b94b38f71bc7e0323f0c6201df421fa8af8518 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Wed, 20 Nov 2024 15:33:43 +0000 Subject: [PATCH 17/21] Team: Salty Chip, Chipathon2024 Modify the layout of both transmission gate and inverter in a interdititized fashion so as to contruct a CDAC switch Status: W.I.P. : --- .../transmission_gate_saltychip/eval.py | 14 +- .../reconfig_inv.py | 117 +++++++++++++++- .../transmission_gate.py | 131 +++++++++++++++++- 3 files changed, 247 insertions(+), 15 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index c06f44f8f..be09ed99e 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -8,20 +8,20 @@ PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" -pmos_width = 1 +pmos_width = 1.5 pmos_length = 0.15 -nmos_width = 1 +nmos_width = 1.5 nmos_length = 0.15 def basic_tg_eval(): - tg_dut = tg.tg_cell( + tg_dut = tg.reconfig_tg( pdk=TARGET_PDK, component_name="tg", - flip_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, - nmos_length=nmos_length + nmos_length=nmos_length, + add_pin=True ) tg_dut.show() @@ -42,7 +42,7 @@ def gate_ctrl_inv_eval(): pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, - orientation="horizontal" + add_pin=True ) gate_ctrl_inv.show() gate_ctrl_inv.write_gds(f"{GDS_DIR}/{gate_ctrl_inv.name}.gds") @@ -76,7 +76,7 @@ def tg_with_ctrl_eval(): def main(): basic_tg_eval() gate_ctrl_inv_eval() - tg_with_ctrl_eval() + #tg_with_ctrl_eval() if __name__ == "__main__": main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py index 8c9a255ee..5d29cb6be 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py @@ -1,3 +1,4 @@ +from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict #from glayout.flow.pdk.gf180_mapped import gf180 from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 from glayout.flow.pdk.mappedpdk import MappedPDK @@ -11,8 +12,10 @@ from glayout.flow.routing.L_route import L_route from glayout.flow.routing.smart_route import smart_route +LONG_CHANNEL_WIDTH = 1.5 + #@cell -def reconfig_inv( +def short_channel_inv( pdk: MappedPDK, component_name, pmos_width, @@ -85,3 +88,115 @@ def reconfig_inv( top_level.add(comp_ref) return top_level + +#@cell +def long_channel_inv( + pdk: MappedPDK, + component_name, + pmos_width, + pmos_length, + nmos_width, + nmos_length, + orientation_config: dict[str, Union[int, str]], + add_pin: bool = True, # For LVS + **kwargs +) -> Component: + # Create a top level component + top_level = Component(component_name) + # To prepare one PMOS and one NMOS for the subsequent inverter cell construction + pfet = pmos(pdk=pdk, gate_rmult=1, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=1, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + pfet.name="pmos" + nfet.name="nmos" + + # Instantiation of above PMOS and NMOS under the top level + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) + top_level.add(pfet_ref) + top_level.add(nfet_ref) + + # Placement (relative move) + mos_spacing = pdk.util_max_metal_seperation(metal_levels=("met1", "met2", "met3", "met4", "met5")) + if orientation_config["pmos_degree"] != None: + pfet_ref.rotate(orientation_config["pmos_degree"]) + if orientation_config["nmos_degree"] != None: + nfet_ref.rotate(orientation_config["nmos_degree"]) + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + # Routing + top_level << c_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_W"], cglayer="met3") # connected by li1 + top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_gate_S"], nfet_ref.ports["multiplier_0_gate_S"]) # connected by li1 + + # To add the ports + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + + if add_pin == True: + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the inverter + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_S"), None)) + # --- Port: Y, i.e. output of the inverver + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) + # --- Port: VDD + VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VDD_pin.add_label(text="VDD", layer=met1_label) + pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) + # --- Port: VSS + VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + VSS_pin.add_label(text="VSS", layer=met1_label) + pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) + + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) + + return top_level + +#@cell +def reconfig_inv( + pdk, + component_name, + pmos_width, + pmos_length, + nmos_width, + nmos_length, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: + if pmos_width != nmos_width: + raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") + elif pmos_width >= LONG_CHANNEL_WIDTH: # Long-channel PMOS and NMOS + inv = long_channel_inv( + pdk=pdk, + component_name=component_name, + orientation_config={"pmos_degree":0, "nmos_degree":180}, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + add_pin=True + ) + else: # Short-channel PMOS and NMOS + inv = short_channel_inv( + pdk=pdk, + component_name=component_name, + orientation="horizontal", + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + add_pin=True + ) + + return inv \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index d77a4a147..41cb97a3a 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -17,12 +17,14 @@ # My own cell library from reconfig_inv import reconfig_inv - + +LONG_CHANNEL_WIDTH = 1.5 + #@cell -def tg_cell( +def short_channel_tg( pdk: MappedPDK, component_name: str, - flip_config: + orientation_config: dict[str, Union[int, str]], pmos_width, pmos_length, @@ -46,9 +48,9 @@ def tg_cell( # Placement mos_spacing = pdk.util_max_metal_seperation() - if flip_config["degree"] != None: - pfet_ref.rotate(flip_config["degree"]) - nfet_ref.rotate(flip_config["degree"]) + if orientation_config["degree"] != None: + pfet_ref.rotate(orientation_config["degree"]) + nfet_ref.rotate(orientation_config["degree"]) pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) # Routing @@ -94,6 +96,83 @@ def tg_cell( return top_level +#@cell +def long_channel_tg( + pdk: MappedPDK, + component_name: str, + orientation_config: + dict[str, Union[int, str]], + pmos_width, + pmos_length, + nmos_width, + nmos_length, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: + # To prepare all necessary cells to construct a transmission gate, i.e. + # 1) PMOS + # 2) NMOS + pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + + # Placement and adding ports + top_level = Component(name=component_name) + pfet_ref = prec_ref_center(pfet) + nfet_ref = prec_ref_center(nfet) + top_level.add(pfet_ref) + top_level.add(nfet_ref) + + # Placement + mos_spacing = pdk.util_max_metal_seperation() + if orientation_config["pmos_degree"] != None: + pfet_ref.rotate(orientation_config["pmos_degree"]) + if orientation_config["nmos_degree"] != None: + nfet_ref.rotate(orientation_config["nmos_degree"]) + pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + # Routing + # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG + # a) PMOS.source connected to NMOS.source + # b) PMOS.drain connected to NMOS.drain + top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_S"], nfet_ref.ports["multiplier_0_drain_S"], glayer1="met3") # "in" of the TG + top_level << c_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_W"], cglayer="met3") # "out" of the TG + + # Add the ports aligned with the basic PMOS and NMOS + top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") + top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + + if add_pin == True: + # Add pins w/ labels for LVS + top_level.unlock() + pin_info = list() # list that contains all port and component information + met1_pin=(pdk.get_glayer("met1")[0], 20) + met1_label=(pdk.get_glayer("met1")[0], 5) + port_size = (0.24, 0.24) + # --- Port: A, i.e. input of the transmission gate + A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + A_pin.add_label(text="A", layer=met1_label) + pin_info.append((A_pin, top_level.ports.get(f"nmos_drain_S"), None)) + # --- Port: Y, i.e. output of the transmission gate + Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + Y_pin.add_label(text="Y", layer=met1_label) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_N"), None)) + # --- Port: C, i.e. gate control to the NMOS + C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + C_pin.add_label(text="C", layer=met1_label) + pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_N"), None)) + # --- Port: CBAR, i.e. gate control to the PMOS + CBAR_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() + CBAR_pin.add_label(text="CBAR", layer=met1_label) + pin_info.append((CBAR_pin, top_level.ports.get(f"pmos_gate_N"), None)) + + # Move everythin to position + for comp, prt, alignment in pin_info: + alignment = ('c', 'b') if alignment is None else alignment + comp_ref = align_comp_to_port(comp, prt, alignment=alignment) + top_level.add(comp_ref) + + return top_level + #@cell def tg_with_ctrl( pdk: MappedPDK, @@ -111,7 +190,7 @@ def tg_with_ctrl( tg = tg_cell( pdk=pdk, component_name="tg", - flip_config={"degree": 270}, + orientation_config={"degree": 270}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, @@ -187,3 +266,41 @@ def tg_with_ctrl( top_level.add(comp_ref) return top_level + +#@cell +def reconfig_tg( + pdk: MappedPDK, + component_name, + pmos_width, + pmos_length, + nmos_width, + nmos_length, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: + if pmos_width != nmos_width: + raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") + elif pmos_width >= LONG_CHANNEL_WIDTH: # Long-channel PMOS and NMOS + tg = long_channel_tg( + pdk=pdk, + component_name=component_name, + orientation_config={"nmos_degree": 180, "pmos_degree": 0}, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + add_pin=True + ) + else: # Short-channel PMOS and NMOS + tg = short_channel_tg( + pdk=pdk, + component_name=component_name, + orientation_config={"degree": 270}, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + add_pin=True + ) + + return tg \ No newline at end of file From 351cbdfe0dff245d07934d4dab28f580491af739 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Thu, 21 Nov 2024 18:21:24 +0000 Subject: [PATCH 18/21] Team: Salty Chip, Chipathon2024 Complete the first prototyping layout of the transmission gate in an interdigitized fashion #Status:Magic DRC passed, netlist generation for the LVS is still working in progress #PCell status: W.I.P. #User manual about the PCell: W.I.P. #Completion date (expected): 23.Nov.2024 --- .../transmission_gate_saltychip/comp_dc.py | 4 + .../transmission_gate_saltychip/eval.py | 12 +- .../gds/gate_ctrl_inv.gds | Bin 33536 -> 28126 bytes .../transmission_gate_saltychip/gds/tg.gds | Bin 33566 -> 0 bytes .../gds/tg_ver1.gds | Bin 0 -> 66472 bytes .../gds/tg_ver2.gds | Bin 0 -> 43572 bytes .../gds/tg_with_ctrl.gds | Bin 67638 -> 67638 bytes .../reconfig_inv.py | 4 +- .../transmission_gate.py | 116 +++++++++++++++--- 9 files changed, 112 insertions(+), 24 deletions(-) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_ver1.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_ver2.gds diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py new file mode 100644 index 000000000..2cc659058 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py @@ -0,0 +1,4 @@ +def initialise(): + global inv_channel_width_base, tg_channel_width_base + inv_channel_width_base = 3.0 + tg_channel_width_base = 3.0 \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index be09ed99e..69d63a3ab 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -3,14 +3,15 @@ from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 import reconfig_inv as reconfig_inv import transmission_gate as tg +import comp_dc TARGET_PDK = sky130 PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" -pmos_width = 1.5 +pmos_width = 6.0*2 pmos_length = 0.15 -nmos_width = 1.5 +nmos_width = 6.0*2 nmos_length = 0.15 def basic_tg_eval(): @@ -26,6 +27,7 @@ def basic_tg_eval(): tg_dut.show() tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") + ''' magic_drc_result = sky130.drc_magic( layout=tg_dut, design_name=tg_dut.name#, @@ -33,6 +35,7 @@ def basic_tg_eval(): ) print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) print("--------------------------------------") + ''' def gate_ctrl_inv_eval(): gate_ctrl_inv = reconfig_inv.reconfig_inv( @@ -75,8 +78,9 @@ def tg_with_ctrl_eval(): def main(): basic_tg_eval() - gate_ctrl_inv_eval() + #gate_ctrl_inv_eval() #tg_with_ctrl_eval() if __name__ == "__main__": - main() \ No newline at end of file + comp_dc.initialise() + main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/gate_ctrl_inv.gds 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if pmos_width != nmos_width: raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif pmos_width >= LONG_CHANNEL_WIDTH: # Long-channel PMOS and NMOS + elif pmos_width >= comp_dc.inv_channel_width_base: # Long-channel PMOS and NMOS inv = long_channel_inv( pdk=pdk, component_name=component_name, diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index 41cb97a3a..58a87c3be 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -1,8 +1,10 @@ from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict +import math #from glayout.flow.pdk.gf180_mapped import gf180 from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 from glayout.flow.pdk.mappedpdk import MappedPDK from glayout.flow.pdk.util.comp_utils import evaluate_bbox +from glayout.flow.pdk.util.port_utils import set_port_orientation, rename_ports_by_orientation, create_private_ports from gdsfactory import Component from gdsfactory.components import rectangle from glayout.flow.primitives.fet import pmos @@ -11,14 +13,14 @@ from glayout.flow.routing.c_route import c_route from glayout.flow.routing.L_route import L_route from glayout.flow.routing.smart_route import smart_route -from glayout.flow.placement.two_transistor_interdigitized import two_nfet_interdigitized -from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized +from glayout.flow.placement.two_transistor_interdigitized import two_pfet_interdigitized, two_nfet_interdigitized, two_transistor_interdigitized +from glayout.flow.placement.common_centroid_ab_ba import common_centroid_ab_ba from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port +from glayout.flow.primitives.via_gen import via_stack # My own cell library from reconfig_inv import reconfig_inv - -LONG_CHANNEL_WIDTH = 1.5 +import comp_dc #@cell def short_channel_tg( @@ -36,8 +38,8 @@ def short_channel_tg( # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) + pfet = pmos(pdk=pdk, gate_rmult=2, with_tie=False, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=2, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) # Placement and adding ports top_level = Component(name=component_name) @@ -109,11 +111,15 @@ def long_channel_tg( add_pin: bool = True, # For LVS **kwargs ) -> Component: + # To calculate the number of fingers for the underlying PMOS/NMOS layout + finger_num = math.ceil(pmos_width / comp_dc.tg_channel_width_base) + mos_width = comp_dc.tg_channel_width_base + # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) + pfet = pmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=pmos_length) + nfet = nmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=nmos_length) # Placement and adding ports top_level = Component(name=component_name) @@ -124,18 +130,92 @@ def long_channel_tg( # Placement mos_spacing = pdk.util_max_metal_seperation() - if orientation_config["pmos_degree"] != None: - pfet_ref.rotate(orientation_config["pmos_degree"]) - if orientation_config["nmos_degree"] != None: - nfet_ref.rotate(orientation_config["nmos_degree"]) + #if orientation_config["pmos_degree"] != None: + # pfet_ref.rotate(orientation_config["pmos_degree"]) + #if orientation_config["nmos_degree"] != None: + # nfet_ref.rotate(orientation_config["nmos_degree"]) + rename_ports_by_orientation(nfet_ref.mirror_y()) # To vertically flip the NMOS such that the its gate point toward the PMOS's gate pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + + pmos_drain_viaStack = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + pmos_drain_viaStack1 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + pmos_drain_viaStack2 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + pmos_drain_viaStack3 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + pmos_drain_viaStack4 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + pmos_drain_viaStack5 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + + nmos_drain_viaStack = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + nmos_drain_viaStack1 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + nmos_drain_viaStack2 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + nmos_drain_viaStack3 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + nmos_drain_viaStack4 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + nmos_drain_viaStack5 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") + + pmos_drain_viaStack_ref = prec_ref_center(pmos_drain_viaStack) + pmos_drain_viaStack1_ref = prec_ref_center(pmos_drain_viaStack1) + pmos_drain_viaStack2_ref = prec_ref_center(pmos_drain_viaStack2) + pmos_drain_viaStack3_ref = prec_ref_center(pmos_drain_viaStack3) + pmos_drain_viaStack4_ref = prec_ref_center(pmos_drain_viaStack4) + pmos_drain_viaStack5_ref = prec_ref_center(pmos_drain_viaStack5) + nmos_drain_viaStack_ref = prec_ref_center(nmos_drain_viaStack) + nmos_drain_viaStack1_ref = prec_ref_center(nmos_drain_viaStack1) + nmos_drain_viaStack2_ref = prec_ref_center(nmos_drain_viaStack2) + nmos_drain_viaStack3_ref = prec_ref_center(nmos_drain_viaStack3) + nmos_drain_viaStack4_ref = prec_ref_center(nmos_drain_viaStack4) + nmos_drain_viaStack5_ref = prec_ref_center(nmos_drain_viaStack5) + top_level.add(pmos_drain_viaStack_ref) + top_level.add(pmos_drain_viaStack1_ref) + top_level.add(pmos_drain_viaStack2_ref) + top_level.add(pmos_drain_viaStack3_ref) + top_level.add(pmos_drain_viaStack4_ref) + top_level.add(pmos_drain_viaStack5_ref) + top_level.add(nmos_drain_viaStack_ref) + top_level.add(nmos_drain_viaStack1_ref) + top_level.add(nmos_drain_viaStack2_ref) + top_level.add(nmos_drain_viaStack3_ref) + top_level.add(nmos_drain_viaStack4_ref) + top_level.add(nmos_drain_viaStack5_ref) + + pmos_drain_viaStack_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + pmos_drain_viaStack1_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + pmos_drain_viaStack2_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + pmos_drain_viaStack3_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) + pmos_drain_viaStack4_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) + pmos_drain_viaStack5_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) + nmos_drain_viaStack3_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) + nmos_drain_viaStack4_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) + nmos_drain_viaStack5_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) + pmos_drain_viaStack1_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) + pmos_drain_viaStack2_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) + pmos_drain_viaStack4_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) + pmos_drain_viaStack5_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) + nmos_drain_viaStack1_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) + nmos_drain_viaStack2_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) + nmos_drain_viaStack4_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) + nmos_drain_viaStack5_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) + + c = Component() + c.add_polygon( + [ + (nmos_drain_viaStack1_ref.xmin, nmos_drain_viaStack1_ref.ymin),#leftBottom_pos + (nmos_drain_viaStack2_ref.xmax, nmos_drain_viaStack2_ref.ymin),#rightBottom_pos + (pmos_drain_viaStack2_ref.xmax, pmos_drain_viaStack2_ref.ymax),#rightTop_pos + (pmos_drain_viaStack1_ref.xmin, pmos_drain_viaStack1_ref.ymax) #leftTop_pos + ], + layer=pdk.get_glayer("met3") + ) + c_ref = top_level.add_ref(c) + # Routing # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG # a) PMOS.source connected to NMOS.source - # b) PMOS.drain connected to NMOS.drain - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_S"], nfet_ref.ports["multiplier_0_drain_S"], glayer1="met3") # "in" of the TG - top_level << c_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_W"], cglayer="met3") # "out" of the TG + # b) PMOS.drain connected to NMOS.drain + top_level << c_route(pdk, pfet_ref.ports["drain_E"], nfet_ref.ports["drain_E"], cglayer="met3") # "out" of the TG + + #top_level << straight_route(pdk, pmos_drain_viaStack_ref.ports["top_met_S"], nmos_drain_viaStack_ref.ports["top_met_S"])#, glayer1="met3") + #top_level << straight_route(pdk, pmos_drain_viaStack1_ref.ports["top_met_S"], nmos_drain_viaStack1_ref.ports["top_met_S"]) + #top_level << straight_route(pdk, pmos_drain_viaStack2_ref.ports["top_met_S"], nmos_drain_viaStack2_ref.ports["top_met_S"]) # Add the ports aligned with the basic PMOS and NMOS top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") @@ -151,11 +231,11 @@ def long_channel_tg( # --- Port: A, i.e. input of the transmission gate A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"nmos_drain_S"), None)) + pin_info.append((A_pin, top_level.ports.get(f"nmos_source_S"), None)) # --- Port: Y, i.e. output of the transmission gate Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_N"), None)) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_S"), None)) # --- Port: C, i.e. gate control to the NMOS C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() C_pin.add_label(text="C", layer=met1_label) @@ -280,7 +360,7 @@ def reconfig_tg( ) -> Component: if pmos_width != nmos_width: raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif pmos_width >= LONG_CHANNEL_WIDTH: # Long-channel PMOS and NMOS + elif pmos_width >= comp_dc.tg_channel_width_base: # Long-channel PMOS and NMOS tg = long_channel_tg( pdk=pdk, component_name=component_name, From 8bd30da88b77af22d74c3742f51920f8a6685247 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sat, 23 Nov 2024 09:22:20 +0000 Subject: [PATCH 19/21] Final modification of the intergititized layout of the transmission gate PCell --- .../transmission_gate_saltychip/comp_dc.py | 7 +- .../transmission_gate_saltychip/eval.py | 18 +- .../gds/gate_ctrl_inv.gds | Bin 28126 -> 0 bytes .../gds/tg_ver1.gds | Bin 66472 -> 0 bytes .../gds/tg_ver2.gds | Bin 43572 -> 0 bytes .../gds/tg_with_ctrl.gds | Bin 67638 -> 0 bytes .../reconfig_inv.py | 2 +- .../drc/long_width_tg_3f598baa_drc.rpt | 3 + .../lvs/long_width_tg_3f598baa_lvs.rpt | 67 ++++ .../report/figures/tg_with_inv.png | Bin 99588 -> 0 bytes .../transmission_gate.py | 292 ++++++------------ 11 files changed, 188 insertions(+), 201 deletions(-) delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/gate_ctrl_inv.gds delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_ver1.gds delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_ver2.gds delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/tg_with_ctrl.gds create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/report/figures/tg_with_inv.png diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py index 2cc659058..5b9a59b20 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py @@ -1,4 +1,5 @@ def initialise(): - global inv_channel_width_base, tg_channel_width_base - inv_channel_width_base = 3.0 - tg_channel_width_base = 3.0 \ No newline at end of file + global inv_fet_width_base, tg_fet_width_base, tg_fet_width_factor + inv_fet_width_base = 3.0 + tg_fet_width_base = 3.0 + tg_fet_width_factor = tg_fet_width_base*4 \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 69d63a3ab..601503473 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -8,10 +8,12 @@ TARGET_PDK = sky130 PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" +DRC_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/drc" +LVS_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/lvs" -pmos_width = 6.0*2 +pmos_width = 12.0*1 pmos_length = 0.15 -nmos_width = 6.0*2 +nmos_width = 12.0*1 nmos_length = 0.15 def basic_tg_eval(): @@ -27,15 +29,19 @@ def basic_tg_eval(): tg_dut.show() tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") - ''' magic_drc_result = sky130.drc_magic( layout=tg_dut, - design_name=tg_dut.name#, - #output_file=f"{absolute_path}/{tg.name}.rpt" + design_name=tg_dut.name, + output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_drc.rpt" ) print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) print("--------------------------------------") - ''' + netgen_lvs_result = sky130.lvs_netgen( + layout=tg_dut, + design_name=tg_dut.name, + output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_lvs.rpt", + copy_intermediate_files=True + ) def gate_ctrl_inv_eval(): gate_ctrl_inv = reconfig_inv.reconfig_inv( diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/gate_ctrl_inv.gds b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/gds/gate_ctrl_inv.gds deleted file mode 100644 index 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z+P4c@kJpby{jt4;_R7rn!AEJP^;d@Y;rv5+d*%brgkV~4zyCoj^7hOJo(aLU-hTh1 z&f7B|cqRnXdi(tk{FVQn%*P@1pPvzdI?#{$GbOa%|G#_ef`v3fl2)X{R$n{U;nDjmAiRJmzQ2kkc4|a^7{h1In{_QRFd&2%d zRDbL=&N6=XXF||^#5mg5#-Y?12exv+N z>#g@cuvgy4WxfL{f75#F{SWM?Io|EB>6s8r>+SbH@Y8Yk;hLTa!L;6f{{uhr_sj>L z3Bk19e*Yu;=W#0jj>-2XJ+a(>8ry$vl^))lYg?{VvV*6S?;^KO+KlU>r%;)jEFdt?*Sd+G zjyiL%!j>!7Y?)ZSW-e7Ydhz(1Hf$KwVb&Qb*oLFdNYSjsnu+r^O>W*g*;0w}U(rne SD)Dnwr3y$li%Kk9Sp7d@K)$j7 diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py index 914c025a2..97ab884af 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py @@ -176,7 +176,7 @@ def reconfig_inv( ) -> Component: if pmos_width != nmos_width: raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif pmos_width >= comp_dc.inv_channel_width_base: # Long-channel PMOS and NMOS + elif pmos_width >= comp_dc.inv_fet_width_base: # Long-channel PMOS and NMOS inv = long_channel_inv( pdk=pdk, component_name=component_name, diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt new file mode 100644 index 000000000..d599f9790 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt @@ -0,0 +1,3 @@ +long_width_tg_3f598baa count: +---------------------------------------- + diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt new file mode 100644 index 000000000..41ca2a7df --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt @@ -0,0 +1,67 @@ + +Circuit 1 cell sky130_fd_pr__pfet_01v8 and Circuit 2 cell sky130_fd_pr__pfet_01v8 are black boxes. +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent. + +Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box. +Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box. + +Subcircuit pins: +Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 +-------------------------------------------|------------------------------------------- +1 |1 +2 |2 +3 |3 +4 |4 +--------------------------------------------------------------------------------------- +Cell pin lists are equivalent. +Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent. +Flattening unmatched subcell PMOS in circuit long_width_tg_3f598baa (1)(2 instances) +Flattening unmatched subcell NMOS in circuit long_width_tg_3f598baa (1)(2 instances) + +Cell long_width_tg_3f598baa (1) disconnected node: VDD +Cell long_width_tg_3f598baa (1) disconnected node: VSS +Class long_width_tg_3f598baa (0): Merged 6 parallel devices. +Class long_width_tg_3f598baa (1): Merged 2 parallel devices. +Cell long_width_tg_3f598baa (1) disconnected node: VDD +Cell long_width_tg_3f598baa (1) disconnected node: VSS +Subcircuit summary: +Circuit 1: long_width_tg_3f598baa |Circuit 2: long_width_tg_3f598baa +-------------------------------------------|------------------------------------------- +sky130_fd_pr__pfet_01v8 (4->1) |sky130_fd_pr__pfet_01v8 (8->1) +sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (8->1) +Number of devices: 2 |Number of devices: 2 +Number of nets: 6 **Mismatch** |Number of nets: 5 **Mismatch** +--------------------------------------------------------------------------------------- +NET mismatches: Class fragments follow (with fanout counts): +Circuit 1: long_width_tg_3f598baa |Circuit 2: long_width_tg_3f598baa + +--------------------------------------------------------------------------------------- +Net: w_n697_603# |Net: B + sky130_fd_pr__pfet_01v8/4 = 1 | sky130_fd_pr__pfet_01v8/4 = 1 + | sky130_fd_pr__nfet_01v8/4 = 1 + | +Net: (no pins) |(no matching net) + sky130_fd_pr__nfet_01v8/4 = 1 | +--------------------------------------------------------------------------------------- +Netlists do not match. + +Subcircuit pins: +Circuit 1: long_width_tg_3f598baa |Circuit 2: long_width_tg_3f598baa +-------------------------------------------|------------------------------------------- +Cell pin lists are equivalent. +Device classes long_width_tg_3f598baa and long_width_tg_3f598baa are equivalent. + +Final result: Netlists do not match. diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/report/figures/tg_with_inv.png b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/report/figures/tg_with_inv.png deleted file mode 100644 index c6b93bcc349dd5f0aac4becb0b31c526e9ef4848..0000000000000000000000000000000000000000 GIT binary patch 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+17,30 @@ from glayout.flow.placement.common_centroid_ab_ba import common_centroid_ab_ba from glayout.flow.pdk.util.comp_utils import prec_ref_center, movey, evaluate_bbox, align_comp_to_port from glayout.flow.primitives.via_gen import via_stack +from gdsfactory.cell import cell +from glayout.flow.spice import Netlist +from glayout.flow.pdk.util.snap_to_grid import component_snap_to_grid # My own cell library from reconfig_inv import reconfig_inv import comp_dc -#@cell -def short_channel_tg( +def tg_netlist(pmos: Component, nmos: Component) -> Netlist: + # A: tg.input, i.e. PMOS & NMOS source + # Y: tg.output, i.e. PMOS & NMOS drain + # C: connected to tg.nmos.gate + # CBAR: connected to tg.pmos.gate + # VDD: connected to tg.pmos.body + # VSS: connected to tg.nmos.body + netlist = Netlist(circuit_name='tg', nodes=['VDD', 'VSS', 'A', 'Y', 'C', 'CBAR']) + #netlist.connect_netlist(pmos.info['netlist'], [('D', 'Y'), ('G', 'CBAR'), ('S', 'A'), ('PB', 'VDD')]) + #netlist.connect_netlist(nmos.info['netlist'], [('D', 'Y'), ('G', 'C'), ('S', 'A'), ('NB', 'VSS')]) + netlist.connect_netlist(pmos.info['netlist'], [('D', 'Y'), ('G', 'CBAR'), ('S', 'A')]) + netlist.connect_netlist(nmos.info['netlist'], [('D', 'Y'), ('G', 'C'), ('S', 'A')]) + return netlist + +@cell +def short_width_tg( pdk: MappedPDK, component_name: str, orientation_config: @@ -35,6 +52,7 @@ def short_channel_tg( add_pin: bool = True, # For LVS **kwargs ) -> Component: + # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS @@ -96,14 +114,15 @@ def short_channel_tg( comp_ref = align_comp_to_port(comp, prt, alignment=alignment) top_level.add(comp_ref) - return top_level + component = component_snap_to_grid(rename_ports_by_orientation(top_level)) + component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) + return component + -#@cell -def long_channel_tg( +@cell +def long_width_tg( pdk: MappedPDK, component_name: str, - orientation_config: - dict[str, Union[int, str]], pmos_width, pmos_length, nmos_width, @@ -112,111 +131,94 @@ def long_channel_tg( **kwargs ) -> Component: # To calculate the number of fingers for the underlying PMOS/NMOS layout - finger_num = math.ceil(pmos_width / comp_dc.tg_channel_width_base) - mos_width = comp_dc.tg_channel_width_base + finger_num = math.ceil(pmos_width / comp_dc.tg_fet_width_base) + mos_width = comp_dc.tg_fet_width_base # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS pfet = pmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=pmos_length) nfet = nmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=nmos_length) - - # Placement and adding ports top_level = Component(name=component_name) pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) top_level.add(nfet_ref) - # Placement + # Placement.step_1: + # a) To vertically flip the NMOS such that the its gate point toward the PMOS's gate + # b) To move the PMOS above the NMOS mos_spacing = pdk.util_max_metal_seperation() - #if orientation_config["pmos_degree"] != None: - # pfet_ref.rotate(orientation_config["pmos_degree"]) - #if orientation_config["nmos_degree"] != None: - # nfet_ref.rotate(orientation_config["nmos_degree"]) - rename_ports_by_orientation(nfet_ref.mirror_y()) # To vertically flip the NMOS such that the its gate point toward the PMOS's gate + rename_ports_by_orientation(nfet_ref.mirror_y()) # pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) + # Placement.step_2: instantiation of the stacked vias to the source of every PMOS's finger + fet_source_finger_num = math.ceil((finger_num+1) / 2) + fet_drain_finger_num = finger_num+1-fet_source_finger_num + fet_source_fingerL_num = (fet_source_finger_num-1)/2 # excluding the centered one + fet_drain_fingerL_num = fet_drain_finger_num/2 + finger_col_num = fet_source_finger_num # A half of the fingers belongs to drain + finger_row_num = math.floor((mos_width*0.5) / (2*pdk.get_grule("met2")["min_width"]))-1 # To pave the stacked vias over all bottom half + print(f"finger_row_num: {finger_row_num}, finger_col_num: {finger_col_num}") + pmos_source_sdvias = list() + nmos_source_sdvias = list() + pmos_source_sdvias_ref = list() + nmos_source_sdvias_ref = list() + sdvias_row = [via_stack(pdk=pdk, glayer1="met2", glayer2="met3", fullbottom=True, fulltop=True) for i in range(finger_col_num)] + for row in range(finger_row_num): + pmos_source_sdvias.append(sdvias_row) + nmos_source_sdvias.append(sdvias_row) + + pmos_temp_ref = list() + nmos_temp_ref = list() + for col in range(finger_col_num): + temp_ref = prec_ref_center(pmos_source_sdvias[row][col]) + pmos_temp_ref.append(temp_ref) + temp_ref = prec_ref_center(nmos_source_sdvias[row][col]) + nmos_temp_ref.append(temp_ref) + + pmos_source_sdvias_ref.append(pmos_temp_ref) + nmos_source_sdvias_ref.append(nmos_temp_ref) + top_level.add(pmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) + top_level.add(nmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) + + # Placement.step_3: moving the all the stacked vias associated with the PMOS's source such that + # they are connected to the PMOS's source + centroid_index = math.floor(fet_source_finger_num/2) + y_offset = pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"] + x_s2d_offset = abs(pfet_ref.ports["multiplier_0_leftsd_array_row0_col0_bottom_via_S"].center[0]-pfet_ref.ports["multiplier_0_row0_col0_rightsd_array_row0_col0_bottom_via_S"].center[0]) + x_offset = x_s2d_offset*2 # Distance between one soure finger to another source finger at its left-/right-hand side is (S-to-D distance)*2 + for row in range(finger_row_num): + x_spacing = x_offset*centroid_index # initial value + for col in range(finger_col_num): + # Moving the positions of the stacked vias associated with the PMOS + pmos_source_sdvias_ref[row][col].movey(evaluate_bbox(nfet)[1]+mos_spacing-(y_offset*row)) + pmos_source_sdvias_ref[row][col].movex(x_spacing) + + # Moving the positions fo the stacked vias associated with NMOS + nmos_source_sdvias_ref[row][col].movey(y_offset*row) # In NMOS, the row_0 is exactly placed at the center position (0, 0), + # thereby no need for moving the stacked vias of row_0, i.e. movey by 0 + nmos_source_sdvias_ref[row][col].movex(x_spacing) + + x_spacing = x_spacing-x_offset - pmos_drain_viaStack = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - pmos_drain_viaStack1 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - pmos_drain_viaStack2 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - pmos_drain_viaStack3 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - pmos_drain_viaStack4 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - pmos_drain_viaStack5 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - - nmos_drain_viaStack = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - nmos_drain_viaStack1 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - nmos_drain_viaStack2 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - nmos_drain_viaStack3 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - nmos_drain_viaStack4 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - nmos_drain_viaStack5 = via_stack(pdk=pdk, glayer1="met2", glayer2="met3") - - pmos_drain_viaStack_ref = prec_ref_center(pmos_drain_viaStack) - pmos_drain_viaStack1_ref = prec_ref_center(pmos_drain_viaStack1) - pmos_drain_viaStack2_ref = prec_ref_center(pmos_drain_viaStack2) - pmos_drain_viaStack3_ref = prec_ref_center(pmos_drain_viaStack3) - pmos_drain_viaStack4_ref = prec_ref_center(pmos_drain_viaStack4) - pmos_drain_viaStack5_ref = prec_ref_center(pmos_drain_viaStack5) - nmos_drain_viaStack_ref = prec_ref_center(nmos_drain_viaStack) - nmos_drain_viaStack1_ref = prec_ref_center(nmos_drain_viaStack1) - nmos_drain_viaStack2_ref = prec_ref_center(nmos_drain_viaStack2) - nmos_drain_viaStack3_ref = prec_ref_center(nmos_drain_viaStack3) - nmos_drain_viaStack4_ref = prec_ref_center(nmos_drain_viaStack4) - nmos_drain_viaStack5_ref = prec_ref_center(nmos_drain_viaStack5) - top_level.add(pmos_drain_viaStack_ref) - top_level.add(pmos_drain_viaStack1_ref) - top_level.add(pmos_drain_viaStack2_ref) - top_level.add(pmos_drain_viaStack3_ref) - top_level.add(pmos_drain_viaStack4_ref) - top_level.add(pmos_drain_viaStack5_ref) - top_level.add(nmos_drain_viaStack_ref) - top_level.add(nmos_drain_viaStack1_ref) - top_level.add(nmos_drain_viaStack2_ref) - top_level.add(nmos_drain_viaStack3_ref) - top_level.add(nmos_drain_viaStack4_ref) - top_level.add(nmos_drain_viaStack5_ref) - - pmos_drain_viaStack_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - pmos_drain_viaStack1_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - pmos_drain_viaStack2_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - pmos_drain_viaStack3_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) - pmos_drain_viaStack4_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) - pmos_drain_viaStack5_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing - pdk.get_grule("met3")["min_separation"] - pdk.get_grule("met3")["min_width"]) - nmos_drain_viaStack3_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) - nmos_drain_viaStack4_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) - nmos_drain_viaStack5_ref.movey(pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"]) - pmos_drain_viaStack1_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) - pmos_drain_viaStack2_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) - pmos_drain_viaStack4_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) - pmos_drain_viaStack5_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) - nmos_drain_viaStack1_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) - nmos_drain_viaStack2_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) - nmos_drain_viaStack4_ref.movex(pfet_ref.ports["source_W"].center[0]+0.15) - nmos_drain_viaStack5_ref.movex(-pfet_ref.ports["source_W"].center[0]-0.15) - - c = Component() - c.add_polygon( + # Routing + # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG + # a) PMOS.source connected to NMOS.source by placing a large MET2-layered rectangle + # b) PMOS.drain connected to NMOS.drain + source_connection = Component() + source_connection.add_polygon( [ - (nmos_drain_viaStack1_ref.xmin, nmos_drain_viaStack1_ref.ymin),#leftBottom_pos - (nmos_drain_viaStack2_ref.xmax, nmos_drain_viaStack2_ref.ymin),#rightBottom_pos - (pmos_drain_viaStack2_ref.xmax, pmos_drain_viaStack2_ref.ymax),#rightTop_pos - (pmos_drain_viaStack1_ref.xmin, pmos_drain_viaStack1_ref.ymax) #leftTop_pos + (nmos_source_sdvias_ref[0][finger_col_num-1].xmin, nmos_source_sdvias_ref[0][finger_col_num-1].ymin),#leftBottom_pos + (pmos_source_sdvias_ref[0][finger_col_num-1].xmin, pmos_source_sdvias_ref[0][finger_col_num-1].ymax),#leftTop_pos + (pmos_source_sdvias_ref[0][0].xmax, pmos_source_sdvias_ref[0][0].ymax),#rightTop_pos + (nmos_source_sdvias_ref[0][0].xmax, nmos_source_sdvias_ref[0][0].ymin) #rightBottom_pos ], layer=pdk.get_glayer("met3") ) - c_ref = top_level.add_ref(c) - - # Routing - # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG - # a) PMOS.source connected to NMOS.source - # b) PMOS.drain connected to NMOS.drain + source_connection = top_level.add_ref(source_connection) top_level << c_route(pdk, pfet_ref.ports["drain_E"], nfet_ref.ports["drain_E"], cglayer="met3") # "out" of the TG - #top_level << straight_route(pdk, pmos_drain_viaStack_ref.ports["top_met_S"], nmos_drain_viaStack_ref.ports["top_met_S"])#, glayer1="met3") - #top_level << straight_route(pdk, pmos_drain_viaStack1_ref.ports["top_met_S"], nmos_drain_viaStack1_ref.ports["top_met_S"]) - #top_level << straight_route(pdk, pmos_drain_viaStack2_ref.ports["top_met_S"], nmos_drain_viaStack2_ref.ports["top_met_S"]) - # Add the ports aligned with the basic PMOS and NMOS top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") @@ -250,104 +252,11 @@ def long_channel_tg( alignment = ('c', 'b') if alignment is None else alignment comp_ref = align_comp_to_port(comp, prt, alignment=alignment) top_level.add(comp_ref) - - return top_level - -#@cell -def tg_with_ctrl( - pdk: MappedPDK, - component_name: str, - pmos_width, - pmos_length, - nmos_width, - nmos_length, - add_pin: bool = True, # For LVS - **kwargs -) -> Component: - # To prepare all necessary cells to construct a transmission gate, i.e. - # 1) transmission gate - # 2) Inverter - tg = tg_cell( - pdk=pdk, - component_name="tg", - orientation_config={"degree": 270}, - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=False - ) - inv = reconfig_inv( - pdk=pdk, - component_name="gate_ctrl_inv", - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - orientation="horizontal", - add_pin=False - ) - - # Instantiation of the essential cells - top_level = Component(name=component_name) - tg_ref = prec_ref_center(tg) - inv_ref = prec_ref_center(inv) - top_level.add(tg_ref) - top_level.add(inv_ref) - - # Placement - mos_spacing = pdk.util_max_metal_seperation() - nwell_min_spacing = pdk.get_grule("nwell")["min_separation"] - inv_cell_width = inv_ref.xsize # or = evaluate_bbox(inv)[0] - tg_ref.movex(inv_cell_width + nwell_min_spacing) - - # Routing - # 1) PMOS of the TG is switched on/off by the inverter's output - # 2) NMOS of the TG is switched on/off by an external control signal connected to inverter's input port as well - top_level << smart_route(pdk, inv_ref.ports["pmos_multiplier_0_drain_E"], tg_ref.ports["pmos_multiplier_0_gate_W"]) - top_level << straight_route(pdk, inv_ref.ports["nmos_multiplier_0_gate_S"], tg_ref.ports["nmos_multiplier_0_gate_S"], glayer1="met3") - - # Adding the ports - top_level.add_ports(tg_ref.get_ports_list(), prefix="tg_") - top_level.add_ports(inv_ref.get_ports_list(), prefix="inv_") - if add_pin == True: - # Add pins w/ labels for LVS - top_level.unlock() - pin_info = list() # list that contains all port and component information - met1_pin=(pdk.get_glayer("met1")[0], 20) - met1_label=(pdk.get_glayer("met1")[0], 5) - port_size = (0.24, 0.24) - # --- Port: A, i.e. input of the transmission gate - A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"tg_nmos_drain_S"), None)) - # --- Port: Y, i.e. output of the transmission gate - Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"tg_pmos_drain_S"), None)) - # --- Port: C, i.e. gate control to the NMOS - C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - C_pin.add_label(text="C", layer=met1_label) - pin_info.append((C_pin, top_level.ports.get(f"inv_nmos_gate_N"), None)) - # --- Port: VDD - VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VDD_pin.add_label(text="VDD", layer=met1_label) - pin_info.append((VDD_pin, top_level.ports.get(f"inv_pmos_drain_E"), None)) - # --- Port: VSS - VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VSS_pin.add_label(text="VSS", layer=met1_label) - pin_info.append((VSS_pin, top_level.ports.get(f"inv_nmos_source_W"), ('r', 't'))) - - # Move everythin to position - for comp, prt, alignment in pin_info: - alignment = ('c', 'b') if alignment is None else alignment - comp_ref = align_comp_to_port(comp, prt, alignment=alignment) - top_level.add(comp_ref) - - return top_level + component = component_snap_to_grid(rename_ports_by_orientation(top_level)) + component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) + return component -#@cell def reconfig_tg( pdk: MappedPDK, component_name, @@ -360,19 +269,20 @@ def reconfig_tg( ) -> Component: if pmos_width != nmos_width: raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif pmos_width >= comp_dc.tg_channel_width_base: # Long-channel PMOS and NMOS - tg = long_channel_tg( + elif (pmos_width % comp_dc.tg_fet_width_factor) != 0: + raise ValueError(f"PCell constraint: the widths of PMOS and NMOS must be multiple of {comp_dc.tg_fet_width_factor} (the given width: {pmos_width})") + elif pmos_width >= comp_dc.tg_fet_width_base: # Long-width PMOS and NMOS + tg = long_width_tg( pdk=pdk, component_name=component_name, - orientation_config={"nmos_degree": 180, "pmos_degree": 0}, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, add_pin=True ) - else: # Short-channel PMOS and NMOS - tg = short_channel_tg( + else: # Short-width PMOS and NMOS + tg = short_width_tg( pdk=pdk, component_name=component_name, orientation_config={"degree": 270}, From 6d7956460cacff5441fb39e3befd3d905809aeed Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sat, 23 Nov 2024 10:05:06 +0000 Subject: [PATCH 20/21] Modify the netlist gen for the transmission gate --- .../transmission_gate_saltychip/eval.py | 4 +- .../transmission_gate.py | 46 ++++++++++++++++++- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py index 601503473..004737730 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py @@ -32,14 +32,14 @@ def basic_tg_eval(): magic_drc_result = sky130.drc_magic( layout=tg_dut, design_name=tg_dut.name, - output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_drc.rpt" + output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_2_drc.rpt" ) print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) print("--------------------------------------") netgen_lvs_result = sky130.lvs_netgen( layout=tg_dut, design_name=tg_dut.name, - output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_lvs.rpt", + output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_2_lvs.rpt", copy_intermediate_files=True ) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py index bedfb3fa4..4f6414e2f 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py @@ -25,6 +25,7 @@ from reconfig_inv import reconfig_inv import comp_dc +''' def tg_netlist(pmos: Component, nmos: Component) -> Netlist: # A: tg.input, i.e. PMOS & NMOS source # Y: tg.output, i.e. PMOS & NMOS drain @@ -38,6 +39,43 @@ def tg_netlist(pmos: Component, nmos: Component) -> Netlist: netlist.connect_netlist(pmos.info['netlist'], [('D', 'Y'), ('G', 'CBAR'), ('S', 'A')]) netlist.connect_netlist(nmos.info['netlist'], [('D', 'Y'), ('G', 'C'), ('S', 'A')]) return netlist +''' + +def transmission_gate_netlist( + pdk: MappedPDK, + width: float, + multipliers: int, + length: float, + subckt_only: Optional[bool] = False +) -> Netlist: + if length is None: + length = pdk.get_grule('poly')['min_width'] + if width is None: + width = 3 + mtop = multipliers if subckt_only else 1 + model_pmos = pdk.models['pfet'] + model_nmos = pdk.models['nfet'] + print(f"model_pmos: {model_pmos}") + source_netlist = """.subckt {circuit_name} {nodes} """ + f'l={length} w={width} m={mtop} ' + """ +XM1 Y CBAR A {model_pmos} l={{l}} w={{w}} m={{m}} +XM2 Y C A {model_nmos} l={{l}} w={{w}} m={{m}}""" + source_netlist += "\n.ends {circuit_name}" + + instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" + + return Netlist( + circuit_name='tg', + nodes=['Y', 'C', 'CBAR', 'A'], + source_netlist=source_netlist, + instance_format=instance_format, + parameters={ + 'model_pmos': model_pmos, + 'model_nmos': model_nmos, + 'width': width, + 'length': length, + 'mult': multipliers + } + ) @cell def short_width_tg( @@ -254,7 +292,13 @@ def long_width_tg( top_level.add(comp_ref) component = component_snap_to_grid(rename_ports_by_orientation(top_level)) - component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) + + component.info['netlist'] = transmission_gate_netlist( + pdk, + width=kwargs.get('width', pmos_width), length=kwargs.get('length', pmos_length), multipliers=1, + subckt_only=True + ) + #component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) return component def reconfig_tg( From 0fcd05adeefd41ebbed945483b1cb5e3edcf9cf1 Mon Sep 17 00:00:00 2001 From: tsengs0 Date: Sun, 24 Nov 2024 19:20:06 +0000 Subject: [PATCH 21/21] Contributor: Team SaltyChip, Chipathon 2024 Add the directory of building the layout of transmission-gate PCell with GDS, Magic DRC and LVS results --- .../elementary/transmission_gate/README.md | 186 ++++++++ .../elementary/transmission_gate/__init__.py | 4 + .../elementary/transmission_gate/eval.py | 57 +++ .../gds/tg_cell_471429cf.gds | Bin 0 -> 77596 bytes .../tg_cell_471429cf_20241124185925_drc.rpt} | 2 +- .../tg_cell_471429cf_20241124185925_lvs.rpt} | 34 +- .../transmission_gate}/transmission_gate.py | 282 +++++++---- .../transmission_gate_saltychip/README.md | 36 -- .../transmission_gate_saltychip/__init__.py | 4 - .../transmission_gate_saltychip/comp_dc.py | 5 - .../transmission_gate_saltychip/eval.py | 92 ---- .../mimcap_array.py | 451 ------------------ .../reconfig_inv.py | 202 -------- 13 files changed, 446 insertions(+), 909 deletions(-) create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/README.md create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/__init__.py create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/eval.py create mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/gds/tg_cell_471429cf.gds rename openfasoc/generators/glayout/glayout/flow/blocks/{transmission_gate_saltychip/regression/drc/long_width_tg_3f598baa_drc.rpt => elementary/transmission_gate/regression/drc/tg_cell_471429cf_20241124185925_drc.rpt} (57%) rename openfasoc/generators/glayout/glayout/flow/blocks/{transmission_gate_saltychip/regression/lvs/long_width_tg_3f598baa_lvs.rpt => elementary/transmission_gate/regression/lvs/tg_cell_471429cf_20241124185925_lvs.rpt} (65%) rename openfasoc/generators/glayout/glayout/flow/blocks/{transmission_gate_saltychip => elementary/transmission_gate}/transmission_gate.py (53%) delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py delete mode 100644 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py delete mode 100755 openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/README.md new file mode 100644 index 000000000..489f1e42e --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/README.md @@ -0,0 +1,186 @@ + +# PCell of transmission gate +- Contributor: Team SaltyChip (from Chipathon 2024) + + +## Glayout Source codes (1) + +- **Function:** short_width_tg +- **Description/Purpose:** to build a layout of the transmission gate without multifinger transistors +- **Source file:** transmission_gate.py + +``` +def short_width_tg( + pdk: MappedPDK, + component_name: str = "tg", + with_substrate_tap: bool = False, + fet_min_width: float = 3, + pmos_width: float = 3, + pmos_length: float = 0.15, + nmos_width: float = 3, + nmos_length: float = 0.15, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: +``` +| Parameter | Type | Description | Default | Constraint/Limit | +| --- | --- | --- | --- | --- | +| pdk | MappedPDK | To select the target PDK | | sky130 or gf180mcu | +| component_name | string | The component name of the instantiated PCell | tg | | +| fet_min_width | float | A constraint to specify the mimimum width of each PMOS/NMOS inside the PCell | 3 (unit: um) | fet_min_width >= 2 | +| pmos_width | float | Width of the PMOS in the underlying PCell | 3 (unit: um) | pmos_width = fet_min_width | +| pmos_length | float | Length of the PMOS in the underlying PCell | 0.15 (unit: um) | pmos_length = 0.15 | +| nmos_width | float |Width of the NMOS in the underlying PCell | 3 (unit: um) | float | nmos_width = fet_min_width | +| nmos_length | float | Length of the NMOS in the underlying PCell | 0.15 (unit: um) | nmos_length = 0.15 | +| with_substrate_tap | bool | To add substrate tap surrounding the top level of the PCell if it is set True | False | | +| add_pin | bool | To add the pins with labels for the top level of the PCell (for the LVS) if it is set True | True | | + +--- + +## Glayout Source codes (2) + +- **Function:** long_width_tg +- **Description/Purpose:** to build an interdigitized layout of the transmission gate when the width of the underlying trasistors is relatively long +- **Source file:** transmission_gate.py + +``` +def long_width_tg( + pdk: MappedPDK, + component_name: str = "tg", + fet_min_width: float = 3, + pmos_width: float = 12, + pmos_length: float = 0.15, + nmos_width: float = 12, + nmos_length: float = 0.15, + with_substrate_tap: bool = True, + add_pin: bool = True, # For LVS + **kwargs +) -> Component: +``` +| Parameter | Type | Description | Default | Constraint/Limit | +| --- | --- | --- | --- | --- | +| pdk | MappedPDK | To select the target PDK | | sky130 or gf180mcu | +| component_name | string | The component name of the instantiated PCell | tg | | +| fet_min_width | float | A constraint to specify the mimimum width of each PMOS/NMOS inside the PCell | 3 (unit: um) | fet_min_width >= 2 | +| pmos_width | float | Width of the PMOS in the underlying PCell | 12 (unit: um) | **pmos_width** must be a multiple of **fet_min_width*4** | +| pmos_length | float | Length of the PMOS in the underlying PCell | 0.15 (unit: um) | pmos_length = 0.15 | +| nmos_width | float |Width of the NMOS in the underlying PCell | 12 (unit: um) | **nmos_width** must be a multiple of **fet_min_width*4** | +| nmos_length | float | Length of the NMOS in the underlying PCell | 0.15 (unit: um) | nmos_length = 0.15 | +| add_pin | bool | To add the pins with labels for the top level of the PCell (for the LVS) if it is set True | True | | +| with_substrate_tap | bool | To add substrate tap surrounding the top level of the PCell if it is set True | False | | + +--- + +## Glayout Source codes (3) + +- **Function:** tg_cell +- **Description/Purpose:** a generic function to build a layout of the transmission gate in an either single-finger or multifinger fashion depeending on the specified widht of PMOS/NMOS +- **Source file:** transmission_gate.py + +``` +def tg_cell( + pdk: MappedPDK, + component_name: str = "tg", + fet_min_width: float = 3, + pmos_width: float = 6, + pmos_length: float = 0.15, + nmos_width: float = 6, + nmos_length: float = 0.15, + add_pin: bool = True, # For LVS + with_substrate_tap: bool = True, + **kwargs +) -> Component: +``` +| Parameter | Type | Description | Default | Constraint/Limit | +| --- | --- | --- | --- | --- | +| pdk | MappedPDK | To select the target PDK | | sky130 or gf180mcu | +| component_name | string | The component name of the instantiated PCell | tg | | +| fet_min_width | float | A constraint to specify the mimimum width of each PMOS/NMOS inside the PCell | 3 (unit: um) | fet_min_width >= 2 | +| pmos_width | float | Width of the PMOS in the underlying PCell | 12 (unit: um) | **pmos_width** must be equal to **fet_min_width** or a multiple of **fet_min_width*4** | +| pmos_length | float | Length of the PMOS in the underlying PCell | 0.15 (unit: um) | pmos_length = 0.15 | +| nmos_width | float |Width of the NMOS in the underlying PCell | 12 (unit: um) | **nmos_width** must be equal to **fet_min_width** or a multiple of **fet_min_width*4** | +| nmos_length | float | Length of the NMOS in the underlying PCell | 0.15 (unit: um) | nmos_length = 0.15 | +| add_pin | bool | To add the pins with labels for the top level of the PCell (for the LVS) if it is set True | True | | +| with_substrate_tap | bool | To add substrate tap surrounding the top level of the PCell if it is set True | False | | + +--- + +## Example code of evaluating the PCell + +In this example, a Python file, **eval.py** created under the directory **transmission_gate**, is wrote as follow which diplays the GDS and the check the DRC and LVS results. + +``` +from datetime import datetime +import subprocess +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +import transmission_gate as tg + +TARGET_PDK = sky130 +PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) +GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" +DRC_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/drc" +LVS_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/lvs" + +pmos_width = 12 +pmos_length = 0.15 +nmos_width = 12 +nmos_length = 0.15 +fet_min_width = 3 + +def basic_tg_eval(): + tg_dut = tg.tg_cell( + pdk=TARGET_PDK, + component_name="tg", + fet_min_width=fet_min_width, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + with_substrate_tap=True, + add_pin=True + ) + + tg_dut.show() + print(tg_dut.info["netlist"].generate_netlist()) + tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") + + now = datetime.now() # Get the current date and time + regression_id = now.strftime('%Y%m%d%H%M%S') # Format the date and time without spaces + + magic_drc_result = sky130.drc_magic( + layout=tg_dut, + design_name=tg_dut.name, + output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_{regression_id}_drc.rpt" + ) + print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) + print("--------------------------------------") + netgen_lvs_result = sky130.lvs_netgen( + layout=tg_dut, + design_name=tg_dut.name, + output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_{regression_id}_lvs.rpt", + copy_intermediate_files=True + ) + +def main(): + basic_tg_eval() + +if __name__ == "__main__": + main() +``` + +--- + +## Progress (until 24/11/2024) + +- ToDo list +- Transmission gate + - [x] Layout + - [x] Add ports w/ labels onto the layout (for the subsequent LVS) + - [x] DRC of the layout w/o error (Magic) + - [ ] DRC of the layout w/o error (Klayout) + - [x] Create the baseline schematic of the created component + - [ ] LVS w/o error + - [x] Document about the PCell specification + - [ ] PEX and create the testbench + - [ ] Verification gets passed \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/__init__.py b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/__init__.py new file mode 100644 index 000000000..2e5c967f8 --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/__init__.py @@ -0,0 +1,4 @@ +from glayout.flow.blocks.elementary.transmission_gate.transmission_gate import transmission_gate_netlist +from glayout.flow.blocks.elementary.transmission_gate.transmission_gate import short_width_tg +from glayout.flow.blocks.elementary.transmission_gate.transmission_gate import long_width_tg +from glayout.flow.blocks.elementary.transmission_gate.transmission_gate import tg_cell \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/eval.py new file mode 100644 index 000000000..e3ab98b8e --- /dev/null +++ b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/eval.py @@ -0,0 +1,57 @@ +from datetime import datetime +import subprocess +#from glayout.flow.pdk.gf180_mapped import gf180 +from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 +import transmission_gate as tg + +TARGET_PDK = sky130 +PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) +GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" +DRC_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/drc" +LVS_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/lvs" + +pmos_width = 12 +pmos_length = 0.15 +nmos_width = 12 +nmos_length = 0.15 +fet_min_width = 3 + +def basic_tg_eval(): + tg_dut = tg.tg_cell( + pdk=TARGET_PDK, + component_name="tg", + fet_min_width=fet_min_width, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + with_substrate_tap=True, + add_pin=True + ) + + tg_dut.show() + print(tg_dut.info["netlist"].generate_netlist()) + tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") + + now = datetime.now() # Get the current date and time + regression_id = now.strftime('%Y%m%d%H%M%S') # Format the date and time without spaces + + magic_drc_result = sky130.drc_magic( + layout=tg_dut, + design_name=tg_dut.name, + output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_{regression_id}_drc.rpt" + ) + print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) + print("--------------------------------------") + netgen_lvs_result = sky130.lvs_netgen( + layout=tg_dut, + design_name=tg_dut.name, + output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_{regression_id}_lvs.rpt", + copy_intermediate_files=True + ) + +def main(): + basic_tg_eval() + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/gds/tg_cell_471429cf.gds b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/gds/tg_cell_471429cf.gds new file mode 100644 index 0000000000000000000000000000000000000000..5723b19f9ff50124190d2f8776f1dfaf7bc87714 GIT binary patch literal 77596 zcmd6wf2?IydH2t`=bjlW3Q`=EAX=h?7z-+tjMbJO1v4c|hDz{jo3Hu;F*!b@sXE zU2wtKzp(jrzi{*~o_qdi{yC%3hUd?XP8e<2e{S@`(a*nNvb3~t>}WK1Cfj|>-0*)J z-Q@lG14nKAuXN*=jv9?7o0gWu>4Wes%d|e(v_kyPH~E(?B>qO?#LvU)JG6ddia#mk zKa2KP5hs2P?(Wd~Rjb5*qluq?UK4Lliaz;9if@j;<9~V-armE}2Jzq0`cWyq@;`l9 zlYhFs$=}lY%Tj!mfAVmXfAVybzoqquhvVn}t%;xN_~pOQ`uxA8_{#sh@=*WjOCj|) ztUJO9e!ztH+*X#UgnXKndw|93Y2 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--------------------------------------------------------------------------------------- NET mismatches: Class fragments follow (with fanout counts): -Circuit 1: long_width_tg_3f598baa |Circuit 2: long_width_tg_3f598baa +Circuit 1: tg_cell_471429cf |Circuit 2: tg_cell_471429cf --------------------------------------------------------------------------------------- -Net: w_n697_603# |Net: B - sky130_fd_pr__pfet_01v8/4 = 1 | sky130_fd_pr__pfet_01v8/4 = 1 - | sky130_fd_pr__nfet_01v8/4 = 1 +Net: w_n715_603# |Net: VDD + sky130_fd_pr__pfet_01v8/4 = 3 | sky130_fd_pr__pfet_01v8/4 = 1 | -Net: (no pins) |(no matching net) - sky130_fd_pr__nfet_01v8/4 = 1 | +Net: a_n877_n684# |Net: VSS + sky130_fd_pr__nfet_01v8/4 = 3 | sky130_fd_pr__nfet_01v8/4 = 1 --------------------------------------------------------------------------------------- Netlists do not match. Subcircuit pins: -Circuit 1: long_width_tg_3f598baa |Circuit 2: long_width_tg_3f598baa +Circuit 1: tg_cell_471429cf |Circuit 2: tg_cell_471429cf -------------------------------------------|------------------------------------------- Cell pin lists are equivalent. -Device classes long_width_tg_3f598baa and long_width_tg_3f598baa are equivalent. +Device classes tg_cell_471429cf and tg_cell_471429cf are equivalent. Final result: Netlists do not match. diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/transmission_gate.py similarity index 53% rename from openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py rename to openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/transmission_gate.py index 4f6414e2f..f70a86aaa 100755 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/transmission_gate.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/transmission_gate/transmission_gate.py @@ -20,26 +20,7 @@ from gdsfactory.cell import cell from glayout.flow.spice import Netlist from glayout.flow.pdk.util.snap_to_grid import component_snap_to_grid - -# My own cell library -from reconfig_inv import reconfig_inv -import comp_dc - -''' -def tg_netlist(pmos: Component, nmos: Component) -> Netlist: - # A: tg.input, i.e. PMOS & NMOS source - # Y: tg.output, i.e. PMOS & NMOS drain - # C: connected to tg.nmos.gate - # CBAR: connected to tg.pmos.gate - # VDD: connected to tg.pmos.body - # VSS: connected to tg.nmos.body - netlist = Netlist(circuit_name='tg', nodes=['VDD', 'VSS', 'A', 'Y', 'C', 'CBAR']) - #netlist.connect_netlist(pmos.info['netlist'], [('D', 'Y'), ('G', 'CBAR'), ('S', 'A'), ('PB', 'VDD')]) - #netlist.connect_netlist(nmos.info['netlist'], [('D', 'Y'), ('G', 'C'), ('S', 'A'), ('NB', 'VSS')]) - netlist.connect_netlist(pmos.info['netlist'], [('D', 'Y'), ('G', 'CBAR'), ('S', 'A')]) - netlist.connect_netlist(nmos.info['netlist'], [('D', 'Y'), ('G', 'C'), ('S', 'A')]) - return netlist -''' +from glayout.flow.primitives.guardring import tapring def transmission_gate_netlist( pdk: MappedPDK, @@ -57,8 +38,8 @@ def transmission_gate_netlist( model_nmos = pdk.models['nfet'] print(f"model_pmos: {model_pmos}") source_netlist = """.subckt {circuit_name} {nodes} """ + f'l={length} w={width} m={mtop} ' + """ -XM1 Y CBAR A {model_pmos} l={{l}} w={{w}} m={{m}} -XM2 Y C A {model_nmos} l={{l}} w={{w}} m={{m}}""" +XM1 Y C A VDD {model_pmos} l={{l}} w={{w}} m={{m}} +XM2 Y CBAR A VSS {model_nmos} l={{l}} w={{w}} m={{m}}""" source_netlist += "\n.ends {circuit_name}" instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" @@ -77,16 +58,16 @@ def transmission_gate_netlist( } ) -@cell +#@cell def short_width_tg( pdk: MappedPDK, - component_name: str, - orientation_config: - dict[str, Union[int, str]], - pmos_width, - pmos_length, - nmos_width, - nmos_length, + component_name: str = "tg", + with_substrate_tap: bool = False, + fet_min_width: float = 3, + pmos_width: float = 3, + pmos_length: float = 0.15, + nmos_width: float = 3, + nmos_length: float = 0.15, add_pin: bool = True, # For LVS **kwargs ) -> Component: @@ -94,36 +75,117 @@ def short_width_tg( # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, gate_rmult=2, with_tie=False, with_substrate_tap=False, with_dummy=(True, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, gate_rmult=2, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, True), width=nmos_width, length=nmos_length) - - # Placement and adding ports + pfet = pmos(pdk=pdk, gate_rmult=1, with_tie=False, with_substrate_tap=False, with_dummy=(True, True), width=pmos_width, length=pmos_length) + nfet = nmos(pdk=pdk, gate_rmult=1, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(True, True), width=nmos_width, length=nmos_length) top_level = Component(name=component_name) pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) top_level.add(nfet_ref) - # Placement + # Placement (1) + # a) To vertically flip the NMOS such that the its gate point toward the PMOS's gate + # b) To move the PMOS above the NMOS mos_spacing = pdk.util_max_metal_seperation() - if orientation_config["degree"] != None: - pfet_ref.rotate(orientation_config["degree"]) - nfet_ref.rotate(orientation_config["degree"]) + rename_ports_by_orientation(nfet_ref.mirror_y()) pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - # Routing - # To simplify the routing for the parallel-gate transistors, the layout is realised as follow which is expected to be equivalent to a TG - # a) PMOS.source connected to NMOS.source - # b) PMOS.drain connected to NMOS.drain - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_source_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # "in" of the TG - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_source_E"], glayer1="met2") # "out" of the TG - # Add the ports aligned with the basic PMOS and NMOS top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + + # Placement (2): + # a) Add a bunch of met1-to-met2 vias attached to the mcron-layered points inside the source of PMOS/NMOS + # b) Add a bunch of met1-to-met2 vias attached to the mcron-layered points inside the drain of PMOS/NMOS + fet_source_finger_num = 1 + fet_drain_finger_num = 1 + finger_col_num = 1 + finger_row_num = math.floor((fet_min_width*0.5) / (2*pdk.get_grule("met2")["min_width"]))-1 # To pave the stacked vias over all bottom half + pmos_source_sdvias = list() + nmos_source_sdvias = list() + pmos_drain_sdvias = list() + nmos_drain_sdvias = list() + pmos_source_sdvias_ref = list() + nmos_source_sdvias_ref = list() + pmos_drain_sdvias_ref = list() + nmos_drain_sdvias_ref = list() + sdvias_row = [via_stack(pdk=pdk, glayer1="met2", glayer2="met3", fullbottom=True, fulltop=True) for i in range(finger_col_num)] + for row in range(finger_row_num): + pmos_source_sdvias.append(sdvias_row) + nmos_source_sdvias.append(sdvias_row) + pmos_drain_sdvias.append(sdvias_row) + nmos_drain_sdvias.append(sdvias_row) + + pmos_source_cols_ref = list() + nmos_source_cols_ref = list() + pmos_drain_cols_ref = list() + nmos_drain_cols_ref = list() + for col in range(finger_col_num): + # For source terminals of the PMOS and NMOS + temp_ref = prec_ref_center(pmos_source_sdvias[row][col]) + pmos_source_cols_ref.append(temp_ref) + temp_ref = prec_ref_center(nmos_source_sdvias[row][col]) + nmos_source_cols_ref.append(temp_ref) + # For drain terminals of the PMOS and NMOS + temp_ref = prec_ref_center(pmos_drain_sdvias[row][col]) + pmos_drain_cols_ref.append(temp_ref) + temp_ref = prec_ref_center(nmos_drain_sdvias[row][col]) + nmos_drain_cols_ref.append(temp_ref) + + pmos_source_sdvias_ref.append(pmos_source_cols_ref) + nmos_source_sdvias_ref.append(nmos_source_cols_ref) + pmos_drain_sdvias_ref.append(pmos_drain_cols_ref) + nmos_drain_sdvias_ref.append(nmos_drain_cols_ref) + top_level.add(pmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) + top_level.add(nmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) + top_level.add(pmos_drain_sdvias_ref[row][col] for col in range(finger_col_num)) + top_level.add(nmos_drain_sdvias_ref[row][col] for col in range(finger_col_num)) + # Placement (3): + # a) Move all the a part of particular stacked vias such that they are connected to the source of PMOS/NMOS + # b) Move all the a part of particular stacked vias such that they are connected to the drain of PMOS/NMOS + y_offset = pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"] + x_offset = abs(top_level.ports["pmos_multiplier_0_leftsd_array_row0_col0_bottom_via_N"].center[0]-pfet_ref.center[0]) + for row in range(finger_row_num): + # Moving the positions of the stacked vias associated with the PMOS + pmos_source_sdvias_ref[row][0].movex(-x_offset) + pmos_source_sdvias_ref[row][0].movey(evaluate_bbox(nfet)[1]+mos_spacing-(y_offset*row)) + pmos_drain_sdvias_ref[row][0].movex(x_offset) + pmos_drain_sdvias_ref[row][0].movey(evaluate_bbox(nfet)[1]+mos_spacing-(y_offset*row)) + + # Moving the positions fo the stacked vias associated with NMOS + nmos_source_sdvias_ref[row][0].movex(-x_offset) + nmos_source_sdvias_ref[row][0].movey(y_offset*row) + nmos_drain_sdvias_ref[row][0].movex(x_offset) + nmos_drain_sdvias_ref[row][0].movey(y_offset*row) + + # Routing + # a) PMOS.source connected to NMOS.source by placing a large MET2-layered rectangle + # b) PMOS.drain connected to NMOS.drain by placing a large MET2-layered rectangle + print("nmos_source_sdvias_ref.len: ", nmos_source_sdvias_ref) + sdvias_connection = Component() + sdvias_connection.add_polygon( + [ + (nmos_source_sdvias_ref[0][finger_col_num-1].xmin, nmos_source_sdvias_ref[0][finger_col_num-1].ymin),#leftBottom_pos + (pmos_source_sdvias_ref[0][finger_col_num-1].xmin, pmos_source_sdvias_ref[0][finger_col_num-1].ymax),#leftTop_pos + (pmos_source_sdvias_ref[0][0].xmax, pmos_source_sdvias_ref[0][0].ymax),#rightTop_pos + (nmos_source_sdvias_ref[0][0].xmax, nmos_source_sdvias_ref[0][0].ymin) #rightBottom_pos + ], + layer=pdk.get_glayer("met3") + ) + sdvias_connection.add_polygon( + [ + (nmos_drain_sdvias_ref[0][finger_col_num-1].xmin, nmos_drain_sdvias_ref[0][finger_col_num-1].ymin),#leftBottom_pos + (pmos_drain_sdvias_ref[0][finger_col_num-1].xmin, pmos_drain_sdvias_ref[0][finger_col_num-1].ymax),#leftTop_pos + (pmos_drain_sdvias_ref[0][0].xmax, pmos_drain_sdvias_ref[0][0].ymax),#rightTop_pos + (nmos_drain_sdvias_ref[0][0].xmax, nmos_drain_sdvias_ref[0][0].ymin) #rightBottom_pos + ], + layer=pdk.get_glayer("met3") + ) + sdvias_connection_ref = top_level.add_ref(sdvias_connection) + + # Add pins w/ labels for LVS if add_pin == True: - # Add pins w/ labels for LVS top_level.unlock() pin_info = list() # list that contains all port and component information met1_pin=(pdk.get_glayer("met1")[0], 20) @@ -132,15 +194,15 @@ def short_width_tg( # --- Port: A, i.e. input of the transmission gate A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"nmos_drain_S"), None)) + pin_info.append((A_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) # --- Port: Y, i.e. output of the transmission gate Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"pmos_drain_S"), None)) + pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), ('l', 't'))) # --- Port: C, i.e. gate control to the NMOS C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() C_pin.add_label(text="C", layer=met1_label) - pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_N"), None)) + pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_S"), None)) # --- Port: CBAR, i.e. gate control to the PMOS CBAR_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() CBAR_pin.add_label(text="CBAR", layer=met1_label) @@ -152,52 +214,65 @@ def short_width_tg( comp_ref = align_comp_to_port(comp, prt, alignment=alignment) top_level.add(comp_ref) - component = component_snap_to_grid(rename_ports_by_orientation(top_level)) - component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) - return component + # Add substrate tap + if with_substrate_tap: + substrate_tap = tapring(pdk, enclosed_rectangle=pdk.snap_to_2xgrid(evaluate_bbox(top_level.flatten(),padding=pdk.util_max_metal_seperation()))) + substrate_tap_ref = top_level << movey(substrate_tap,destination=pdk.snap_to_2xgrid(top_level.flatten().center[1],snap4=True)) + top_level.add_ports(substrate_tap_ref.get_ports_list(),prefix="substratetap_") + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + top_level.info['netlist'] = transmission_gate_netlist( + pdk, + width=kwargs.get('width', pmos_width), length=kwargs.get('length', pmos_length), multipliers=1, + subckt_only=True + ) + top_level.info['netlist'].generate_netlist() + return top_level -@cell + +#@cell def long_width_tg( pdk: MappedPDK, - component_name: str, - pmos_width, - pmos_length, - nmos_width, - nmos_length, + component_name: str = "tg", + fet_min_width: float = 3, + pmos_width: float = 12, + pmos_length: float = 0.15, + nmos_width: float = 12, + nmos_length: float = 0.15, + with_substrate_tap: bool = True, add_pin: bool = True, # For LVS **kwargs ) -> Component: # To calculate the number of fingers for the underlying PMOS/NMOS layout - finger_num = math.ceil(pmos_width / comp_dc.tg_fet_width_base) - mos_width = comp_dc.tg_fet_width_base + finger_num = math.ceil(pmos_width / fet_min_width) # To prepare all necessary cells to construct a transmission gate, i.e. # 1) PMOS # 2) NMOS - pfet = pmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=pmos_length) - nfet = nmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=3, gate_rmult=1, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=mos_width, length=nmos_length) + pfet = pmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=1, gate_rmult=1, with_tie=False, with_substrate_tap=False, with_dummy=(True, True), width=fet_min_width, length=pmos_length) + nfet = nmos(pdk=pdk, multipliers=1, fingers=finger_num, interfinger_rmult=1, gate_rmult=1, with_tie=False, with_dnwell=False, with_substrate_tap=False, with_dummy=(True, True), width=fet_min_width, length=nmos_length) top_level = Component(name=component_name) pfet_ref = prec_ref_center(pfet) nfet_ref = prec_ref_center(nfet) top_level.add(pfet_ref) top_level.add(nfet_ref) - # Placement.step_1: - # a) To vertically flip the NMOS such that the its gate point toward the PMOS's gate - # b) To move the PMOS above the NMOS + # Placement (1) + # a) To vertically flip the NMOS such that the its gate point toward the PMOS's gate + # b) To move the PMOS above the NMOS mos_spacing = pdk.util_max_metal_seperation() rename_ports_by_orientation(nfet_ref.mirror_y()) # pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - # Placement.step_2: instantiation of the stacked vias to the source of every PMOS's finger + # Placement (2): + # a) Add a bunch of met1-to-met2 vias attached to the mcron-layered points inside the source of PMOS/NMOS fet_source_finger_num = math.ceil((finger_num+1) / 2) fet_drain_finger_num = finger_num+1-fet_source_finger_num fet_source_fingerL_num = (fet_source_finger_num-1)/2 # excluding the centered one fet_drain_fingerL_num = fet_drain_finger_num/2 finger_col_num = fet_source_finger_num # A half of the fingers belongs to drain - finger_row_num = math.floor((mos_width*0.5) / (2*pdk.get_grule("met2")["min_width"]))-1 # To pave the stacked vias over all bottom half - print(f"finger_row_num: {finger_row_num}, finger_col_num: {finger_col_num}") + finger_row_num = math.floor((fet_min_width*0.5) / (2*pdk.get_grule("met2")["min_width"]))-1 # To pave the stacked vias over all bottom half +# print(f"finger_row_num: {finger_row_num}, finger_col_num: {finger_col_num}") pmos_source_sdvias = list() nmos_source_sdvias = list() pmos_source_sdvias_ref = list() @@ -220,8 +295,8 @@ def long_width_tg( top_level.add(pmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) top_level.add(nmos_source_sdvias_ref[row][col] for col in range(finger_col_num)) - # Placement.step_3: moving the all the stacked vias associated with the PMOS's source such that - # they are connected to the PMOS's source + # Placement (3): + # a) Move all the a part of particular stacked vias such that they are connected to the source of PMOS/NMOS centroid_index = math.floor(fet_source_finger_num/2) y_offset = pdk.get_grule("met3")["min_separation"]+pdk.get_grule("met3")["min_width"] x_s2d_offset = abs(pfet_ref.ports["multiplier_0_leftsd_array_row0_col0_bottom_via_S"].center[0]-pfet_ref.ports["multiplier_0_row0_col0_rightsd_array_row0_col0_bottom_via_S"].center[0]) @@ -261,8 +336,8 @@ def long_width_tg( top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") + # Add pins w/ labels for LVS if add_pin == True: - # Add pins w/ labels for LVS top_level.unlock() pin_info = list() # list that contains all port and component information met1_pin=(pdk.get_glayer("met1")[0], 20) @@ -279,7 +354,7 @@ def long_width_tg( # --- Port: C, i.e. gate control to the NMOS C_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() C_pin.add_label(text="C", layer=met1_label) - pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_N"), None)) + pin_info.append((C_pin, top_level.ports.get(f"nmos_gate_S"), None)) # --- Port: CBAR, i.e. gate control to the PMOS CBAR_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() CBAR_pin.add_label(text="CBAR", layer=met1_label) @@ -290,50 +365,63 @@ def long_width_tg( alignment = ('c', 'b') if alignment is None else alignment comp_ref = align_comp_to_port(comp, prt, alignment=alignment) top_level.add(comp_ref) - - component = component_snap_to_grid(rename_ports_by_orientation(top_level)) + + # Add substrate tap + if with_substrate_tap: + substrate_tap = tapring(pdk, enclosed_rectangle=pdk.snap_to_2xgrid(evaluate_bbox(top_level.flatten(),padding=pdk.util_max_metal_seperation()))) + substrate_tap_ref = top_level << movey(substrate_tap,destination=pdk.snap_to_2xgrid(top_level.flatten().center[1],snap4=True)) + top_level.add_ports(substrate_tap_ref.get_ports_list(),prefix="substratetap_") - component.info['netlist'] = transmission_gate_netlist( + top_level = component_snap_to_grid(rename_ports_by_orientation(top_level)) + top_level.info['netlist'] = transmission_gate_netlist( pdk, - width=kwargs.get('width', pmos_width), length=kwargs.get('length', pmos_length), multipliers=1, + width=kwargs.get('width', pmos_width), length=kwargs.get('length', pmos_length), multipliers=finger_num, subckt_only=True ) - #component.info['netlist'] = tg_netlist(pmos=pfet, nmos=nfet) - return component + top_level.info['netlist'].generate_netlist() -def reconfig_tg( + return top_level + +@cell +def tg_cell( pdk: MappedPDK, - component_name, - pmos_width, - pmos_length, - nmos_width, - nmos_length, + component_name: str = "tg", + fet_min_width: float = 3, + pmos_width: float = 12, + pmos_length: float = 0.15, + nmos_width: float = 12, + nmos_length: float = 0.15, add_pin: bool = True, # For LVS + with_substrate_tap: bool = True, **kwargs ) -> Component: if pmos_width != nmos_width: raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif (pmos_width % comp_dc.tg_fet_width_factor) != 0: - raise ValueError(f"PCell constraint: the widths of PMOS and NMOS must be multiple of {comp_dc.tg_fet_width_factor} (the given width: {pmos_width})") - elif pmos_width >= comp_dc.tg_fet_width_base: # Long-width PMOS and NMOS - tg = long_width_tg( - pdk=pdk, - component_name=component_name, - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=True - ) + elif pmos_width > fet_min_width: # Long-width PMOS and NMOS + if (pmos_width % (fet_min_width*4)) != 0: + raise ValueError(f"PCell constraint: the widths of PMOS and NMOS must be a multiple of {fet_min_width*4} um, however the given width is {pmos_width} um") + else: + tg = long_width_tg( + pdk=pdk, + component_name=component_name, + fet_min_width=fet_min_width, + pmos_width=pmos_width, + pmos_length=pmos_length, + nmos_width=nmos_width, + nmos_length=nmos_length, + with_substrate_tap=True, + add_pin=True + ) else: # Short-width PMOS and NMOS tg = short_width_tg( pdk=pdk, component_name=component_name, - orientation_config={"degree": 270}, + fet_min_width=fet_min_width, pmos_width=pmos_width, pmos_length=pmos_length, nmos_width=nmos_width, nmos_length=nmos_length, + with_substrate_tap=True, add_pin=True ) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md deleted file mode 100644 index 22bafe394..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/README.md +++ /dev/null @@ -1,36 +0,0 @@ -# Transmission gate block for SAR A/D converter -- Team: SaltyChip -- Design (our target): DAC for 6-bit A/D converter -- Progress: ongoing, 03/11/2024 - -| Design File | Description | Remark | -| --- | --- | --- | -| inv_lib.py | Layout generation of inverter for controlling the transmission gate's PMOS and NMOS | | -| transmission_gate.py | Layout generation of a transmission gate | The layout is still under construction | -| mimcap_array.py | Layout generation of a 8x8 MIM capacitor array | Transmission gate combined with a MIM capacitor array is the aim in this project | - ---- - -Submission of PR Draft (deadline: 24/11/2024) - -- ToDo list -- Transmission gate - - [x] Layout - - [ ] Add ports w/ labels onto the layout (for the subsequent LVS) - - [ ] DRC of the layout w/o error (Magic) - - [ ] DRC of the layout w/o error (Klayout) - - [ ] Create the baseline schematic of the created component - - [ ] LVS w/o error - - [ ] Document about the PCell specification - - [ ] PEX and create the testbench - - [ ] Verification gets passed -- MIMI capacitor array - - [x] Layout - - [ ] Add ports w/ labels onto the layout (for the subsequent LVS) - - [ ] DRC of the layout w/o error (Magic) - - [ ] DRC of the layout w/o error (Klayout) - - [ ] Create the baseline schematic of the created component - - [ ] LVS w/o error - - [ ] Document about the PCell specification - - [ ] PEX and create the testbench - - [ ] Verification gets passed \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py deleted file mode 100644 index 813e096a6..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/__init__.py +++ /dev/null @@ -1,4 +0,0 @@ -from glayout.flow.blocks.transmission_gate_saltychip.inv_lib import reconfig_inv -from glayout.flow.blocks.transmission_gate_saltychip.transmission_gate import tg_with_inv -from glayout.flow.blocks.transmission_gate_saltychip.cell_config import add_port_lvs -from glayout.flow.blocks.transmission_gate_saltychip.eval import main diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py deleted file mode 100644 index 5b9a59b20..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/comp_dc.py +++ /dev/null @@ -1,5 +0,0 @@ -def initialise(): - global inv_fet_width_base, tg_fet_width_base, tg_fet_width_factor - inv_fet_width_base = 3.0 - tg_fet_width_base = 3.0 - tg_fet_width_factor = tg_fet_width_base*4 \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py deleted file mode 100644 index 004737730..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/eval.py +++ /dev/null @@ -1,92 +0,0 @@ -import subprocess -#from glayout.flow.pdk.gf180_mapped import gf180 -from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 -import reconfig_inv as reconfig_inv -import transmission_gate as tg -import comp_dc - -TARGET_PDK = sky130 -PWD_OUTPUT = subprocess.run(['pwd'], capture_output=True, text=True) -GDS_DIR = PWD_OUTPUT.stdout.strip() + "/gds" -DRC_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/drc" -LVS_RPT_DIR = PWD_OUTPUT.stdout.strip() + "/regression/lvs" - -pmos_width = 12.0*1 -pmos_length = 0.15 -nmos_width = 12.0*1 -nmos_length = 0.15 - -def basic_tg_eval(): - tg_dut = tg.reconfig_tg( - pdk=TARGET_PDK, - component_name="tg", - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=True - ) - - tg_dut.show() - tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") - magic_drc_result = sky130.drc_magic( - layout=tg_dut, - design_name=tg_dut.name, - output_file=f"{DRC_RPT_DIR}/{tg_dut.name}_2_drc.rpt" - ) - print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) - print("--------------------------------------") - netgen_lvs_result = sky130.lvs_netgen( - layout=tg_dut, - design_name=tg_dut.name, - output_file_path=f"{LVS_RPT_DIR}/{tg_dut.name}_2_lvs.rpt", - copy_intermediate_files=True - ) - -def gate_ctrl_inv_eval(): - gate_ctrl_inv = reconfig_inv.reconfig_inv( - pdk=TARGET_PDK, - component_name="gate_ctrl_inv", - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=True - ) - gate_ctrl_inv.show() - gate_ctrl_inv.write_gds(f"{GDS_DIR}/{gate_ctrl_inv.name}.gds") - magic_drc_result = sky130.drc_magic( - layout=gate_ctrl_inv, - design_name=gate_ctrl_inv.name#, - #output_file=f"{absolute_path}/{gate_ctrl_inv.name}.rpt" - ) - print(f"Magic DRC result ({gate_ctrl_inv.name}): \n", magic_drc_result) - print("--------------------------------------") - -def tg_with_ctrl_eval(): - tg_dut = tg.tg_with_ctrl( - pdk=TARGET_PDK, - component_name="tg_with_ctrl", - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length - ) - tg_dut.show() - tg_dut.write_gds(f"{GDS_DIR}/{tg_dut.name}.gds") - magic_drc_result = sky130.drc_magic( - layout=tg_dut, - design_name=tg_dut.name#, - #output_file=f"{absolute_path}/{tg_dut.name}.rpt" - ) - print(f"Magic DRC result ({tg_dut.name}): \n", magic_drc_result) - print("--------------------------------------") - -def main(): - basic_tg_eval() - #gate_ctrl_inv_eval() - #tg_with_ctrl_eval() - -if __name__ == "__main__": - comp_dc.initialise() - main() \ No newline at end of file diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py deleted file mode 100644 index 0b87f2310..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/mimcap_array.py +++ /dev/null @@ -1,451 +0,0 @@ -# Primitives -from glayout.flow.primitives.mimcap import mimcap -from glayout.flow.primitives.mimcap import mimcap_array -from glayout.flow.primitives.via_gen import via_stack, via_array - -# Standard -from glayout.flow.pdk.mappedpdk import MappedPDK -from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 - -# gdsfactory -from gdsfactory import Component -from gdsfactory.cell import cell -from gdsfactory.components.rectangle import rectangle - -# Utility -from glayout.flow.pdk.util.comp_utils import evaluate_bbox, prec_center, prec_array, align_comp_to_port - -# Routing -from glayout.flow.routing.straight_route import straight_route -from glayout.flow.routing.c_route import c_route - -import copy - -def get_mimcap_layerconstruction_info(pdk: MappedPDK) -> tuple[str,str]: - """returns the glayer metal below and glayer metal above capmet - args: pdk - """ - capmettop = pdk.layer_to_glayer(pdk.get_grule("capmet")["capmettop"]) - capmetbottom = pdk.layer_to_glayer(pdk.get_grule("capmet")["capmetbottom"]) - pdk.has_required_glayers(["capmet",capmettop,capmetbottom]) - pdk.activate() - return capmettop, capmetbottom - -def create_6bit_dac_mimcap_array(pdk: MappedPDK): - """ - Creates a 6-bit DAC using an 8x8 MIM capacitor array with binary weighting. - """ - # Create the top-level component - dac_mim_cap = Component("6bit_DAC_MIMCAP_Array") - - ''' - # Define unit capacitor size (for example, 2x2 microns) - unit_size = [5.0, 5.0] - unit_mimcap = mimcap(pdk, size=unit_size) - - # Define bit weights for binary weighted capacitors - bit_weights = [32, 16, 8, 4, 2, 1] # From MSB to LSB - total_units = sum(bit_weights) - total_caps = 64 # 8x8 array - dummy_units = total_caps - total_units # Extra units as dummy - - # Generate common centroid indices for optimal matching - cap_indices = [(i, j) for i in range(8) for j in range(8)] - ''' - - # metal and via layers - met2 = pdk.get_glayer('met3') - met3_capmetbottom = pdk.get_glayer('met4') - met4_capmettop = pdk.get_glayer('met5') - via3 = pdk.get_glayer('via4') - mimcap_arr = Component("mimcap_arr") - #test_cap << rectangle(size=(1, 1), layer=via3) - mimcap_single_size = 5 - mimcap_single = mimcap(pdk, size=(mimcap_single_size,mimcap_single_size)) - rows_num = 8 - columns_num = 8 - mimcap_space = 10*pdk.get_grule("capmet")["min_separation"] - met4_width = pdk.get_grule("met5")["min_width"] - array_ref = mimcap_arr << prec_array(mimcap_single, rows=rows_num, columns=columns_num, spacing=2*[mimcap_space]) - mimcap_arr.add_ports(array_ref.get_ports_list()) - mim_metal_space = mimcap_space/9 - ##################### - port_pairs = list() - port_sides_pairs = list() - via_refs = list() - for rownum in range(rows_num): - for colnum in range(columns_num): - base_mimcap = f"row{rownum}_col{colnum}_" - right_mimcap = f"row{rownum}_col{colnum+1}_" - up_mimcap = f"row{rownum+1}_col{colnum}_" - capmetbottom = "met4" - capmettop = "met5" - - # Bottom Metal - level = "bottom_met_" - layer = capmetbottom - base_east_port = mimcap_arr.ports.get(base_mimcap+level+"E") - right_west_port = mimcap_arr.ports.get(right_mimcap+level+"W") - base_north_port = mimcap_arr.ports.get(base_mimcap+level+"N") - up_south_port = mimcap_arr.ports.get(up_mimcap+level+"S") - if rownum == rows_num-1 and colnum == columns_num-1: - pass #continue - elif rownum == rows_num-1: - port_pairs.append((base_east_port,right_west_port,layer)) - elif colnum == columns_num-1: - port_pairs.append((base_north_port,up_south_port,layer)) - else: - port_pairs.append((base_east_port,right_west_port,layer)) - port_pairs.append((base_north_port,up_south_port,layer)) - - # Top metal - level = "top_met_" - position_up = "up_" - position_down = "down_" - position_right = "right_" - position_left = "left_" - layer = capmettop - base_east_port = mimcap_arr.ports.get(base_mimcap+level+"E") - met4_distance_from_center = base_east_port.width/2 - pdk.get_grule(layer)["min_width"] - if base_east_port is not None: - base_east_port_up = base_east_port.copy() - base_east_port_up.name = base_mimcap+position_up+level+"E" - base_east_port_up.center[1] += met4_distance_from_center #(base_east_port_up.width/2 - pdk.get_grule(layer)["min_width"]) - base_east_port_up_space1 = base_east_port_up.copy() - base_east_port_up_space1.name = base_mimcap+position_up+level+"W" - base_east_port_up_space1.center[0] += mim_metal_space*1 - base_east_port_up_space4 = base_east_port_up.copy() - base_east_port_up_space4.name = base_mimcap+position_up+level+"W" - base_east_port_up_space4.center[0] += mim_metal_space*4 - base_east_port_down = base_east_port.copy() - base_east_port_down.name = base_mimcap+position_down+level+"E" - base_east_port_down.center[1] -= met4_distance_from_center #(base_north_port.width/2 - pdk.get_grule(layer)["min_width"]) - base_east_port_down_space1 = base_east_port_down.copy() - base_east_port_down_space1.name = base_mimcap+position_down+level+"W" - base_east_port_down_space1.center[0] += mim_metal_space*1 - base_east_port_down_space4 = base_east_port_down.copy() - base_east_port_down_space4.name = base_mimcap+position_down+level+"W" - base_east_port_down_space4.center[0] += mim_metal_space*4 - right_west_port = mimcap_arr.ports.get(right_mimcap+level+"W") - if right_west_port is not None: - right_west_port_up = right_west_port.copy() - right_west_port_up.name = right_mimcap+position_up+level+"W" - right_west_port_up.center[1] += met4_distance_from_center #(right_west_port_up.width/2 - pdk.get_grule(layer)["min_width"]) - right_west_port_up_space3 = right_west_port_up.copy() - right_west_port_up_space3.name = right_mimcap+position_up+level+"E" - right_west_port_up_space3.center[0] -= mim_metal_space*3 - right_west_port_up_space4 = right_west_port_up.copy() - right_west_port_up_space4.name = right_mimcap+position_up+level+"E" - right_west_port_up_space4.center[0] -= mim_metal_space*4 - right_west_port_up_space7 = right_west_port_up.copy() - right_west_port_up_space7.name = right_mimcap+position_up+level+"E" - right_west_port_up_space7.center[0] -= mim_metal_space*7 - right_west_port_down = right_west_port.copy() - right_west_port_down.name = right_mimcap+position_down+level+"W" - right_west_port_down.center[1] -= met4_distance_from_center #(right_west_port_down.width/2 - pdk.get_grule(layer)["min_width"]) - right_west_port_down_space3 = right_west_port_down.copy() - right_west_port_down_space3.name = right_mimcap+position_down+level+"E" - right_west_port_down_space3.center[0] -= mim_metal_space*3 - right_west_port_down_space4 = right_west_port_down.copy() - right_west_port_down_space4.name = right_mimcap+position_down+level+"E" - right_west_port_down_space4.center[0] -= mim_metal_space*4 - right_west_port_down_space7 = right_west_port_down.copy() - right_west_port_down_space7.name = right_mimcap+position_down+level+"E" - right_west_port_down_space7.center[0] -= mim_metal_space*7 - base_north_port = mimcap_arr.ports.get(base_mimcap+level+"N") - if base_north_port is not None: - base_north_port_right = base_north_port.copy() - base_north_port_right.name = base_mimcap+position_right+level+"N" - base_north_port_right.center[0] += met4_distance_from_center #(base_north_port_right.width/2 - pdk.get_grule(layer)["min_width"]) - base_north_port_right_space = base_north_port_right.copy() - base_north_port_right_space.name = base_mimcap+position_right+level+"S" - base_north_port_right_space.center[1] += mim_metal_space*4 - base_north_port_left = base_north_port.copy() - base_north_port_left.name = base_mimcap+position_left+level+"N" - base_north_port_left.center[0] -= met4_distance_from_center #(base_north_port_left.width/2 - pdk.get_grule(layer)["min_width"]) - base_north_port_left_space = base_north_port_left.copy() - base_north_port_left_space.name = base_mimcap+position_left+level+"S" - base_north_port_left_space.center[1] += mim_metal_space*4 - up_south_port = mimcap_arr.ports.get(up_mimcap+level+"S") - if up_south_port is not None: - up_south_port_right = up_south_port.copy() - up_south_port_right.name = base_mimcap+position_right+level+"S" - up_south_port_right.center[0] += met4_distance_from_center #(up_south_port_right.width/2 - pdk.get_grule(layer)["min_width"]) - up_south_port_right_space = up_south_port_right.copy() - up_south_port_right_space.name = base_mimcap+position_right+level+"N" - up_south_port_right_space.center[1] -= mim_metal_space*4 - up_south_port_left = up_south_port.copy() - up_south_port_left.name = base_mimcap+position_left+level+"S" - up_south_port_left.center[0] -= met4_distance_from_center #(up_south_port_left.width/2 - pdk.get_grule(layer)["min_width"]) - up_south_port_left_space = up_south_port_left.copy() - up_south_port_left_space.name = base_mimcap+position_left+level+"N" - up_south_port_left_space.center[1] -= mim_metal_space*4 - - ''' - if rownum in (0,1,2,4): - if colnum == 0: - base_west_side_port = mimcap_arr.ports.get(base_mimcap+level+"W") - base_west_side_port.name = base_mimcap+level+"westside_"+"W" - base_west_side_port.center - += met4_distance_from_center - else: - if colnum == 7: - ''' - - if rownum == 0: - # North and South - if colnum in (2,3,5,6): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (5,6): #(1,7) - port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) - via_mimcap = via_stack(pdk, "met3", capmettop) - #via_mimcap = via_array(pdk, "met3", capmettop, size=(met4_width,met4_width), num_vias=(2,2), fullbottom=False) - via_refs.append(align_comp_to_port(via_mimcap, right_west_port_up_space7, ("c", "c"))) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 1: - # North and South - if colnum in (1,2,4,5): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (0,2,3,5): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum in (1,6): #(1,7) - port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) - elif colnum == 4: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 2: - # North and South - if colnum in (0,1,2,3,4,5,7): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (4,5): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum in (0,6): #(1,7) - port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) - elif colnum == 3: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 3: - # North and South - if colnum in (0,1,2,3,5,6,7): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (0,1,2,3): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 4: - # North and South - if colnum in (0,2,3,4,5,6,7): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (2,3): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum in (5,6): #(1,7) - port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) - elif colnum == 4: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 5: - # North and South - if colnum in (2,3,5,6): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (2,3,6): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum == 1: #(1,7) - port_pairs.append((base_east_port_up,base_east_port_up_space1,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space1,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space7,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space7,layer)) - elif colnum == 0: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 6: - # North and South - if colnum in (1,2,4,5): - port_pairs.append((base_north_port_right,base_north_port_right_space,layer)) - port_pairs.append((base_north_port_left,base_north_port_left_space,layer)) - port_pairs.append((up_south_port_right,up_south_port_right_space,layer)) - port_pairs.append((up_south_port_left,up_south_port_left_space,layer)) - else: - port_pairs.append((base_north_port_left,up_south_port_left,layer)) - port_pairs.append((base_north_port_right,up_south_port_right,layer)) - # West and East - if colnum in (1,2,3,4,5,6): #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum == 0: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - elif rownum == 7: - # West and East - if colnum == 1: #(4,4) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space4,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space4,layer)) - elif colnum == 0: #(4,3) - port_pairs.append((base_east_port_up,base_east_port_up_space4,layer)) - port_pairs.append((base_east_port_down,base_east_port_down_space4,layer)) - port_pairs.append((right_west_port_up,right_west_port_up_space3,layer)) - port_pairs.append((right_west_port_down,right_west_port_down_space3,layer)) - elif colnum == columns_num-1: - pass #continue - else: - port_pairs.append((base_east_port_up,right_west_port_up,layer)) - port_pairs.append((base_east_port_down,right_west_port_down,layer)) - - # metal2 - layer = "met3" - base_east_port_metal2_up = mimcap_arr.ports.get(base_mimcap+level+"E") - base_east_port_metal2_up.name = base_mimcap+"east_metal2_up" - base_east_port_metal2_up.center[0] += mim_metal_space*3 - base_east_port_metal2_up.center[1] += (met4_distance_from_center + met4_width/2) - base_east_port_metal2_up.orientation = 270 - base_east_port_metal2_up.layer = met2 - base_east_port_metal2_down = base_east_port_metal2_up.copy() - base_east_port_metal2_down.name = base_mimcap+"east_metal2_down" - if colnum == 4: - base_east_port_metal2_down.center[1] -= (mimcap_single_size*15/2 + mimcap_space*8) - else: - base_east_port_metal2_down.center[1] -= (mimcap_single_size*17/2 + mimcap_space*8) - port_pairs.append((base_east_port_metal2_up,base_east_port_metal2_down,layer)) - base_west_port_metal2_up = mimcap_arr.ports.get(base_mimcap+level+"W") - base_west_port_metal2_up.name = base_mimcap+"west_metal2_up" - base_west_port_metal2_up.center[0] -= mim_metal_space*3 - base_west_port_metal2_up.center[1] += (met4_distance_from_center + met4_width/2) - base_west_port_metal2_up.orientation = 270 - base_west_port_metal2_up.layer = met2 - base_west_port_metal2_down = base_west_port_metal2_up.copy() - base_west_port_metal2_down.name = base_mimcap+"west_metal2_down" - if colnum in (1,2,6,7): - base_west_port_metal2_down.center[1] -= (mimcap_single_size*15/2 + mimcap_space*8) - else: - base_west_port_metal2_down.center[1] -= (mimcap_single_size*17/2 + mimcap_space*8) - port_pairs.append((base_west_port_metal2_up,base_west_port_metal2_down,layer)) - - for port_pair in port_pairs: - mimcap_arr << straight_route(pdk, port_pair[0], port_pair[1], width=met4_width) - for via_ref in via_refs: - mimcap_arr.add(via_refs) - - cap_ref = dac_mim_cap.add_ref(mimcap_arr) - #cap_ref.movey(-30) - - - return dac_mim_cap - - - -# Create and show the DAC MIM capacitor array layout -dac_mimcap_component = create_6bit_dac_mimcap_array(sky130).show() diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py b/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py deleted file mode 100755 index 97ab884af..000000000 --- a/openfasoc/generators/glayout/glayout/flow/blocks/transmission_gate_saltychip/reconfig_inv.py +++ /dev/null @@ -1,202 +0,0 @@ -from typing import ClassVar, Optional, Any, Union, Literal, Iterable, TypedDict -#from glayout.flow.pdk.gf180_mapped import gf180 -from glayout.flow.pdk.sky130_mapped import sky130_mapped_pdk as sky130 -from glayout.flow.pdk.mappedpdk import MappedPDK -from glayout.flow.pdk.util.comp_utils import prec_ref_center, movex, movey, evaluate_bbox, align_comp_to_port -from gdsfactory import Component -from gdsfactory.components import rectangle -from glayout.flow.primitives.fet import pmos -from glayout.flow.primitives.fet import nmos -from glayout.flow.routing.straight_route import straight_route -from glayout.flow.routing.c_route import c_route -from glayout.flow.routing.L_route import L_route -from glayout.flow.routing.smart_route import smart_route - -import comp_dc - -#@cell -def short_channel_inv( - pdk: MappedPDK, - component_name, - pmos_width, - pmos_length, - nmos_width, - nmos_length, - orientation, - add_pin: bool = True, # For LVS - **kwargs -) -> Component: - # Create a top level component - top_level = Component(component_name) - # To prepare one PMOS and one NMOS for the subsequent inverter cell construction - pfet = pmos(pdk=pdk, gate_rmult=2, with_substrate_tap=False, with_dummy=(False, True), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, gate_rmult=2, with_dnwell=False, with_substrate_tap=False, with_dummy=(True, False), width=nmos_width, length=nmos_length) - pfet.name="pmos" - nfet.name="nmos" - - # Instantiation of above PMOS and NMOS under the top level - pfet_ref = prec_ref_center(pfet) - nfet_ref = prec_ref_center(nfet) - top_level.add(pfet_ref) - top_level.add(nfet_ref) - - # Placement (relative move) - mos_spacing = pdk.util_max_metal_seperation(metal_levels=("met1", "met2", "met3", "met4", "met5")) - if(orientation=="horizontal"): - pfet_ref.rotate(90) - nfet_ref.rotate(90) - else: - pass - pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - - # Routing - top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_E"], glayer1="met2") # connected by li1 - input_route = top_level << straight_route(pdk, pfet_ref.ports["multiplier_0_gate_W"], nfet_ref.ports["multiplier_0_gate_W"] , glayer1="met2") # connected by li1 - - # To add the ports - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - - if add_pin == True: - # Add pins w/ labels for LVS - top_level.unlock() - pin_info = list() # list that contains all port and component information - met1_pin=(pdk.get_glayer("met1")[0], 20) - met1_label=(pdk.get_glayer("met1")[0], 5) - port_size = (0.24, 0.24) - # --- Port: A, i.e. input of the inverter - A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_E"), None)) - # --- Port: Y, i.e. output of the inverver - Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) - # --- Port: VDD - VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VDD_pin.add_label(text="VDD", layer=met1_label) - pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) - # --- Port: VSS - VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VSS_pin.add_label(text="VSS", layer=met1_label) - pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) - - # Move everythin to position - for comp, prt, alignment in pin_info: - alignment = ('c', 'b') if alignment is None else alignment - comp_ref = align_comp_to_port(comp, prt, alignment=alignment) - top_level.add(comp_ref) - - return top_level - -#@cell -def long_channel_inv( - pdk: MappedPDK, - component_name, - pmos_width, - pmos_length, - nmos_width, - nmos_length, - orientation_config: dict[str, Union[int, str]], - add_pin: bool = True, # For LVS - **kwargs -) -> Component: - # Create a top level component - top_level = Component(component_name) - # To prepare one PMOS and one NMOS for the subsequent inverter cell construction - pfet = pmos(pdk=pdk, gate_rmult=1, with_substrate_tap=False, with_dummy=(False, False), width=pmos_width, length=pmos_length) - nfet = nmos(pdk=pdk, gate_rmult=1, with_dnwell=False, with_substrate_tap=False, with_dummy=(False, False), width=nmos_width, length=nmos_length) - pfet.name="pmos" - nfet.name="nmos" - - # Instantiation of above PMOS and NMOS under the top level - pfet_ref = prec_ref_center(pfet) - nfet_ref = prec_ref_center(nfet) - top_level.add(pfet_ref) - top_level.add(nfet_ref) - - # Placement (relative move) - mos_spacing = pdk.util_max_metal_seperation(metal_levels=("met1", "met2", "met3", "met4", "met5")) - if orientation_config["pmos_degree"] != None: - pfet_ref.rotate(orientation_config["pmos_degree"]) - if orientation_config["nmos_degree"] != None: - nfet_ref.rotate(orientation_config["nmos_degree"]) - pfet_ref.movey(evaluate_bbox(nfet)[1] + mos_spacing) - - # Routing - top_level << c_route(pdk, pfet_ref.ports["multiplier_0_drain_E"], nfet_ref.ports["multiplier_0_drain_W"], cglayer="met3") # connected by li1 - top_level << smart_route(pdk, pfet_ref.ports["multiplier_0_gate_S"], nfet_ref.ports["multiplier_0_gate_S"]) # connected by li1 - - # To add the ports - top_level.add_ports(pfet_ref.get_ports_list(), prefix="pmos_") - top_level.add_ports(nfet_ref.get_ports_list(), prefix="nmos_") - - if add_pin == True: - # Add pins w/ labels for LVS - top_level.unlock() - pin_info = list() # list that contains all port and component information - met1_pin=(pdk.get_glayer("met1")[0], 20) - met1_label=(pdk.get_glayer("met1")[0], 5) - port_size = (0.24, 0.24) - # --- Port: A, i.e. input of the inverter - A_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - A_pin.add_label(text="A", layer=met1_label) - pin_info.append((A_pin, top_level.ports.get(f"nmos_gate_S"), None)) - # --- Port: Y, i.e. output of the inverver - Y_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - Y_pin.add_label(text="Y", layer=met1_label) - pin_info.append((Y_pin, top_level.ports.get(f"nmos_drain_E"), None)) - # --- Port: VDD - VDD_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VDD_pin.add_label(text="VDD", layer=met1_label) - pin_info.append((VDD_pin, top_level.ports.get(f"pmos_drain_E"), None)) - # --- Port: VSS - VSS_pin=rectangle(layer=met1_pin, size=port_size, centered=True).copy() - VSS_pin.add_label(text="VSS", layer=met1_label) - pin_info.append((VSS_pin, top_level.ports.get(f"nmos_source_W"), ('r', 't'))) - - # Move everythin to position - for comp, prt, alignment in pin_info: - alignment = ('c', 'b') if alignment is None else alignment - comp_ref = align_comp_to_port(comp, prt, alignment=alignment) - top_level.add(comp_ref) - - return top_level - -#@cell -def reconfig_inv( - pdk, - component_name, - pmos_width, - pmos_length, - nmos_width, - nmos_length, - add_pin: bool = True, # For LVS - **kwargs -) -> Component: - if pmos_width != nmos_width: - raise ValueError("PCell constraint: the widths of PMOS and NMOS must be identical") - elif pmos_width >= comp_dc.inv_fet_width_base: # Long-channel PMOS and NMOS - inv = long_channel_inv( - pdk=pdk, - component_name=component_name, - orientation_config={"pmos_degree":0, "nmos_degree":180}, - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=True - ) - else: # Short-channel PMOS and NMOS - inv = short_channel_inv( - pdk=pdk, - component_name=component_name, - orientation="horizontal", - pmos_width=pmos_width, - pmos_length=pmos_length, - nmos_width=nmos_width, - nmos_length=nmos_length, - add_pin=True - ) - - return inv \ No newline at end of file