From 01912475d40bfd5156a95a6bd14d40f68756f732 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Wed, 21 Aug 2024 09:40:30 -0700 Subject: [PATCH] SRF: Release v1.05 event files This commit releases SRF v1.05 events and updates mapfile.csv accordingly. --- SRF/events/sierraforest_core.json | 10 +- SRF/events/sierraforest_uncore.json | 78 ++- .../sierraforest_uncore_experimental.json | 510 +++++++++++++++--- mapfile.csv | 6 +- 4 files changed, 518 insertions(+), 86 deletions(-) diff --git a/SRF/events/sierraforest_core.json b/SRF/events/sierraforest_core.json index ea1635ee..570cb0cd 100644 --- a/SRF/events/sierraforest_core.json +++ b/SRF/events/sierraforest_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.04", - "DatePublished": "05/14/2024", - "Version": "1.04", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.05", + "DatePublished": "08/14/2024", + "Version": "1.05", "Legend": "" }, "Events": [ @@ -3183,8 +3183,8 @@ "EventCode": "0xcd", "UMask": "0x03", "EventName": "ARITH.DIV_ACTIVE", - "BriefDescription": "Counts the number of cycles when any of the dividers are active.", - "PublicDescription": "Counts the number of cycles when any of the dividers are active.", + "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", diff --git a/SRF/events/sierraforest_uncore.json b/SRF/events/sierraforest_uncore.json index da3292eb..c150bef9 100644 --- a/SRF/events/sierraforest_uncore.json +++ b/SRF/events/sierraforest_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.04", - "DatePublished": "05/14/2024", - "Version": "1.04", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.05", + "DatePublished": "08/14/2024", + "Version": "1.05", "Legend": "" }, "Events": [ @@ -2023,6 +2023,42 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "BriefDescription": "TOR Occupancy for Data read opt from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "CHA", "EventCode": "0x36", @@ -2059,6 +2095,42 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "CHA", "EventCode": "0x36", diff --git a/SRF/events/sierraforest_uncore_experimental.json b/SRF/events/sierraforest_uncore_experimental.json index 3ba07c64..0f1de18d 100644 --- a/SRF/events/sierraforest_uncore_experimental.json +++ b/SRF/events/sierraforest_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.04", - "DatePublished": "05/14/2024", - "Version": "1.04", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.05", + "DatePublished": "08/14/2024", + "Version": "1.05", "Legend": "" }, "Events": [ @@ -2257,78 +2257,6 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, - { - "Unit": "CHA", - "EventCode": "0x36", - "UMask": "0x01", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00C827FD", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", - "BriefDescription": "TOR Occupancy for Data read opt from local IA that hit the cache", - "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", - "Counter": "0", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0", - "CounterType": "PGMABLE" - }, - { - "Unit": "CHA", - "EventCode": "0x36", - "UMask": "0x01", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00C8A7FD", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", - "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", - "Counter": "0", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0", - "CounterType": "PGMABLE" - }, - { - "Unit": "CHA", - "EventCode": "0x36", - "UMask": "0x01", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00C827FE", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", - "BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache", - "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", - "Counter": "0", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0", - "CounterType": "PGMABLE" - }, - { - "Unit": "CHA", - "EventCode": "0x36", - "UMask": "0x01", - "PortMask": "0x00", - "FCMask": "0x00", - "UMaskExt": "0x00C8A7FE", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", - "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", - "Counter": "0", - "ELLC": "0", - "Filter": "na", - "ExtSel": "0", - "Deprecated": "0", - "FILTER_VALUE": "0", - "CounterType": "PGMABLE" - }, { "Unit": "CHA", "EventCode": "0x36", @@ -4759,6 +4687,240 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "UPI LL", + "EventCode": "0x27", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "BriefDescription": "Cycles in L0p", + "PublicDescription": "Cycles in L0p", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x28", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PublicDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x29", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PublicDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x04", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x05", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "BriefDescription": "Power Strongest Upper Limit Cycles", + "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x74", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "BriefDescription": "Cycles spent changing Frequency", + "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x2b", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "BriefDescription": "Package C State Residency - C2E", + "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x2d", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "BriefDescription": "Package C State Residency - C6", + "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x35", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "BriefDescription": "Number of cores in C0", + "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x36", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3", + "BriefDescription": "Number of cores in C3", + "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x37", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "BriefDescription": "Number of cores in C6", + "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x0a", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "BriefDescription": "External Prochot", + "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x09", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "BriefDescription": "Internal Prochot", + "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "B2CMI", "EventCode": "0x17", @@ -6307,6 +6469,186 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK0", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK1", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK2", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK3", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK0", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK1", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK2", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x47", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK3", + "BriefDescription": "# of cycles a given rank is in Power Down Mode", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x88", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_POWER_CHANNEL_PPD_CYCLES", + "BriefDescription": "# of cycles a given rank is in Power Down Mode and all pages are closed", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x43", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS_CYCLES", + "BriefDescription": "# of cycles all ranks were in SR", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "IIO", "EventCode": "0x42", @@ -6757,6 +7099,24 @@ "FILTER_VALUE": "0", "CounterType": "PGMABLE" }, + { + "Unit": "IMC", + "EventCode": "0x43", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS", + "BriefDescription": "subevent0 - # of cycles all ranks were in SR subevent1 - # of times all ranks went into SR subevent2 -# of times ps_sr_active asserted (SRE) subevent3 - # of times ps_sr_active deasserted (SRX) subevent4 - # of times PS-&>Refresh ps_sr_req asserted (SRE) subevent5 - # of times PS-&>Refresh ps_sr_req deasserted (SRX) subevent6 - # of cycles PSCtrlr FSM was in FATAL", + "PublicDescription": "UNC_M_SELF_REFRESH.ENTER_SUCCESS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, { "Unit": "CHA", "EventCode": "0x36", diff --git a/mapfile.csv b/mapfile.csv index 8bb99691..150c1664 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -196,9 +196,9 @@ GenuineIntel-6-AE,V1.03,/GNR/events/graniterapids_core.json,core,,, GenuineIntel-6-AE,V1.03,/GNR/events/graniterapids_uncore.json,uncore,,, GenuineIntel-6-AE,V1.03,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AE,V0,/GNR/metrics/graniterapids_metrics.json,metrics,,, -GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_core.json,core,,, -GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_uncore.json,uncore,,, -GenuineIntel-6-AF,V1.04,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AF,V1.05,/SRF/events/sierraforest_core.json,core,,, +GenuineIntel-6-AF,V1.05,/SRF/events/sierraforest_uncore.json,uncore,,, +GenuineIntel-6-AF,V1.05,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AF,V0,/SRF/metrics/sierraforest_metrics.json,metrics,,, GenuineIntel-6-B6,V1.04,/GRR/events/grandridge_core.json,core,,, GenuineIntel-6-B6,V1.04,/GRR/events/grandridge_uncore.json,uncore,,,