diff --git a/doc/user_guide/_docs/A01-sample-example.md b/doc/user_guide/_docs/A01-sample-example.md
index 40239b4da..ff97f6d22 100644
--- a/doc/user_guide/_docs/A01-sample-example.md
+++ b/doc/user_guide/_docs/A01-sample-example.md
@@ -16,43 +16,27 @@ To get a quick feel for what ROHD looks like, below is an example of what a simp
 // Import the ROHD package
 import 'package:rohd/rohd.dart';
 
-// Define a class Counter that extends ROHD's abstract Module class
+// Define a class Counter that extends ROHD's abstract Module class.
 class Counter extends Module {
-
-  // For convenience, map interesting outputs to 
-  // short variable names for consumers of this module
+  // For convenience, map interesting outputs to short variable names for
+  // consumers of this module.
   Logic get val => output('val');
 
-  // This counter supports any width, determined at run-time
+  // This counter supports any width, determined at run-time.
   final int width;
-  Counter(Logic en, Logic reset, Logic clk, {this.width=8, String name='counter'}) 
-      : super(name: name) {
+
+  Counter(Logic en, Logic reset, Logic clk,
+      {this.width = 8, super.name = 'counter'}) {
     // Register inputs and outputs of the module in the constructor.
-    // Module logic must consume registered inputs and output to registered outputs.
-    en    = addInput('en', en);
+    // Module logic must consume registered inputs and output to registered
+    // outputs.
+    en = addInput('en', en);
     reset = addInput('reset', reset);
-    clk   = addInput('clk', clk);
+    clk = addInput('clk', clk);
+    addOutput('val', width: width);
 
-    var val = addOutput('val', width: width);
-
-    // A local signal named 'nextVal'
-    var nextVal = Logic(name: 'nextVal', width: width);
-    
-    // Assignment statement of nextVal to be val+1 (<= is the assignment operator)
-    nextVal <= val + 1;
-
-    // `Sequential` is like SystemVerilog's always_ff, 
-    // in this case trigger on the positive edge of clk
-    Sequential(clk, [
-      // `If` is a conditional if statement, 
-      // like `if` in SystemVerilog always blocks
-      If(reset, then:[
-        // the '<' operator is a conditional assignment
-        val < 0
-      ], orElse: [If(en, then: [
-        val < nextVal
-      ])])
-    ]);
+    // We can use the `flop` function to automate creation of a `Sequential`.
+    val <= flop(clk, reset: reset, en: en, val + 1);
   }
 }
 
diff --git a/doc/user_guide/_docs/B02-comparisons-with-alternatives.md b/doc/user_guide/_docs/B02-comparisons-with-alternatives.md
index 8a7ef2178..ca98fd2eb 100644
--- a/doc/user_guide/_docs/B02-comparisons-with-alternatives.md
+++ b/doc/user_guide/_docs/B02-comparisons-with-alternatives.md
@@ -64,8 +64,8 @@ There are a number of other attempts to make HLS better, including [XLS](https:/
 
 Transaction Level Verilog (TL-Verilog) is like an extension on top of SystemVerilog that makes pipelining simpler and more concise.
 
-- TL-Verilog makes RTL design easier, but doesn't really add much in terms of verification
-- Abstraction of pipelining is something that could be achievable with ROHD, but is not (yet) implemented in base ROHD.
+- TL-Verilog makes RTL design easier, especially when pipelining, but doesn't really add much in terms of verification
+- ROHD also supports a [pipelining abstraction](https://intel.github.io/rohd-website/docs/pipelines/).
 
 Read more about TL-Verilog here: <https://www.redwoodeda.com/tl-verilog>
 
diff --git a/doc/user_guide/_get-started/01-overview.md b/doc/user_guide/_get-started/01-overview.md
index 830f45a99..0481708e5 100644
--- a/doc/user_guide/_get-started/01-overview.md
+++ b/doc/user_guide/_get-started/01-overview.md
@@ -42,7 +42,7 @@ One of ROHD's goals is to help grow an open-source community around reusable har
 
 Dart is a modern, relatively new language developed by Google.  It is designed with client-side application development in mind (e.g. apps and websites), but also has great performance for general tasks.  It adopts some of the most loved syntax and features from languages like C++, Java, C#, JavaScript/TypeScript, and Kotlin.  Dart is extremely user-friendly, fun to use, and **easy to learn**.  The excellent, fast static analysis with a modern IDE with autocomplete makes it easy to learn as you work.  Dart has a lot of great modern language features, including null safety.
 
-Because it is designed with asynchronous requests in mind (i.e. sending a request to a server and not freezing the application while it waits for a response), Dart has async/await and `Future`s built in, with concurrent programming using *isolates*.  These constructs enable code to execute in parallel without multithreading.  These chacteristics make modelling hardware very easy.
+Because it is designed with asynchronous requests in mind (i.e. sending a request to a server and not freezing the application while it waits for a response), Dart has `async`/`await` and `Future`s built in, with [concurrent programming](https://dart.dev/language/concurrency).  These constructs enable code to execute in parallel without multithreading.  These chacteristics make modelling hardware very easy.
 
 Dart can compile to native machine code, but also includes its own high-performance VM and a JIT compiler.  During development, you can use a feature called "hot reload" to change code while the program is actively executing.