-
Notifications
You must be signed in to change notification settings - Fork 3
/
fifo_sync_late.v
126 lines (102 loc) · 2.58 KB
/
fifo_sync_late.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
// A parameterized FIFO
// One flop delay between re and rd_data/ne.
// Two flop delay from wr_data to rd_data, which is due to
// the ram.
module fifo_sync_late
(
clk,
reset_l,
wr_data, // Write data
we, // Write enable
ns_full,
full, // Almost full
ovf, // Overflow FATAL error (FIFO is broken once this is set)
rd_data, // Read data registered
re, // Read enable
ne, // Not empty
unf // Underflow FATAL error (FIFO is broken once this is set)
);
parameter
ADDRWIDTH = 5, // Address width: FIFO will have 2^ADDRWIDTH words
DATAWIDTH = 18, // Data width
SLOP = 4; // No. words between full and overflow
input clk;
input reset_l;
input [DATAWIDTH-1:0] wr_data; // Write data
input we; // Write enable
output ns_full;
reg ns_full;
output full; // Almost full
reg full;
output ovf; // Overflow FATAL error (FIFO is broken once this is set)
reg ovf;
output [DATAWIDTH-1:0] rd_data; // Read data registered
input re; // Read enable
output ne; // Not empty
reg ne;
output unf; // Underflow FATAL error (FIFO is broken once this is set)
reg unf;
reg [ADDRWIDTH-1:0] rd_addr, ns_rd_addr; // Points to oldest data
reg [ADDRWIDTH-1:0] wr_addr, ns_wr_addr;
reg [ADDRWIDTH:0] count, ns_count; // No. words in FIFO
ram_dp #(.DATAWIDTH(DATAWIDTH), .ADDRWIDTH(ADDRWIDTH)) ram
(
.clk (clk),
.wr_data (wr_data),
.wr_addr (wr_addr),
.we (we),
.rd_data (rd_data),
.rd_addr (ns_rd_addr)
);
// State machine
reg we_d; // Delay assertion of ne after we because ram has 2 cycle delay
always @(posedge clk or negedge reset_l)
if (!reset_l)
begin
rd_addr <= 0;
count <= 0;
ovf <= 0;
unf <= 0;
full <= 0;
wr_addr <= 0;
we_d <= 0;
end
else
begin
we_d <= we;
wr_addr <= ns_wr_addr;
rd_addr <= ns_rd_addr;
count <= ns_count;
full <= ns_full;
// Don't care about latency of these flags
if (re && !ne)
begin
unf <= 1;
$display("%m FIFO underflow error");
$finish;
end
if (we_d && (count == (1 << ADDRWIDTH)))
begin
ovf <= 1;
$display("%m FIFO overflow error");
$finish;
end
end
// Read side state
always @(*)
begin
ns_rd_addr = rd_addr;
ns_wr_addr = wr_addr;
ns_count = count;
if (re)
ns_rd_addr = ns_rd_addr + 1'd1;
if (we)
ns_wr_addr = ns_wr_addr + 1'd1;
if (we_d && !re)
ns_count = ns_count + 1'd1;
else if (re && !we_d)
ns_count = ns_count - 1'd1;
ns_full = (ns_count >= (1 << ADDRWIDTH) - SLOP);
ne = (count != 0);
end
endmodule