From 6dd88f8ee1fe2f6dd0d70c7661150360e8598c73 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 9 Feb 2024 11:40:51 -0500 Subject: [PATCH] [LowerToHW] Fix shr(0-bit, n) lowering (#6683) Fix an error if a 0-bit was shifted right by any amount and this made it all the way to LowerToHW (and wasn't canonicalized away earlier). FIRRTL semantics interpret this case as a 1-bit zero. Insert the 1-bit zero if we ever see this. Fixes #6652. Signed-off-by: Schuyler Eldridge --- lib/Conversion/FIRRTLToHW/LowerToHW.cpp | 4 ++++ test/Conversion/FIRRTLToHW/zero-width.mlir | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp index 79b781d61c0d..b7b708da2a14 100644 --- a/lib/Conversion/FIRRTLToHW/LowerToHW.cpp +++ b/lib/Conversion/FIRRTLToHW/LowerToHW.cpp @@ -3748,6 +3748,10 @@ LogicalResult FIRRTLLowering::visitExpr(ShlPrimOp op) { } LogicalResult FIRRTLLowering::visitExpr(ShrPrimOp op) { + // If this is a 0-bit value shifted by any amount, then return a 1-bit zero. + if (isZeroBitFIRRTLType(op.getInput().getType())) + return setLowering(op, getOrCreateIntConstant(1, 0)); + auto input = getLoweredValue(op.getInput()); if (!input) return failure(); diff --git a/test/Conversion/FIRRTLToHW/zero-width.mlir b/test/Conversion/FIRRTLToHW/zero-width.mlir index 080f041efd40..2e7b1c5807e3 100644 --- a/test/Conversion/FIRRTLToHW/zero-width.mlir +++ b/test/Conversion/FIRRTLToHW/zero-width.mlir @@ -79,4 +79,14 @@ firrtl.circuit "Arithmetic" { // CHECK-NEXT: hw.output } + // Check that a zero-width value shifted right produces a zero. + // See: https://github.com/llvm/circt/issues/6652 + // CHECK-LABEL: hw.module @ShrZW + firrtl.module @ShrZW(in %x: !firrtl.uint<0>, out %out: !firrtl.uint<1>) attributes {convention = #firrtl} { + %0 = firrtl.shr %x, 5 : (!firrtl.uint<0>) -> !firrtl.uint<1> + firrtl.connect %out, %0 : !firrtl.uint<1>, !firrtl.uint<1> + // CHECK: %[[false:.+]] = hw.constant false + // CHECK-NEXT: hw.output %false + } + }