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[Calyx] Switch sequential memories to be true single port memories #23845

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[Calyx] Switch sequential memories to be true single port memories

[Calyx] Switch sequential memories to be true single port memories #23845

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Build and Test (clang, clang++, debug, ON, ON)

Build and Test (clang, clang++, debug, ON, ON)
succeeded Feb 28, 2024 in 7m 17s