From 918f00407d31a19b3a1a957f5803b7888bb4ede0 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen@sifive.com>
Date: Mon, 20 May 2024 20:04:08 -0700
Subject: [PATCH] Update option and option desc

---
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 3388a21bd5ca31..d9f8222669cab3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -97,8 +97,9 @@ static cl::opt<bool> EnableMISchedLoadClustering(
     cl::init(false));
 
 static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
-    "riscv-vsetvli-after-rvv-regalloc", cl::Hidden,
-    cl::desc("vsetvl insertion after rvv regalloc"), cl::init(true));
+    "riscv-vsetvl-after-rvv-regalloc", cl::Hidden,
+    cl::desc("Insert vsetvls after vector register allocation"),
+    cl::init(true));
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());