From c4a252c218f9235f60f8b50c1bd27fb28015d65b Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Mon, 22 Apr 2024 15:56:42 +0800
Subject: [PATCH] Add implicit VL use

---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 6bc31416faa226..6e7f9316568737 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1541,6 +1541,8 @@ void RISCVInsertVSETVLI::convertToX0X0(MachineBasicBlock &MBB) {
         MI.getOperand(0).setIsDead(true);
         MI.getOperand(1).ChangeToRegister(RISCV::X0, /*isDef*/ false);
         MI.getOperand(1).setIsKill(true);
+        MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
+                                                /*isImp*/ true));
         Info = MIInfo; // transferAfter can't handle x0,x0
         continue;
       }