From e778cea1cd3766a2c1dbef7f83cef994df0a8a80 Mon Sep 17 00:00:00 2001
From: Jorge Botto <jorge.botto.16@ucl.ac.uk>
Date: Tue, 6 Aug 2024 23:33:03 +0100
Subject: [PATCH] Fixing miscompilation

---
 .../Transforms/InstCombine/InstCombineSimplifyDemanded.cpp    | 4 ++++
 llvm/test/Transforms/InstCombine/pr98435.ll                   | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index c494fec84c1e6e..f8f52e25874d69 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1740,9 +1740,13 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
         Constant *CElt = CV->getAggregateElement(i);
         if (isa<ConstantExpr>(CElt))
           continue;
+
         // TODO: If a select condition element is undef, we can demand from
         // either side. If one side is known undef, choosing that side would
         // propagate undef.
+        if (isa<UndefValue>(CElt))
+          continue;
+
         if (CElt->isNullValue())
           DemandedLHS.clearBit(i);
         else
diff --git a/llvm/test/Transforms/InstCombine/pr98435.ll b/llvm/test/Transforms/InstCombine/pr98435.ll
index dd92b4c405b392..e8793c4f3c8f37 100644
--- a/llvm/test/Transforms/InstCombine/pr98435.ll
+++ b/llvm/test/Transforms/InstCombine/pr98435.ll
@@ -4,7 +4,8 @@
 define <2 x i1> @pr98435(<2 x i1> %val0) {
 ; CHECK-LABEL: define <2 x i1> @pr98435(
 ; CHECK-SAME: <2 x i1> [[VAL0:%.*]]) {
-; CHECK-NEXT:    ret <2 x i1> <i1 poison, i1 true>
+; CHECK-NEXT:    [[VAL3:%.*]] = select <2 x i1> <i1 undef, i1 true>, <2 x i1> <i1 true, i1 true>, <2 x i1> [[VAL0]]
+; CHECK-NEXT:    ret <2 x i1> [[VAL3]]
 ;
   %val3 = select <2 x i1> <i1 undef, i1 true>, <2 x i1> <i1 true, i1 true>, <2 x i1> %val0
   ret <2 x i1> %val3