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[X86] Assertion failure in X86 shuffle combine #51200

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nikic opened this issue Sep 14, 2021 · 2 comments
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[X86] Assertion failure in X86 shuffle combine #51200

nikic opened this issue Sep 14, 2021 · 2 comments
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backend:X86 bugzilla Issues migrated from bugzilla

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@nikic
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nikic commented Sep 14, 2021

Bugzilla Link 51858
Resolution FIXED
Resolved on Sep 20, 2021 11:25
Version trunk
OS Linux
Blocks #50580
CC @topperc,@RKSimon,@phoebewang,@rotateright,@tstellar
Fixed by commit(s) dcba994 b96ee8f

Extended Description

define i8 @​test(i128 %arg) {
%vec = bitcast i128 %arg to <16 x i8>
%red = tail call i8 @​llvm.vector.reduce.mul.v16i8(<16 x i8> %vec)
ret i8 %red
}

declare i8 @​llvm.vector.reduce.mul.v16i8(<16 x i8>)

Not a vector MVT!
UNREACHABLE executed at /home/nikic/llvm-project/llvm/include/llvm/Support/MachineValueType.h:686!
[...]
#​6 0x0000559214dc715c combineX86ShuffleChain(llvm::ArrayRefllvm::SDValue, llvm::SDValue, llvm::ArrayRef, int, bool, bool, bool, llvm::SelectionDAG&, llvm::X86Subtarget const&) X86ISelLowering.cpp:0:0
#​7 0x0000559214e1cbbf combineX86ShufflesRecursively(llvm::ArrayRefllvm::SDValue, int, llvm::SDValue, llvm::ArrayRef, llvm::ArrayRef<llvm::SDNode const*>, unsigned int, unsigned int, bool, bool, bool, llvm::SelectionDAG&, llvm::X86Subtarget const&) X86ISelLowering.cpp:0:0
#​8 0x0000559214e27181 combineX86ShufflesRecursively(llvm::SDValue, llvm::SelectionDAG&, llvm::X86Subtarget const&) (.constprop.0) X86ISelLowering.cpp:0:0
#​9 0x0000559214e2aceb combineEXTEND_VECTOR_INREG(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) X86ISelLowering.cpp:0:0

Note that the vector.reduce.mul is expanded in IR, so the actual input is this:

define i8 @​test(i128 %arg) {
%vec = bitcast i128 %arg to <16 x i8>
%rdx.shuf = shufflevector <16 x i8> %vec, <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx = mul <16 x i8> %vec, %rdx.shuf
%rdx.shuf1 = shufflevector <16 x i8> %bin.rdx, <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx2 = mul <16 x i8> %bin.rdx, %rdx.shuf1
%rdx.shuf3 = shufflevector <16 x i8> %bin.rdx2, <16 x i8> poison, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx4 = mul <16 x i8> %bin.rdx2, %rdx.shuf3
%rdx.shuf5 = shufflevector <16 x i8> %bin.rdx4, <16 x i8> poison, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%bin.rdx6 = mul <16 x i8> %bin.rdx4, %rdx.shuf5
%1 = extractelement <16 x i8> %bin.rdx6, i32 0
ret i8 %1
}

@nikic
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nikic commented Sep 14, 2021

assigned to @RKSimon

@tstellar
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Merged: b96ee8f

@llvmbot llvmbot transferred this issue from llvm/llvm-bugzilla-archive Dec 11, 2021
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