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Issues list

[AVX-512] vmovdqu8 {k} + vmovdqa => vpblendmb backend:X86
#114743 opened Nov 4, 2024 by Validark
3
[AVX-512] Decompose vpermb into broadcast+vpshufb when possible backend:X86
#114001 opened Oct 29, 2024 by Validark
@RKSimon
6
Add llvm.experimental.expand new issue
#113422 opened Oct 23, 2024 by Validark
[PPC PWR10] Bit extraction opts to use expensive vector code backend:PowerPC
#113352 opened Oct 22, 2024 by Validark
1
Aggressive instruction re-ordering introduces register spilling llvm:optimizations
#113275 opened Oct 22, 2024 by Validark
[AVX-512] Only qword ptr and zmmword ptr dereferences are folded into vpand? backend:X86
#113262 opened Oct 22, 2024 by Validark
6
[BMI2] Interleaving bitstrings should compile to pdeps backend:X86
#111433 opened Oct 7, 2024 by Validark
3
[x86-64] Work done in vectors shouldn't round-trip to general-purpose registers just to do one subtraction (bitReverse(bitReverse(a) - bitReverse(b))) backend:X86
#111046 opened Oct 3, 2024 by Validark
1
[AVX-512] Don't fold vectorized byte shift into vgf2p8affineqb when the results are going to be ANDed later anyway backend:X86
#110846 opened Oct 2, 2024 by Validark
3
[AVX] Offset pointers to constant memory shouldn't be broadcast into a vector differently than other constants backend:X86
#110839 opened Oct 2, 2024 by Validark
1
[AVX-512] Moving from a GPR to a k-register just to spill to memory should just spill via mov, or just stay in a k-register backend:X86
#110626 opened Oct 1, 2024 by Validark
1
[AVX512] Prefer to do work in k-registers instead of always moving over to general purpose registers backend:X86 missed-optimization
#110426 opened Sep 29, 2024 by Validark
3
[AVX-512] clz(32 x u8) and clz(64 x u8) should use an algorithm similar to avx2 backend:X86
#110308 opened Sep 27, 2024 by Validark
3
[x86][znver3] Dead 32-byte constant accessed via vbroadcasti128 not eliminated from assembly backend:X86 missed-optimization
#110305 opened Sep 27, 2024 by Validark
1
[AVX2] vpsllvq builtin-semantics are not recognized by LLVM vectors backend:X86 llvm:instcombine missed-optimization
#109888 opened Sep 25, 2024 by Validark
1
@RKSimon
3
[Aarch64] clz on a vector of 2 x u64 should be better optimized backend:AArch64 missed-optimization
#109122 opened Sep 18, 2024 by Validark
1
Don't hoist NOT's out of loop that will be folded into ANDN/ORN anyway (except sometimes on Arm) backend:AArch64 backend:RISC-V backend:X86 missed-optimization
#108840 opened Sep 16, 2024 by Validark
3
Simple bit manipulation resulting in disjoint set could be tracked llvm:optimizations missed-optimization
#108829 opened Sep 16, 2024 by Validark
4
[Aarch64] bitcast i16 to <16 x i1> + sext <16 x i1> to <16 x i8> should not go bit-by-bit backend:AArch64
#107700 opened Sep 7, 2024 by Validark
5
[Aarch64] Bad register scheduling (bsl -> st4 might have to do with it?) backend:AArch64
#107438 opened Sep 5, 2024 by Validark
1
Failure to optimize away adding a vector of zeroes llvm:SelectionDAG SelectionDAGISel as well missed-optimization
#107423 opened Sep 5, 2024 by Validark
@RKSimon
4
[AArch64][X86] Shift by a multiple of 8 on a i128 could turn into a vector shift backend:AArch64 backend:X86 missed-optimization
#107289 opened Sep 4, 2024 by Validark
4
[Aarch64] Various idioms equivalent to a simple vector shl or shr should be optimized backend:AArch64 missed-optimization
#107287 opened Sep 4, 2024 by Validark
1
[Aarch64] Vector constant that could use u16-dup is loaded from memory instead backend:AArch64 missed-optimization
#107243 opened Sep 4, 2024 by Validark
1
[Aarch64] Missed st3 and st4 emit backend:AArch64
#107099 opened Sep 3, 2024 by Validark
2
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