From d4992fd9ad21e4b9940c3e88f96780796ed9ec2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 15:52:17 +0800 Subject: [PATCH 01/16] [HDL] Add a multi-mode ff which can support posedge and negedge --- .../openfpga_cell_library/verilog/dff.v | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 9413ee2c7..2b3f88a5e 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -294,6 +294,33 @@ DFFRQ FF_CORE (.RST(post_rst), endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +// - clock +// which can be switched between positive edge triggered and negative edge triggered +//----------------------------------------------------- +module MULTI_MODE_DFFRCKQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_rst = mode[0] ? ~RST : RST; +wire post_clk = mode[1] ? ~CK : CK; + +DFFRQ FF_CORE (.RST(post_rst), + .CK(post_clk), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset From c8ff3fc8dc634eb7962565fefb3dd67d1cb9973f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:00:51 +0800 Subject: [PATCH 02/16] [test] add regression test to validate compilation of openfpga cell library files --- openfpga_flow/openfpga_cell_library/Makefile | 29 +++++++++++++++++++ .../openfpga_cell_library/verilog_sources.f | 23 +++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 openfpga_flow/openfpga_cell_library/Makefile create mode 100644 openfpga_flow/openfpga_cell_library/verilog_sources.f diff --git a/openfpga_flow/openfpga_cell_library/Makefile b/openfpga_flow/openfpga_cell_library/Makefile new file mode 100644 index 000000000..883aace7b --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/Makefile @@ -0,0 +1,29 @@ +# +# OpenFPGA cell library Makefile +# ============================== +# +# Check correctness of the cell library files + +SHELL = bash +PYTHON_EXEC ?= python3 + +# Put it first so that "make" without argument is like "make help". +export COMMENT_EXTRACT + +# Put it first so that "make" without argument is like "make help". +help: + @${PYTHON_EXEC} -c "$$COMMENT_EXTRACT" + +compile_verilog: +# This command checks the compile compatibility of Verilog files + for f in `cat verilog_sources.f`; do iverilog $$f; done + +# Functions to extract comments from Makefiles +define COMMENT_EXTRACT +import re +with open ('Makefile', 'r' ) as f: + matches = re.finditer('^([a-zA-Z-_]*):.*\n#(.*)', f.read(), flags=re.M) + for _, match in enumerate(matches, start=1): + header, content = match[1], match[2] + print(f" {header:10} {content}") +endef diff --git a/openfpga_flow/openfpga_cell_library/verilog_sources.f b/openfpga_flow/openfpga_cell_library/verilog_sources.f new file mode 100644 index 000000000..f045187a1 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog_sources.f @@ -0,0 +1,23 @@ +verilog/adder.v +verilog/aib.v +verilog/buf4.v +verilog/dff.v +verilog/dpram.v +verilog/dpram16k.v +verilog/dpram1k.v +verilog/dpram8k.v +verilog/dpram_2048x8.v +verilog/frac_mem_32k.v +verilog/frac_mult_16x16.v +verilog/gpio.v +verilog/inv.v +verilog/latch.v +verilog/lut6.v +verilog/mult_32x32.v +verilog/mult_36x36.v +verilog/mult_8x8.v +verilog/mux2.v +verilog/or2.v +verilog/spram_4x1.v +verilog/sram.v +verilog/tap_buf4.v From 790628b22e317f7be419e673606e97bde5d00530 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:08:31 +0800 Subject: [PATCH 03/16] [ci] add opoenfpga cell library test to ci --- .github/workflows/cell_lib_test.yml | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 .github/workflows/cell_lib_test.yml diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml new file mode 100644 index 000000000..07ac43b84 --- /dev/null +++ b/.github/workflows/cell_lib_test.yml @@ -0,0 +1,36 @@ +name: Cell Library Tests + +# Run CI on push, PR, and weekly. + +on: + push: + pull_request: + schedule: + - cron: "0 0 * * 0 " # weekly + +# Multiple job to tests +jobs: + # Test the RTL compilation compatibility + verilog: + name: RTL compilation and tests + runs-on: ubuntu-latest + steps: + - name: Cancel previous + uses: styfle/cancel-workflow-action@0.9.1 + with: + access_token: ${{ github.token }} + + - name: Checkout OpenFPGA repo + uses: actions/checkout@v2 + with: + submodules: true + + - name: Dump tool versions + run: | + iverilog -V + vvp -V + + - name: Verilog compilation + run: | + cd openfpga_flow/openfpga_cell_library + make compile_verilog From 812af4f722987c557128e1a1d8bd97fd6494c883 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:32:01 +0800 Subject: [PATCH 04/16] [arch] add arch that supports negative edge triggered flip-flop --- openfpga_flow/openfpga_arch/README.md | 2 +- ...4_frac_N4_fracff2edge_40nm_cc_openfpga.xml | 273 +++++++ .../openfpga_cell_library/verilog/dff.v | 2 +- openfpga_flow/vpr_arch/README.md | 2 +- .../k4_frac_N4_tileable_fracff2edge_40nm.xml | 755 ++++++++++++++++++ 5 files changed, 1031 insertions(+), 3 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index 36fb95acd..81bd512f7 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -6,7 +6,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f * The keyword 'frac' is to specify if fracturable LUT is used or not. * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. -- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable +- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs - scan\_chain: If scan chain testing infrastructure is used inside CLBs diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml new file mode 100644 index 000000000..4243e7804 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml @@ -0,0 +1,273 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 2b3f88a5e..814f01a83 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -301,7 +301,7 @@ endmodule //End Of Module // - clock // which can be switched between positive edge triggered and negative edge triggered //----------------------------------------------------- -module MULTI_MODE_DFFRCKQ ( +module MULTI_MODE_DFFNRQ ( input RST, // Reset input input CK, // Clock Input input D, // Data Input diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 8fb2b1fbe..e5855b390 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -7,7 +7,7 @@ Please reveal the following architecture features in the names to help quickly s - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. - tileable: If the routing architecture is tileable or not. * The keyword 'IO' specifies if the I/O tile is tileable or not -- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable +- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs - scan\_chain: If scan chain testing infrastructure is used inside CLBs diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml new file mode 100644 index 000000000..43081040d --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml @@ -0,0 +1,755 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 9c7868cfabe0c0cd702909d43c529518b13fc757 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:41:21 +0800 Subject: [PATCH 05/16] [hdl] add a counter design which is triggered by negative edges --- .../counter.v | 29 +++++++++++++++++++ .../counter_tb.v | 25 ++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v new file mode 100644 index 000000000..12d22e61e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v @@ -0,0 +1,29 @@ +/////////////////////////////////////////// +// Functionality: Counter triggered at negative edge with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clkn, + reset, + result +); + + input clkn; + input reset; + output [7:0] result; + + reg [7:0] result; + + initial begin + result <= 0; + end + + always @(negedge clkn or posedge reset) + begin + if (reset) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v new file mode 100644 index 000000000..566ba3ed7 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, reset; + wire [7:0] result; + + counter DUT( + .clkn(clk), + .reset(reset), + .result(result) + ); + + initial begin + #0 reset = 1'b1; clk = 1'b0; + #100 reset = 1'b0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule From 22c4d723581684fb08500f50702d3b3e4c64a7c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:57:42 +0800 Subject: [PATCH 06/16] [test] add a test case to validate negative edge-triggered ff --- .../config/pin_constraints_reset.xml | 8 ++++ .../k4n4_fracff2edge/config/task.conf | 42 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3c3b38ee7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/task.conf new file mode 100644 index 000000000..fa45d0149 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 0afe3a6d331d8b96e157e5bf98a675d4ed84453e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 16:58:18 +0800 Subject: [PATCH 07/16] [HDL] update dff map rules to support negative triggered ffs --- .../openfpga_yosys_techlib/openfpga_dff_map.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v index 8c6c149c4..28e153e59 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -47,21 +47,21 @@ endmodule // The following techmap operation are not performed right now // as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10 // but in case we implement clock inversion in the future, the support is ready for it. -module \$_DFF_N_ (D, C, Q); +module \$_DFF_N_ (D, CN, Q); input D; - input C; + input CN; output Q; parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); + dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN)); endmodule -module \$_DFF_NP0_ (D, C, R, Q); +module \$_DFF_NP0_ (D, CN, R, Q); input D; - input C; + input CN; input R; output Q; parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); + dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN), .R(R)); endmodule module \$_DFFE_NP0P_ (D, C, E, R, Q); From effa9e0f4169d68cddba0e47c1250a632f692a0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:03:33 +0800 Subject: [PATCH 08/16] [ci] fixed a bug --- .github/workflows/cell_lib_test.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 07ac43b84..59cb8453b 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -25,6 +25,10 @@ jobs: with: submodules: true + - name: Install Dependencies + run: | + source .github/workflow/install_dependencies_run.sh + - name: Dump tool versions run: | iverilog -V From 9f56e613426954217671163dce55e61ca14594ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:13:57 +0800 Subject: [PATCH 09/16] [arch] syntax --- .../k4_frac_N4_tileable_fracff2edge_40nm.xml | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml index 43081040d..21d08c961 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml @@ -70,6 +70,17 @@ + + + + + + + + + + + @@ -82,17 +93,6 @@ - - - - - - - - - - - @@ -447,7 +447,7 @@ - + @@ -624,7 +624,7 @@ - + From 7ed1548c6e323cdd5d0f6242bf8ba101e4491558 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:22:48 +0800 Subject: [PATCH 10/16] [arch] fixed a few bugs --- ...4_frac_N4_fracff2edge_40nm_cc_openfpga.xml | 2 +- .../openfpga_yosys_techlib/openfpga_dff_map.v | 6 ++-- .../openfpga_yosys_techlib/openfpga_dff_sim.v | 28 +++++++++++++++++++ 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml index 4243e7804..7b3b3c4f2 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml @@ -220,7 +220,7 @@ - + diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v index 28e153e59..536ddcd79 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -55,13 +55,13 @@ module \$_DFF_N_ (D, CN, Q); dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN)); endmodule -module \$_DFF_NP0_ (D, CN, R, Q); +module \$_DFF_NP0_ (D, C, R, Q); input D; - input CN; + input C; input R; output Q; parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN), .R(R)); + dffnr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CN(C), .R(R)); endmodule module \$_DFFE_NP0P_ (D, C, E, R, Q); diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v index 12b9e8ec3..4f7478030 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -47,6 +47,34 @@ module dffr( endcase endmodule +(* abc9_flop, lib_whitebox *) +module dffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input CN +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge CN or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge CN or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + (* abc9_flop, lib_whitebox *) module dffre( output reg Q, From d7e854eae737a47d8ec7c402e11fb47499c21a8b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:23:57 +0800 Subject: [PATCH 11/16] [test] deploy new test to ci --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index aefc686c8..66dd32d21 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -110,6 +110,8 @@ echo -e "Testing K4N4 with facturable LUTs"; run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs echo -e "Testing K4N4 with asynchronous reset"; run-task basic_tests/k4_series/k4n4_fracff --debug --show_thread_logs +echo -e "Testing K4N4 with negative edge clocks"; +run-task basic_tests/k4_series/k4n4_fracff2edge --debug --show_thread_logs echo -e "Testing K4N4 with hard adders"; run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs echo -e "Testing K4N4 without local routing architecture"; @@ -185,4 +187,4 @@ run-task template_tasks/vtr_benchmarks_template --debug --show_thread_logs echo -e "Testing create tsk from template and run task" create-task _task_copy basic_tests/generate_fabric -run-task _task_copy \ No newline at end of file +run-task _task_copy From 925ac9051c4f9f2e5ae65d91b8e28ffe463e9c10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:45:31 +0800 Subject: [PATCH 12/16] [ci] typo --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 59cb8453b..2bea7842a 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -27,7 +27,7 @@ jobs: - name: Install Dependencies run: | - source .github/workflow/install_dependencies_run.sh + source .github/workflows/install_dependencies_run.sh - name: Dump tool versions run: | From 15617392ae2115d76126e31ca8481a10d535e7fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:51:02 +0800 Subject: [PATCH 13/16] [ci] debugging --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 2bea7842a..08706b947 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -27,7 +27,7 @@ jobs: - name: Install Dependencies run: | - source .github/workflows/install_dependencies_run.sh + bash .github/workflows/install_dependencies_run.sh - name: Dump tool versions run: | From 52b348c6db84d8c617c108f97b402fdd8baba09f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:54:08 +0800 Subject: [PATCH 14/16] [ci] debug --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 08706b947..32fa43c97 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -27,7 +27,7 @@ jobs: - name: Install Dependencies run: | - bash .github/workflows/install_dependencies_run.sh + sudo .github/workflows/install_dependencies_run.sh - name: Dump tool versions run: | From 0f56dbcb92801291b8475b2fdfd455fb5ca73a8a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 17:58:17 +0800 Subject: [PATCH 15/16] [ci] debug --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 32fa43c97..68071e98d 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -27,7 +27,7 @@ jobs: - name: Install Dependencies run: | - sudo .github/workflows/install_dependencies_run.sh + sudo bash .github/workflows/install_dependencies_run.sh - name: Dump tool versions run: | From b4f9453c00eef7adc2044ca40bdcc0c8c09b14f3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 May 2022 18:00:33 +0800 Subject: [PATCH 16/16] [ci] downgrade ubuntu version in runner due to renamed packages in scripts --- .github/workflows/cell_lib_test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 68071e98d..e04148251 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -13,7 +13,7 @@ jobs: # Test the RTL compilation compatibility verilog: name: RTL compilation and tests - runs-on: ubuntu-latest + runs-on: ubuntu-18.04 steps: - name: Cancel previous uses: styfle/cancel-workflow-action@0.9.1