diff --git a/.svlint.toml b/.svlint.toml index 29bbeb0921..50dd4fc49b 100644 --- a/.svlint.toml +++ b/.svlint.toml @@ -5,7 +5,7 @@ # Rules for svlint, a SystemVerilog linter commonly used in editors. # The configuration matches the lowRISC SystemVerilog style guide at # https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md. -# See https://github.com/dalance/svlint/blob/master/RULES.md for a list of rules. +# See https://github.com/dalance/svlint/blob/master/MANUAL.md for a list of rules. [option] exclude_paths = ["build.*", "sw/.*", ".sv.tpl$", "vendor/.*"] diff --git a/doc/01_overview/verification_overview.rst b/doc/01_overview/verification_overview.rst index 3f13bec5db..77921b7fc6 100644 --- a/doc/01_overview/verification_overview.rst +++ b/doc/01_overview/verification_overview.rst @@ -14,7 +14,7 @@ The configuration space is too large to fully verify the design for all possible To manage this complexity regressions runs and verification closure target a number of :ref:`supported configurations`. Current verification closure effort is focussed on the ``opentitan`` configuration and is the only configuration with nightly regression runs. -Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project `_. +Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project `_. Ibex has achieved **V2S** for the `opentitan` configuration, broadly this means verification is almost complete (over 90% code and functional coverage hit with over 90% regression pass rate with test plan and coverage plan fully implemented) but not yet closed. Nightly regression results, including a coverage summary and details of test failures, for the ``opentitan`` Ibex configuration are published at https://ibex.reports.lowrisc.org/opentitan/latest/report.html. Below is a summary of these results: diff --git a/doc/03_reference/coverage_plan.rst b/doc/03_reference/coverage_plan.rst index b4bdcb327c..551aadea0a 100644 --- a/doc/03_reference/coverage_plan.rst +++ b/doc/03_reference/coverage_plan.rst @@ -342,7 +342,7 @@ For more detail about each security countermeasure in Ibex see :ref:`security` * ``cp_pc_mismatch_err`` - PC mismatch error seen. -The :ref:`security features Ibex implements ` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Hardware Interfaces `_ documentation section). +The :ref:`security features Ibex implements ` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Comportability Definition and Specification `_ documentation section). The mapping between security countermeasures and coverpoints that demonstrate it being used is given below. +--------------------------------+-------------------------------------------------------+ diff --git a/doc/03_reference/debug.rst b/doc/03_reference/debug.rst index aef413a791..5574f4f5d4 100644 --- a/doc/03_reference/debug.rst +++ b/doc/03_reference/debug.rst @@ -3,7 +3,7 @@ Debug Support ============= -Ibex offers support for execution-based debug according to the `RISC-V Debug Specification `_, version 0.13. +Ibex offers support for execution-based debug according to the `RISC-V Debug Specification `_, version 0.13. .. note:: diff --git a/doc/03_reference/verification.rst b/doc/03_reference/verification.rst index 361597160c..d851cbfa0d 100644 --- a/doc/03_reference/verification.rst +++ b/doc/03_reference/verification.rst @@ -19,7 +19,7 @@ At a high level, this testbench uses the open source `RISCV-DV random instructio simple memory model, stimulates the Ibex core to run this program in memory, and then compares the core trace log against a golden model ISS trace log to check for correctness of execution. -Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project `_. +Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project `_. Ibex has achieved **V2S** for the ``opentitan`` configuration, broadly this means verification almost complete (over 90% code and functional coverage hit with over 90% regression pass rate with test plan and coverage plan fully implemented) but not yet closed. @@ -140,7 +140,7 @@ to tell the RISCV-DV code where to find them: .. _LRSpike: https://github.com/lowRISC/riscv-isa-sim .. _riscv-toolchain-source: https://github.com/riscv/riscv-gnu-toolchain .. _riscv-toolchain-releases: https://github.com/lowRISC/lowrisc-toolchains/releases -.. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patches +.. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patch .. _bitmanip: https://github.com/riscv/riscv-bitmanip End-to-end RTL/ISS co-simulation flow @@ -169,7 +169,7 @@ This mechanism is explained in detail at https://github.com/google/riscv-dv/blob As a sidenote, the signature address that this testbench uses for the handshaking is ``0x8ffffffc``. Additionally, as is mentioned in the RISCV-DV documentation of this handshake, a small set of API tasks are provided in `dv/uvm/core_ibex/tests/core_ibex_base_test.sv -`_ to enable easy +`_ to enable easy and efficient integration and usage of this mechanism in this test environment. To see how this handshake is used during real simulations, look in `dv/uvm/core_ibex/tests/core_ibex_test_lib.sv diff --git a/doc/04_developer/concierge.rst b/doc/04_developer/concierge.rst index 74efc594c1..497c1ec8b6 100644 --- a/doc/04_developer/concierge.rst +++ b/doc/04_developer/concierge.rst @@ -25,10 +25,8 @@ The concierge duties rotate between several core developers on a weekly basis. You can find today's concierge on duty in a `public calendar `_. * Greg Chadwick (`@GregAC `_) -* Tom Roberts (`@tomroberts-lowrisc `_) * Rupert Swarbrick (`@rswarbrick `_) * Pirmin Vogel (`@vogelpi `_) -* Philipp Wagner (`@imphil `_) You can be Ibex Concierge, too. Please talk to any of the current concierges to discuss! diff --git a/dv/cs_registers/lint/verilator_waiver.vlt b/dv/cs_registers/lint/verilator_waiver.vlt index 14f01fabd4..911700c515 100644 --- a/dv/cs_registers/lint/verilator_waiver.vlt +++ b/dv/cs_registers/lint/verilator_waiver.vlt @@ -9,7 +9,7 @@ // 'rtl' directory), see verilator_waiver_rtl.vlt in the same // directory. // -// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES +// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files // for documentation. // // Important: This file must included *before* any other Verilog file is read. diff --git a/dv/riscv_compliance/lint/verilator_waiver.vlt b/dv/riscv_compliance/lint/verilator_waiver.vlt index fc9e097305..287b84069c 100644 --- a/dv/riscv_compliance/lint/verilator_waiver.vlt +++ b/dv/riscv_compliance/lint/verilator_waiver.vlt @@ -9,7 +9,7 @@ // 'rtl' directory), see verilator_waiver_rtl.vlt in the same // directory. // -// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES +// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files // for documentation. // // Important: This file must included *before* any other Verilog file is read. diff --git a/dv/uvm/icache/doc/ibex_icache_dv_plan.md b/dv/uvm/icache/doc/ibex_icache_dv_plan.md index 865268ff8c..cd112ef8d0 100644 --- a/dv/uvm/icache/doc/ibex_icache_dv_plan.md +++ b/dv/uvm/icache/doc/ibex_icache_dv_plan.md @@ -11,12 +11,12 @@ title: "Ibex ICache DV Plan" ## Current status -* Design & verification stage (TODO: Create HW dashboard & add link) (see [HW development stages](https://docs.opentitan.org/doc/project/hw_stages) for what this means) +* Design & verification stage (TODO: Create HW dashboard & add link) (see [HW development stages](https://opentitan.org/book/doc/project_governance/development_stages.html) for what this means) * Simulation results (TODO: Generate nightly simulation results & add link) ## Design features -The ICache design is documented in the [Instruction Cache](https://ibex-core.readthedocs.io/en/latest/icache.html) section of the Ibex User Manual. +The ICache design is documented in the [Instruction Cache](https://ibex-core.readthedocs.io/en/latest/03_reference/icache.html) section of the Ibex User Manual. ## Testbench architecture @@ -155,7 +155,7 @@ Coverpoints will be created at two levels, ICache top level and individual fill * `FBAwaitingOutput` - Waiting for fill buffer data to be consumed by output before releasing * `cp_fb_done_reason` - Why the fill buffer has finished * `FBNotDone` - Fill buffer not yet done - * `FBDoneHitNoExtReqs` - Fill buffer hit against cache and sent no external requests + * `FBDoneHitNoExtReqs` - Fill buffer hit against cache and sent no external requests * `FBDoneHitExtReqs` - Fill buffer hit against cache and sent external requests (which must be completed before fill buffer can release) * `FBDoneMiss` - Fill buffer missed in cache and has fetched data to satisfy request * `FBDoneBranchNoExtReqs` - Fill buffer became stale due to branch and sent no external requests and so released diff --git a/examples/simple_system/README.md b/examples/simple_system/README.md index 12ab72df9c..026bbb7c66 100644 --- a/examples/simple_system/README.md +++ b/examples/simple_system/README.md @@ -11,7 +11,7 @@ run stand-alone binaries. It contains: ## Prerequisites -* [Verilator](https://www.veripool.org/wiki/verilator) +* [Verilator](https://www.veripool.org/verilator/) Note Linux package managers may have Verilator but often a very old version that is not suitable. It is recommended Verilator is built from source. * The Python dependencies of this repository. diff --git a/examples/simple_system/lint/verilator_waiver.vlt b/examples/simple_system/lint/verilator_waiver.vlt index b454d0c58c..44a1c28640 100644 --- a/examples/simple_system/lint/verilator_waiver.vlt +++ b/examples/simple_system/lint/verilator_waiver.vlt @@ -9,7 +9,7 @@ // 'rtl' directory), see verilator_waiver_rtl.vlt in the same // directory. // -// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES +// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files // for documentation. // // Important: This file must included *before* any other Verilog file is read. diff --git a/lint/verilator_waiver.vlt b/lint/verilator_waiver.vlt index d03f9bcb48..939bb3fb6b 100644 --- a/lint/verilator_waiver.vlt +++ b/lint/verilator_waiver.vlt @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 // Lint waivers for Verilator -// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES +// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files // for documentation. // // Important: This file must included *before* any other Verilog file is read.