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Create a fusesoc hook for FPGA splice script #1

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rpenugo opened this issue Aug 30, 2019 · 2 comments
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Create a fusesoc hook for FPGA splice script #1

rpenugo opened this issue Aug 30, 2019 · 2 comments
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@imphil

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@rpenugo
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rpenugo commented Aug 30, 2019

On top of PR lowRISC/stwg-base#847 there is a need to hook this script to fusesoc just like extended run after bitfile generation is complete

@imphil has offered to help on this.. once the original PR lowRISC/stwg-base#847 merges in.

Creating a tracker for the same
@lowrisc-bot lowrisc-bot transferred this issue from another repository Aug 31, 2019
@sriyerg sriyerg mentioned this issue Oct 7, 2019
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cdgori referenced this issue Oct 17, 2019
@vogelpi
[aes/rtl] Replace long ternary expressions
68e3ea5 
This commit replaces long ternary expressions by a combination of
`if/else` and `unique case` statements.
@cindychip cindychip mentioned this issue Oct 24, 2019
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@sjgitty
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sjgitty commented Oct 25, 2019

@imphil I'm guessing this is no longer needed?

@weicaiyang weicaiyang mentioned this issue Nov 5, 2019
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weicaiyang added a commit that referenced this issue Nov 5, 2019
@weicaiyang
[dv] Fix cover.cfg and fix outstanding cg
52282da 
1. Fix cover.cfg to remove #1
2  Fix outstanding covergroup in tl monitor
@imphil imphil mentioned this issue Nov 14, 2019
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@imphil
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imphil commented Dec 7, 2019

That's unnecessary, since we build the bootrom into the bitstream at synthesis time using Vivado directly. The splice script is optional and only used in special cases.

@imphil imphil closed this as completed Dec 7, 2019
@tjaychen tjaychen mentioned this issue Apr 2, 2020
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@cdgori cdgori mentioned this issue Jul 6, 2020
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@felixmiller felixmiller mentioned this issue Jul 28, 2020
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@sriyerg sriyerg mentioned this issue Sep 12, 2020
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@felixmiller felixmiller mentioned this issue Sep 30, 2020
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@tunghoang290780 tunghoang290780 mentioned this issue Oct 30, 2020
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@udinator udinator mentioned this issue Dec 23, 2020
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@cindychip cindychip mentioned this issue Sep 14, 2021
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@pt07L pt07L mentioned this issue Sep 16, 2021
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@weicaiyang weicaiyang mentioned this issue Mar 4, 2022
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drewmacrae pushed a commit to drewmacrae/opentitan that referenced this issue Mar 28, 2022
@cfrantz
Initial gcc toolchain configuration for the lowRISC compiler. (lowRISC#1
f7299c2 
)

Initial toolchain definition for riscv32

1. Configure lowrisc_toolchain_rv32imc for use by the OpenTitan project.
2. Deliver per-device flags to the GccEmbeddedFeatures function.
3. Turn off some per-feature compiler/linker flags.  Need to find a
   better way to do this.

Signed-off-by: Chris Frantz <cfrantz@google.com>
@bilgiday bilgiday mentioned this issue Nov 17, 2022
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@msfschaffner msfschaffner mentioned this issue May 6, 2023
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@rswarbrick rswarbrick mentioned this issue Aug 31, 2023
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@Razer6 Razer6 mentioned this issue Nov 23, 2023
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@antmarzam antmarzam mentioned this issue Mar 18, 2024
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@vsukhoml vsukhoml mentioned this issue Mar 19, 2024
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@vsukhoml vsukhoml mentioned this issue Mar 28, 2024
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@rswarbrick rswarbrick mentioned this issue Apr 25, 2024
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rswarbrick added a commit that referenced this issue Apr 25, 2024
@rswarbrick
[prim,rtl,fpv] Fix typo in assertion in prim_alert_receiver
2222770 
This precondition for the assertion was never possible because
!state_q was never InitReq or InitAckWait.

Unfortunately, fixing this makes the assertion false. It turns out
that the problem was that the init_trig_i signal squashes the ping.
Add a condition based on this.

Annoyingly the result is very repetitive! To make things a bit tidier,
move the condition into the __rst argument of the `ASSERT macro.

Finally, drop the initial "##1" (which avoided the property triggering
just after reset). The $rose(...) condition implies this
anyway (because it's false on the first cycle after reset), so we can
drop the cycle. This makes the property marginally stronger (and
Jasper still proves it!)

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Scheremo pushed a commit to mosaic-soc/opentitan that referenced this issue Nov 18, 2024
@paulsc96 @creinwar
Bug fixes to SPI host, update regfiles and Bender (lowRISC#1)
881f8bc 
* vendor: Update to using Bender 0.27.0

* vendor: Fixes to spi_host

* makefile: Fix vendor command

* vendor: Update generated regfiles

Co-authored-by: Christopher Reinwardt <creinwar@ethz.ch>
@Razer6 Razer6 mentioned this issue Nov 27, 2024
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