From 0135ba275ba41141d979f721e402b2c20b21ceef Mon Sep 17 00:00:00 2001 From: Arun Saravanan Balachandran <52521751+ArunSaravananBalachandran@users.noreply.github.com> Date: Wed, 30 Jun 2021 03:49:54 +0530 Subject: [PATCH] DellEMC S6100: Determine pcie.yaml revision based on firmware (#7875) Why I did it To determine the revision of the pcie.yaml to be used based on BIOS version in DellEMC S6100 platform. Depends on: Azure/sonic-platform-common#195 How I did it Added two revisions of pcie.yaml pcie_1.yaml and pcie_2.yaml Included a platform-specific Pcie class to provide the revision of the pcie.yaml to be used by pcieutil/pcied. How to verify it Execute pcieutil check (Azure/sonic-utilities#1672) command and verify the list of PCIe devices displayed. Logs: UT_logs.txt --- .../{pcie.yaml => pcie_1.yaml} | 0 .../x86_64-dell_s6100_c2538-r0/pcie_2.yaml | 50 +++++++++++++++++++ .../s6100/sonic_platform/pcie.py | 29 +++++++++++ 3 files changed, 79 insertions(+) rename device/dell/x86_64-dell_s6100_c2538-r0/{pcie.yaml => pcie_1.yaml} (100%) create mode 100644 device/dell/x86_64-dell_s6100_c2538-r0/pcie_2.yaml create mode 100644 platform/broadcom/sonic-platform-modules-dell/s6100/sonic_platform/pcie.py diff --git a/device/dell/x86_64-dell_s6100_c2538-r0/pcie.yaml b/device/dell/x86_64-dell_s6100_c2538-r0/pcie_1.yaml similarity index 100% rename from device/dell/x86_64-dell_s6100_c2538-r0/pcie.yaml rename to device/dell/x86_64-dell_s6100_c2538-r0/pcie_1.yaml diff --git a/device/dell/x86_64-dell_s6100_c2538-r0/pcie_2.yaml b/device/dell/x86_64-dell_s6100_c2538-r0/pcie_2.yaml new file mode 100644 index 000000000000..2591c5900452 --- /dev/null +++ b/device/dell/x86_64-dell_s6100_c2538-r0/pcie_2.yaml @@ -0,0 +1,50 @@ +- bus: '00' + dev: '01' + fn: '0' + id: 1f10 + name: 'PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 1' +- bus: '00' + dev: '03' + fn: '0' + id: 1f12 + name: 'PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 3' +- bus: '00' + dev: '04' + fn: '0' + id: 1f13 + name: 'PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 4' +- bus: '00' + dev: 0f + fn: '0' + id: 1f16 + name: 'IOMMU: Intel Corporation Atom processor C2000 RCEC' +- bus: '00' + dev: '13' + fn: '0' + id: 1f15 + name: 'System peripheral: Intel Corporation Atom processor C2000 SMBus 2.0' +- bus: '00' + dev: '14' + fn: '0' + id: 1f41 + name: 'Ethernet controller: Intel Corporation Ethernet Connection I354' +- bus: '00' + dev: '14' + fn: '1' + id: 1f41 + name: 'Ethernet controller: Intel Corporation Ethernet Connection I354' +- bus: '00' + dev: '14' + fn: '2' + id: 1f41 + name: 'Ethernet controller: Intel Corporation Ethernet Connection I354' +- bus: '01' + dev: '00' + fn: '0' + id: b960 + name: 'Ethernet controller: Broadcom Limited Broadcom BCM56960 Switch ASIC' +- bus: '01' + dev: '00' + fn: '1' + id: b960 + name: 'Ethernet controller: Broadcom Limited Broadcom BCM56960 Switch ASIC' diff --git a/platform/broadcom/sonic-platform-modules-dell/s6100/sonic_platform/pcie.py b/platform/broadcom/sonic-platform-modules-dell/s6100/sonic_platform/pcie.py new file mode 100644 index 000000000000..cff56c1ea55f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/s6100/sonic_platform/pcie.py @@ -0,0 +1,29 @@ +######################################################################## +# +# DELLEMC S6100 +# +# Module contains a platform specific implementation of SONiC Platform +# Base PCIe class +# +######################################################################## + +try: + from sonic_platform.component import Component + from sonic_platform_base.sonic_pcie.pcie_common import PcieUtil +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Pcie(PcieUtil): + """DellEMC Platform-specific PCIe class""" + + def __init__(self, platform_path): + PcieUtil.__init__(self, platform_path) + bios = Component(component_index=0) + bios_ver = bios.get_firmware_version() + + versions = bios_ver.split("-") + if (len(versions) == 2) and int(versions[1], 10) > 5: + self._conf_rev = "2" + else: + self._conf_rev = "1"