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Bender.yml
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Bender.yml
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# Copyright 2023 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
# Authors:
# - Thomas Benz <tbenz@iis.ee.ethz.ch>
package:
name: idma
authors:
- "Thomas Benz <tbenz@iis.ee.ethz.ch>" # current maintainer
- "Michael Rogenmoser <michaero@iis.ee.ethz.ch>"
- "Tobias Senti <tsenti@ethz.ch>"
- "Axel Vanoni <axvanoni@ethz.ch>"
dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 }
idma_gen: { path: "target/rtl" }
export_include_dirs:
- src/include
- target/rtl/include
sources:
# Source files grouped in levels. Files in level 0 have no dependencies on files in this
# package. Files in level 1 only depend on files in level 0, files in level 2 on files in
# levels 1 and 0, etc. Files within a level are ordered alphabetically.
- target: rtl
files:
# IDMA packet is included through the idma_gen dependency
# Level 0
- src/backend/idma_axil_read.sv
- src/backend/idma_axil_write.sv
- src/backend/idma_axi_read.sv
- src/backend/idma_axi_write.sv
- src/backend/idma_axis_read.sv
- src/backend/idma_axis_write.sv
- src/backend/idma_channel_coupler.sv
- src/backend/idma_dataflow_element.sv
- src/backend/idma_error_handler.sv
- src/backend/idma_init_read.sv
- src/backend/idma_init_write.sv
- src/backend/idma_obi_read.sv
- src/backend/idma_obi_write.sv
- src/backend/idma_tilelink_read.sv
- src/backend/idma_tilelink_write.sv
- src/future/idma_improved_fifo.sv
- src/future/idma_legalizer_page_splitter.sv
- src/future/idma_legalizer_pow2_splitter.sv
- src/future/idma_reg_to_axi.sv
# Midends
- target: rtl
files:
# Level 0
- src/midend/idma_mp_dist_midend.sv
- src/midend/idma_mp_split_midend.sv
- src/midend/idma_nd_midend.sv
- src/midend/idma_rt_midend.sv
# Frontends (without inst64)
- target: rtl
files:
# Level 0
- src/frontend/desc64/idma_desc64_ar_gen.sv
- src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv
- src/frontend/desc64/idma_desc64_reader.sv
- src/frontend/desc64/idma_desc64_reader_gater.sv
- src/frontend/desc64/idma_desc64_reshaper.sv
- src/frontend/idma_transfer_id_gen.sv
# Level 1
- src/frontend/desc64/idma_desc64_reg_wrapper.sv
# Level 2
- src/frontend/desc64/idma_desc64_top.sv
# Synthesis wrappers
- target: synth
files:
# Level 0
- src/frontend/desc64/idma_desc64_synth_pkg.sv
- src/midend/idma_mp_midend_synth_pkg.sv
- src/midend/idma_nd_midend_synth.sv
- src/midend/idma_rt_midend_synth_pkg.sv
# Level 1
- src/frontend/desc64/idma_desc64_synth.sv
- src/midend/idma_mp_midend_synth.sv
- src/midend/idma_rt_midend_synth.sv
# Testbenches
- target: test
files:
# Level 0
- test/frontend/tb_idma_desc64_top.sv
- test/frontend/tb_idma_desc64_bench.sv
- test/future/idma_tb_per2axi.sv
- test/future/idma_obi_asserter.sv
- test/future/TLToAXI4.v
- test/future/tb_idma_improved_fifo.sv
- test/midend/tb_idma_nd_midend.sv
- test/midend/tb_idma_rt_midend.sv
# Level 1
- test/future/idma_obi2axi_bridge.sv
- test/future/idma_tilelink2axi_bridge.sv