diff --git a/js/src/jit-test/lib/wasm-binary.js b/js/src/jit-test/lib/wasm-binary.js index 4929d6baa27c9..832d1feaa7d99 100644 --- a/js/src/jit-test/lib/wasm-binary.js +++ b/js/src/jit-test/lib/wasm-binary.js @@ -234,6 +234,11 @@ F64Code 0x7c ; const +V128Code += +0x7b +; +const AnyFuncCode = 0x70 @@ -296,6 +301,11 @@ SelectCode 0x1b ; const +LocalGetCode += +0x20 +; +const I32Load = 0x28 @@ -535,6 +545,105 @@ RefFuncCode = 0xd2 ; +/ +/ +SIMD +opcodes +const +V128LoadCode += +0x00 +; +const +V128StoreCode += +0x0b +; +/ +/ +Experimental +SIMD +opcodes +as +of +August +2020 +. +const +I32x4DotSI16x8Code += +0xba +; +const +F32x4CeilCode += +0xd8 +; +const +F32x4FloorCode += +0xd9 +; +const +F32x4TruncCode += +0xda +; +const +F32x4NearestCode += +0xdb +; +const +F64x2CeilCode += +0xdc +; +const +F64x2FloorCode += +0xdd +; +const +F64x2TruncCode += +0xde +; +const +F64x2NearestCode += +0xdf +; +const +F32x4PMinCode += +0xea +; +const +F32x4PMaxCode += +0xeb +; +const +F64x2PMinCode += +0xf6 +; +const +F64x2PMaxCode += +0xf7 +; +const +V128Load32ZeroCode += +0xfc +; +const +V128Load64ZeroCode += +0xfd +; const FirstInvalidOpcode = @@ -1925,6 +2034,18 @@ name ) ) ; +if +( +exp +. +hasOwnProperty +( +" +funcIndex +" +) +) +{ body . push @@ -1954,6 +2075,60 @@ funcIndex ) ; } +else +if +( +exp +. +hasOwnProperty +( +" +memIndex +" +) +) +{ +body +. +push +( +. +. +. +varU32 +( +MemoryCode +) +) +; +body +. +push +( +. +. +. +varU32 +( +exp +. +memIndex +) +) +; +} +else +{ +throw +" +Bad +export +" ++ +exp +; +} +} return { name diff --git a/js/src/jit-test/tests/wasm/simd/experimental.js b/js/src/jit-test/tests/wasm/simd/experimental.js new file mode 100644 index 0000000000000..665b3af64a9a2 --- /dev/null +++ b/js/src/jit-test/tests/wasm/simd/experimental.js @@ -0,0 +1,1730 @@ +/ +/ +Experimental +opcodes +. +We +have +no +text +parsing +support +for +these +yet +. +The +/ +/ +tests +will +be +cleaned +up +and +moved +into +ad +- +hack +. +js +if +the +opcodes +are +/ +/ +adopted +. +/ +/ +When +simd +is +enabled +by +default +in +release +builds +we +will +flip +the +value +of +/ +/ +SimdExperimentalEnabled +to +false +in +RELEASE_OR_BETA +builds +. +At +that +point +/ +/ +these +tests +will +start +failing +in +release +or +beta +builds +and +a +guard +/ +/ +asserting +! +RELEASE_OR_BETA +will +have +to +be +added +above +. +That +is +how +it +/ +/ +should +be +. +load +( +libdir ++ +" +wasm +- +binary +. +js +" +) +; +function +wasmEval +( +bytes +imports +) +{ +return +new +WebAssembly +. +Instance +( +new +WebAssembly +. +Module +( +bytes +) +imports +) +; +} +function +get +( +arr +loc +len +) +{ +let +res += +[ +] +; +for +( +let +i += +0 +; +i +< +len +; +i ++ ++ +) +{ +res +. +push +( +arr +[ +loc ++ +i +] +) +; +} +return +res +; +} +function +set +( +arr +loc +vals +) +{ +for +( +let +i += +0 +; +i +< +vals +. +length +; +i ++ ++ +) +{ +if +( +arr +instanceof +BigInt64Array +) +{ +arr +[ +loc ++ +i +] += +BigInt +( +vals +[ +i +] +) +; +} +else +{ +arr +[ +loc ++ +i +] += +vals +[ +i +] +; +} +} +} +function +assertSame +( +got +expected +) +{ +assertEq +( +got +. +length +expected +. +length +) +; +for +( +let +i += +0 +; +i +< +got +. +length +; +i ++ ++ +) +{ +let +g += +got +[ +i +] +; +let +e += +expected +[ +i +] +; +if +( +typeof +g +! += +typeof +e +) +{ +if +( +typeof +g += += +" +bigint +" +) +e += +BigInt +( +e +) +; +else +if +( +typeof +e += += +" +bigint +" +) +g += +BigInt +( +g +) +; +} +assertEq +( +g +e +) +; +} +} +function +iota +( +len +) +{ +let +xs += +[ +] +; +for +( +let +i += +0 +; +i +< +len +; +i ++ ++ +) +xs +. +push +( +i +) +; +return +xs +; +} +function +pmin +( +x +y +) +{ +return +y +< +x +? +y +: +x +} +function +pmax +( +x +y +) +{ +return +x +< +y +? +y +: +x +} +function +ffloor +( +x +) +{ +return +Math +. +fround +( +Math +. +floor +( +x +) +) +} +function +fceil +( +x +) +{ +return +Math +. +fround +( +Math +. +ceil +( +x +) +) +} +function +ftrunc +( +x +) +{ +return +Math +. +fround +( +Math +. +sign +( +x +) +* +Math +. +floor +( +Math +. +abs +( +x +) +) +) +} +function +fnearest +( +x +) +{ +return +Math +. +fround +( +Math +. +round +( +x +) +) +} +function +dfloor +( +x +) +{ +return +Math +. +floor +( +x +) +} +function +dceil +( +x +) +{ +return +Math +. +ceil +( +x +) +} +function +dtrunc +( +x +) +{ +return +Math +. +sign +( +x +) +* +Math +. +floor +( +Math +. +abs +( +x +) +) +} +function +dnearest +( +x +) +{ +return +Math +. +round +( +x +) +} +const +v2vSig += +{ +args +: +[ +] +ret +: +VoidCode +} +; +function +V128Load +( +addr +) +{ +return +[ +I32ConstCode +varS32 +( +addr +) +SimdPrefix +V128LoadCode +4 +varU32 +( +0 +) +] +} +function +V128StoreExpr +( +addr +v +) +{ +return +[ +I32ConstCode +varS32 +( +addr +) +. +. +. +v +SimdPrefix +V128StoreCode +4 +varU32 +( +0 +) +] +; +} +/ +/ +Pseudo +- +min +/ +max +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +122 +var +fxs += +[ +5 +1 +- +4 +2 +] +; +var +fys += +[ +6 +0 +- +7 +3 +] +; +var +dxs += +[ +5 +1 +] +; +var +dys += +[ +6 +0 +] +; +for +( +let +[ +opcode +xs +ys +operator +] +of +[ +[ +F32x4PMinCode +fxs +fys +pmin +] +[ +F32x4PMaxCode +fxs +fys +pmax +] +[ +F64x2PMinCode +dxs +dys +pmin +] +[ +F64x2PMaxCode +dxs +dys +pmax +] +] +) +{ +var +k += +xs +. +length +; +var +ans += +iota +( +k +) +. +map +( +( +i +) += +> +operator +( +xs +[ +i +] +ys +[ +i +] +) +) +var +ins += +wasmEval +( +moduleWithSections +( +[ +sigSection +( +[ +v2vSig +] +) +declSection +( +[ +0 +] +) +memorySection +( +1 +) +exportSection +( +[ +{ +funcIndex +: +0 +name +: +" +run +" +} +{ +memIndex +: +0 +name +: +" +mem +" +} +] +) +bodySection +( +[ +funcBody +( +{ +locals +: +[ +] +body +: +[ +. +. +. +V128StoreExpr +( +0 +[ +. +. +. +V128Load +( +16 +) +. +. +. +V128Load +( +32 +) +SimdPrefix +varU32 +( +opcode +) +] +) +] +} +) +] +) +] +) +) +; +var +mem += +new +( +k += += +4 +? +Float32Array +: +Float64Array +) +( +ins +. +exports +. +mem +. +buffer +) +; +set +( +mem +k +xs +) +; +set +( +mem +2 +* +k +ys +) +; +ins +. +exports +. +run +( +) +; +var +result += +get +( +mem +0 +k +) +; +assertSame +( +result +ans +) +; +} +/ +/ +Widening +integer +dot +product +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +127 +var +ins += +wasmEval +( +moduleWithSections +( +[ +sigSection +( +[ +v2vSig +] +) +declSection +( +[ +0 +] +) +memorySection +( +1 +) +exportSection +( +[ +{ +funcIndex +: +0 +name +: +" +run +" +} +{ +memIndex +: +0 +name +: +" +mem +" +} +] +) +bodySection +( +[ +funcBody +( +{ +locals +: +[ +] +body +: +[ +. +. +. +V128StoreExpr +( +0 +[ +. +. +. +V128Load +( +16 +) +. +. +. +V128Load +( +32 +) +SimdPrefix +varU32 +( +I32x4DotSI16x8Code +) +] +) +] +} +) +] +) +] +) +) +; +var +xs += +[ +5 +1 +- +4 +2 +20 +- +15 +12 +3 +] +; +var +ys += +[ +6 +0 +- +7 +3 +8 +- +1 +- +3 +7 +] +; +var +ans += +[ +xs +[ +0 +] +* +ys +[ +0 +] ++ +xs +[ +1 +] +* +ys +[ +1 +] +xs +[ +2 +] +* +ys +[ +2 +] ++ +xs +[ +3 +] +* +ys +[ +3 +] +xs +[ +4 +] +* +ys +[ +4 +] ++ +xs +[ +5 +] +* +ys +[ +5 +] +xs +[ +6 +] +* +ys +[ +6 +] ++ +xs +[ +7 +] +* +ys +[ +7 +] +] +; +var +mem16 += +new +Int16Array +( +ins +. +exports +. +mem +. +buffer +) +; +var +mem32 += +new +Int32Array +( +ins +. +exports +. +mem +. +buffer +) +; +set +( +mem16 +8 +xs +) +; +set +( +mem16 +16 +ys +) +; +ins +. +exports +. +run +( +) +; +var +result += +get +( +mem32 +0 +4 +) +; +assertSame +( +result +ans +) +; +/ +/ +Rounding +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +232 +var +fxs += +[ +5 +. +1 +- +1 +. +1 +- +4 +. +3 +0 +] +; +var +dxs += +[ +5 +. +1 +- +1 +. +1 +] +; +for +( +let +[ +opcode +xs +operator +] +of +[ +[ +F32x4CeilCode +fxs +fceil +] +[ +F32x4FloorCode +fxs +ffloor +] +[ +F32x4TruncCode +fxs +ftrunc +] +[ +F32x4NearestCode +fxs +fnearest +] +[ +F64x2CeilCode +dxs +dceil +] +[ +F64x2FloorCode +dxs +dfloor +] +[ +F64x2TruncCode +dxs +dtrunc +] +[ +F64x2NearestCode +dxs +dnearest +] +] +) +{ +var +k += +xs +. +length +; +var +ans += +xs +. +map +( +operator +) +; +var +ins += +wasmEval +( +moduleWithSections +( +[ +sigSection +( +[ +v2vSig +] +) +declSection +( +[ +0 +] +) +memorySection +( +1 +) +exportSection +( +[ +{ +funcIndex +: +0 +name +: +" +run +" +} +{ +memIndex +: +0 +name +: +" +mem +" +} +] +) +bodySection +( +[ +funcBody +( +{ +locals +: +[ +] +body +: +[ +. +. +. +V128StoreExpr +( +0 +[ +. +. +. +V128Load +( +16 +) +SimdPrefix +varU32 +( +opcode +) +] +) +] +} +) +] +) +] +) +) +; +var +mem += +new +( +k += += +4 +? +Float32Array +: +Float64Array +) +( +ins +. +exports +. +mem +. +buffer +) +; +set +( +mem +k +xs +) +; +ins +. +exports +. +run +( +) +; +var +result += +get +( +mem +0 +k +) +; +assertSame +( +result +ans +) +; +} +/ +/ +Zero +- +extending +SIMD +load +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +237 +for +( +let +[ +opcode +k +log2align +cons +cast +] +of +[ +[ +V128Load32ZeroCode +4 +2 +Int32Array +Number +] +[ +V128Load64ZeroCode +2 +3 +BigInt64Array +BigInt +] +] +) +{ +var +ins += +wasmEval +( +moduleWithSections +( +[ +sigSection +( +[ +v2vSig +] +) +declSection +( +[ +0 +] +) +memorySection +( +1 +) +exportSection +( +[ +{ +funcIndex +: +0 +name +: +" +run +" +} +{ +memIndex +: +0 +name +: +" +mem +" +} +] +) +bodySection +( +[ +funcBody +( +{ +locals +: +[ +] +body +: +[ +. +. +. +V128StoreExpr +( +0 +[ +I32ConstCode +varU32 +( +16 +) +SimdPrefix +varU32 +( +opcode +) +log2align +varU32 +( +0 +) +] +) +] +} +) +] +) +] +) +) +; +var +mem += +new +cons +( +ins +. +exports +. +mem +. +buffer +) +; +mem +[ +k +] += +cast +( +37 +) +; +ins +. +exports +. +run +( +) +; +var +result += +get +( +mem +0 +k +) +; +assertSame +( +result +iota +( +k +) +. +map +( +( +v +) += +> +v += += +0 +? +37 +: +0 +) +) +; +} diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h index ebec7b9f00c83..96a10dc574785 100644 --- a/js/src/jit/MacroAssembler.h +++ b/js/src/jit/MacroAssembler.h @@ -18442,6 +18442,281 @@ DEFINED_ON x86_shared ) ; +/ +/ +Compare +- +based +minimum +/ +maximum +( +experimental +as +of +August +2020 +) +/ +/ +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +122 +inline +void +pseudoMinFloat32x4 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +pseudoMinFloat64x2 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +pseudoMaxFloat32x4 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +pseudoMaxFloat64x2 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +DEFINED_ON +( +x86_shared +) +; +/ +/ +Widening +/ +pairwise +integer +dot +product +( +experimental +as +of +August +2020 +) +/ +/ +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +127 +inline +void +widenDotInt16x8 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +DEFINED_ON +( +x86_shared +) +; +/ +/ +Floating +point +rounding +( +experimental +as +of +August +2020 +) +/ +/ +https +: +/ +/ +github +. +com +/ +WebAssembly +/ +simd +/ +pull +/ +232 +inline +void +ceilFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +ceilFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +floorFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +floorFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +truncFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +truncFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +nearestFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; +inline +void +nearestFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +DEFINED_ON +( +x86_shared +) +; public : / diff --git a/js/src/jit/arm/MacroAssembler-arm.cpp b/js/src/jit/arm/MacroAssembler-arm.cpp index 382f86b0ba41e..ff6dfd1d30561 100644 --- a/js/src/jit/arm/MacroAssembler-arm.cpp +++ b/js/src/jit/arm/MacroAssembler-arm.cpp @@ -41914,6 +41914,16 @@ high } else { +MOZ_ASSERT +( +! +access +. +isZeroExtendSimd128Load +( +) +) +; bool isFloat = diff --git a/js/src/jit/arm64/MacroAssembler-arm64.cpp b/js/src/jit/arm64/MacroAssembler-arm64.cpp index d10e6309b771b..c4e87474ec127 100644 --- a/js/src/jit/arm64/MacroAssembler-arm64.cpp +++ b/js/src/jit/arm64/MacroAssembler-arm64.cpp @@ -2702,6 +2702,16 @@ Scalar : Float32 : +MOZ_ASSERT +( +! +access +. +isZeroExtendSimd128Load +( +) +) +; Ldr ( SelectFPReg @@ -2721,6 +2731,16 @@ Scalar : Float64 : +MOZ_ASSERT +( +! +access +. +isZeroExtendSimd128Load +( +) +) +; Ldr ( SelectFPReg diff --git a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp index 4b5f1222878ab..47aa3f92cc23a 100644 --- a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp +++ b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp @@ -12979,6 +12979,16 @@ Scalar : Float64 : +MOZ_ASSERT +( +! +access +. +isZeroExtendSimd128Load +( +) +) +; isFloat = true @@ -12991,6 +13001,16 @@ Scalar : Float32 : +MOZ_ASSERT +( +! +access +. +isZeroExtendSimd128Load +( +) +) +; isFloat = true diff --git a/js/src/jit/shared/Assembler-shared.h b/js/src/jit/shared/Assembler-shared.h index f85065214b2ad..efe999f0b44d6 100644 --- a/js/src/jit/shared/Assembler-shared.h +++ b/js/src/jit/shared/Assembler-shared.h @@ -3126,6 +3126,9 @@ wasm BytecodeOffset trapOffset_ ; +bool +zeroExtendSimd128Load_ +; public : explicit @@ -3181,6 +3184,10 @@ trapOffset_ ( trapOffset ) +zeroExtendSimd128Load_ +( +false +) { MOZ_ASSERT ( @@ -3285,6 +3292,58 @@ isNone ) ; } +bool +isZeroExtendSimd128Load +( +) +const +{ +return +zeroExtendSimd128Load_ +; +} +void +setZeroExtendSimd128Load +( +) +{ +MOZ_ASSERT +( +type +( +) += += +Scalar +: +: +Float32 +| +| +type +( +) += += +Scalar +: +: +Float64 +) +; +MOZ_ASSERT +( +! +isAtomic +( +) +) +; +zeroExtendSimd128Load_ += +true +; +} void clearOffset ( diff --git a/js/src/jit/x64/MacroAssembler-x64.cpp b/js/src/jit/x64/MacroAssembler-x64.cpp index 5640394af06eb..a1aceeccece8e 100644 --- a/js/src/jit/x64/MacroAssembler-x64.cpp +++ b/js/src/jit/x64/MacroAssembler-x64.cpp @@ -4322,7 +4322,21 @@ Scalar : Float32 : -loadFloat32 +/ +/ +vmovss +does +the +right +thing +also +for +access +. +isZeroExtendSimdLoad +( +) +vmovss ( srcAddr out @@ -4340,7 +4354,21 @@ Scalar : Float64 : -loadDouble +/ +/ +vmovsd +does +the +right +thing +also +for +access +. +isZeroExtendSimdLoad +( +) +vmovsd ( srcAddr out diff --git a/js/src/jit/x86-shared/Assembler-x86-shared.h b/js/src/jit/x86-shared/Assembler-x86-shared.h index 573d075240396..9b1cd59f0e993 100644 --- a/js/src/jit/x86-shared/Assembler-x86-shared.h +++ b/js/src/jit/x86-shared/Assembler-x86-shared.h @@ -1872,6 +1872,60 @@ X86Encoding ConditionNP } ; +enum +class +SSERoundingMode +{ +Nearest += +int +( +X86Encoding +: +: +SSERoundingMode +: +: +RoundToNearest +) +Floor += +int +( +X86Encoding +: +: +SSERoundingMode +: +: +RoundDown +) +Ceil += +int +( +X86Encoding +: +: +SSERoundingMode +: +: +RoundUp +) +Trunc += +int +( +X86Encoding +: +: +SSERoundingMode +: +: +RoundToZero +) +} +; / / If @@ -4064,6 +4118,76 @@ encoding void vmovsd ( +const +Operand +& +src +FloatRegister +dest +) +{ +switch +( +src +. +kind +( +) +) +{ +case +Operand +: +: +MEM_REG_DISP +: +vmovsd +( +src +. +toAddress +( +) +dest +) +; +break +; +case +Operand +: +: +MEM_SCALE +: +vmovsd +( +src +. +toBaseIndex +( +) +dest +) +; +break +; +default +: +MOZ_CRASH +( +" +Unknown +operand +for +vmovsd +" +) +; +} +} +void +vmovsd +( FloatRegister src const @@ -4265,6 +4389,76 @@ encoding void vmovss ( +const +Operand +& +src +FloatRegister +dest +) +{ +switch +( +src +. +kind +( +) +) +{ +case +Operand +: +: +MEM_REG_DISP +: +vmovss +( +src +. +toAddress +( +) +dest +) +; +break +; +case +Operand +: +: +MEM_SCALE +: +vmovss +( +src +. +toBaseIndex +( +) +dest +) +; +break +; +default +: +MOZ_CRASH +( +" +Unknown +operand +for +vmovss +" +) +; +} +} +void +vmovss +( FloatRegister src const @@ -22225,6 +22419,77 @@ kind } } void +vpmaddwd +( +const +Operand +& +src1 +FloatRegister +src0 +FloatRegister +dest +) +{ +MOZ_ASSERT +( +HasSSE2 +( +) +) +; +switch +( +src1 +. +kind +( +) +) +{ +case +Operand +: +: +FPREG +: +masm +. +vpmaddwd_rr +( +src1 +. +fpu +( +) +src0 +. +encoding +( +) +dest +. +encoding +( +) +) +; +break +; +default +: +MOZ_CRASH +( +" +unexpected +operand +kind +" +) +; +} +} +void vpaddq ( const @@ -29909,6 +30174,152 @@ encoding ) ; } +void +vroundps +( +SSERoundingMode +mode +const +Operand +& +src +FloatRegister +dest +) +{ +MOZ_ASSERT +( +HasSSE41 +( +) +) +; +switch +( +src +. +kind +( +) +) +{ +case +Operand +: +: +FPREG +: +masm +. +vroundps_irr +( +( +X86Encoding +: +: +SSERoundingMode +) +mode +src +. +fpu +( +) +dest +. +encoding +( +) +) +; +break +; +default +: +MOZ_CRASH +( +" +unexpected +operand +kind +" +) +; +} +} +void +vroundpd +( +SSERoundingMode +mode +const +Operand +& +src +FloatRegister +dest +) +{ +MOZ_ASSERT +( +HasSSE41 +( +) +) +; +switch +( +src +. +kind +( +) +) +{ +case +Operand +: +: +FPREG +: +masm +. +vroundpd_irr +( +( +X86Encoding +: +: +SSERoundingMode +) +mode +src +. +fpu +( +) +dest +. +encoding +( +) +) +; +break +; +default +: +MOZ_CRASH +( +" +unexpected +operand +kind +" +) +; +} +} static X86Encoding : @@ -29992,9 +30403,7 @@ X86Encoding RoundingMode mode FloatRegister -src1 -FloatRegister -src0 +src FloatRegister dest ) @@ -30011,12 +30420,7 @@ masm vroundsd_irr ( mode -src1 -. -encoding -( -) -src0 +src . encoding ( @@ -30038,9 +30442,7 @@ X86Encoding RoundingMode mode FloatRegister -src1 -FloatRegister -src0 +src FloatRegister dest ) @@ -30057,12 +30459,7 @@ masm vroundss_irr ( mode -src1 -. -encoding -( -) -src0 +src . encoding ( diff --git a/js/src/jit/x86-shared/BaseAssembler-x86-shared.h b/js/src/jit/x86-shared/BaseAssembler-x86-shared.h index 431baa50cdd9a..917545b3ca907 100644 --- a/js/src/jit/x86-shared/BaseAssembler-x86-shared.h +++ b/js/src/jit/x86-shared/BaseAssembler-x86-shared.h @@ -4935,6 +4935,30 @@ dst ; } void +vpmaddwd_rr +( +XMMRegisterID +src1 +XMMRegisterID +src0 +XMMRegisterID +dst +) +{ +twoByteOpSimd +( +" +vpmaddwd +" +VEX_PD +OP2_PMADDWD_VdqWdq +src1 +src0 +dst +) +; +} +void vpmullw_rr ( XMMRegisterID @@ -23004,9 +23028,7 @@ vroundsd_irr RoundingMode mode XMMRegisterID -src1 -XMMRegisterID -src0 +src XMMRegisterID dst ) @@ -23020,8 +23042,8 @@ VEX_PD OP3_ROUNDSD_VsdWsd ESCAPE_3A mode -src1 -src0 +src +invalid_xmm dst ) ; @@ -23032,9 +23054,7 @@ vroundss_irr RoundingMode mode XMMRegisterID -src1 -XMMRegisterID -src0 +src XMMRegisterID dst ) @@ -23048,8 +23068,66 @@ VEX_PD OP3_ROUNDSS_VsdWsd ESCAPE_3A mode -src1 -src0 +src +invalid_xmm +dst +) +; +} +void +vroundps_irr +( +SSERoundingMode +mode +XMMRegisterID +src +XMMRegisterID +dst +) +{ +threeByteOpImmSimd +( +" +vroundps +" +VEX_PD +OP3_ROUNDPS_VpsWps +ESCAPE_3A +int +( +mode +) +src +invalid_xmm +dst +) +; +} +void +vroundpd_irr +( +SSERoundingMode +mode +XMMRegisterID +src +XMMRegisterID +dst +) +{ +threeByteOpImmSimd +( +" +vroundpd +" +VEX_PD +OP3_ROUNDPD_VpdWpd +ESCAPE_3A +int +( +mode +) +src +invalid_xmm dst ) ; diff --git a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp index cb7ab8a38320f..485bf78b69f53 100644 --- a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp +++ b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp @@ -14744,7 +14744,6 @@ roundingMode ) input output -output ) ; } @@ -14813,7 +14812,6 @@ roundingMode ) input output -output ) ; } @@ -19469,6 +19467,101 @@ lhsDest ; break ; +case +wasm +: +: +SimdOp +: +: +F32x4PMaxExperimental +: +masm +. +pseudoMaxFloat32x4 +( +rhs +lhsDest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F32x4PMinExperimental +: +masm +. +pseudoMinFloat32x4 +( +rhs +lhsDest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2PMaxExperimental +: +masm +. +pseudoMaxFloat64x2 +( +rhs +lhsDest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2PMinExperimental +: +masm +. +pseudoMinFloat64x2 +( +rhs +lhsDest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +I32x4DotSI16x8Experimental +: +masm +. +widenDotInt16x8 +( +rhs +lhsDest +) +; +break +; default : MOZ_CRASH @@ -23037,6 +23130,158 @@ dest ; break ; +case +wasm +: +: +SimdOp +: +: +F32x4CeilExperimental +: +masm +. +ceilFloat32x4 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F32x4FloorExperimental +: +masm +. +floorFloat32x4 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F32x4TruncExperimental +: +masm +. +truncFloat32x4 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F32x4NearestExperimental +: +masm +. +nearestFloat32x4 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2CeilExperimental +: +masm +. +ceilFloat64x2 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2FloorExperimental +: +masm +. +floorFloat64x2 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2TruncExperimental +: +masm +. +truncFloat64x2 +( +src +dest +) +; +break +; +case +wasm +: +: +SimdOp +: +: +F64x2NearestExperimental +: +masm +. +nearestFloat64x2 +( +src +dest +) +; +break +; default : MOZ_CRASH diff --git a/js/src/jit/x86-shared/Constants-x86-shared.h b/js/src/jit/x86-shared/Constants-x86-shared.h index 364d761a73b04..c0559f35ecc11 100644 --- a/js/src/jit/x86-shared/Constants-x86-shared.h +++ b/js/src/jit/x86-shared/Constants-x86-shared.h @@ -1212,6 +1212,8 @@ ConditionCmp_ORD Rounding modes for +ROUNDSS +/ ROUNDSD . enum @@ -1233,6 +1235,91 @@ RoundToZero ; / / +Rounding +modes +for +ROUNDPS +/ +ROUNDPD +. +Note +these +are +the +same +as +for +/ +/ +RoundingMode +above +but +incorporate +the +' +inexact +' +bit +which +says +not +to +signal +/ +/ +exceptions +for +lost +precision +. +It +' +s +not +obvious +that +this +bit +is +needed +; +it +/ +/ +was +however +suggested +in +the +wasm +SIMD +proposal +that +led +to +these +encodings +. +enum +class +SSERoundingMode +{ +RoundToNearest += +0x08 +RoundDown += +0x09 +RoundUp += +0x0A +RoundToZero += +0x0B +} +; +/ +/ Test whether the diff --git a/js/src/jit/x86-shared/Encoding-x86-shared.h b/js/src/jit/x86-shared/Encoding-x86-shared.h index 1de38194f2c15..8219ca9f2ceeb 100644 --- a/js/src/jit/x86-shared/Encoding-x86-shared.h +++ b/js/src/jit/x86-shared/Encoding-x86-shared.h @@ -1310,6 +1310,9 @@ OP2_PSLLQ_VdqWdq OP2_PMULUDQ_VdqWdq = 0xF4 +OP2_PMADDWD_VdqWdq += +0xF5 OP2_PSUBB_VdqWdq = 0xF8 @@ -1339,6 +1342,12 @@ ThreeByteOpcodeID OP3_PSHUFB_VdqWdq = 0x00 +OP3_ROUNDPS_VpsWps += +0x08 +OP3_ROUNDPD_VpdWpd += +0x09 OP3_ROUNDSS_VsdWsd = 0x0A diff --git a/js/src/jit/x86-shared/MacroAssembler-x86-shared-inl.h b/js/src/jit/x86-shared/MacroAssembler-x86-shared-inl.h index 84513de5790cc..1f075de0c0f35 100644 --- a/js/src/jit/x86-shared/MacroAssembler-x86-shared-inl.h +++ b/js/src/jit/x86-shared/MacroAssembler-x86-shared-inl.h @@ -11525,7 +11525,7 @@ lhsDest NaN - propagating -maxium +maximum void MacroAssembler : @@ -11586,6 +11586,368 @@ lhsDest } / / +Compare +- +based +minimum +void +MacroAssembler +: +: +pseudoMinFloat32x4 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +{ +vminps +( +Operand +( +rhs +) +lhsDest +lhsDest +) +; +} +void +MacroAssembler +: +: +pseudoMinFloat64x2 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +{ +vminpd +( +Operand +( +rhs +) +lhsDest +lhsDest +) +; +} +/ +/ +Compare +- +based +maximum +void +MacroAssembler +: +: +pseudoMaxFloat32x4 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +{ +vmaxps +( +Operand +( +rhs +) +lhsDest +lhsDest +) +; +} +void +MacroAssembler +: +: +pseudoMaxFloat64x2 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +{ +vmaxpd +( +Operand +( +rhs +) +lhsDest +lhsDest +) +; +} +void +MacroAssembler +: +: +widenDotInt16x8 +( +FloatRegister +rhs +FloatRegister +lhsDest +) +{ +vpmaddwd +( +Operand +( +rhs +) +lhsDest +lhsDest +) +; +} +/ +/ +Rounding +void +MacroAssembler +: +: +ceilFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundps +( +Assembler +: +: +SSERoundingMode +: +: +Ceil +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +ceilFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundpd +( +Assembler +: +: +SSERoundingMode +: +: +Ceil +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +floorFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundps +( +Assembler +: +: +SSERoundingMode +: +: +Floor +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +floorFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundpd +( +Assembler +: +: +SSERoundingMode +: +: +Floor +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +truncFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundps +( +Assembler +: +: +SSERoundingMode +: +: +Trunc +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +truncFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundpd +( +Assembler +: +: +SSERoundingMode +: +: +Trunc +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +nearestFloat32x4 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundps +( +Assembler +: +: +SSERoundingMode +: +: +Nearest +Operand +( +src +) +dest +) +; +} +void +MacroAssembler +: +: +nearestFloat64x2 +( +FloatRegister +src +FloatRegister +dest +) +{ +vroundpd +( +Assembler +: +: +SSERoundingMode +: +: +Nearest +Operand +( +src +) +dest +) +; +} +/ +/ Floating add void diff --git a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp index 03a4a1fd1b9b7..f6fc7d890869f 100644 --- a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp +++ b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp @@ -10127,7 +10127,6 @@ X86Encoding RoundDown src scratch -scratch ) ; truncateFloat32ToInt32 @@ -10464,7 +10463,6 @@ X86Encoding RoundDown src scratch -scratch ) ; truncateDoubleToInt32 @@ -10888,7 +10886,6 @@ X86Encoding RoundUp src scratch -scratch ) ; truncateFloat32ToInt32 @@ -11227,7 +11224,6 @@ X86Encoding RoundUp src scratch -scratch ) ; truncateDoubleToInt32 @@ -12074,7 +12070,6 @@ X86Encoding RoundDown temp scratch -scratch ) ; / @@ -12705,7 +12700,6 @@ X86Encoding RoundDown temp scratch -scratch ) ; / diff --git a/js/src/jit/x86/MacroAssembler-x86.cpp b/js/src/jit/x86/MacroAssembler-x86.cpp index 9f508e09ac8a8..9f59bf7a7fd46 100644 --- a/js/src/jit/x86/MacroAssembler-x86.cpp +++ b/js/src/jit/x86/MacroAssembler-x86.cpp @@ -4368,6 +4368,20 @@ Scalar : Float32 : +/ +/ +vmovss +does +the +right +thing +also +for +access +. +isZeroExtendSimdLoad +( +) vmovss ( srcAddr @@ -4386,6 +4400,20 @@ Scalar : Float64 : +/ +/ +vmovsd +does +the +right +thing +also +for +access +. +isZeroExtendSimdLoad +( +) vmovsd ( srcAddr diff --git a/js/src/wasm/WasmBaselineCompile.cpp b/js/src/wasm/WasmBaselineCompile.cpp index 52b61718d85c5..5b282a1f7cf27 100644 --- a/js/src/wasm/WasmBaselineCompile.cpp +++ b/js/src/wasm/WasmBaselineCompile.cpp @@ -43087,7 +43087,6 @@ roundingMode ) f0 f0 -f0 ) ; # @@ -43136,7 +43135,6 @@ roundingMode ) f0 f0 -f0 ) ; # @@ -55265,6 +55263,17 @@ viewType ; MOZ_MUST_USE bool +emitLoadZero +( +Scalar +: +: +Type +viewType +) +; +MOZ_MUST_USE +bool emitLoadExtend ( Scalar @@ -80710,6 +80719,116 @@ temp } static void +PMinF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rsd +) +{ +masm +. +pseudoMinFloat32x4 +( +rs +rsd +) +; +} +static +void +PMinF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rsd +) +{ +masm +. +pseudoMinFloat64x2 +( +rs +rsd +) +; +} +static +void +PMaxF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rsd +) +{ +masm +. +pseudoMaxFloat32x4 +( +rs +rsd +) +; +} +static +void +PMaxF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rsd +) +{ +masm +. +pseudoMaxFloat64x2 +( +rs +rsd +) +; +} +static +void +DotI16x8 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rsd +) +{ +masm +. +widenDotInt16x8 +( +rs +rsd +) +; +} +static +void CmpI8x16 ( MacroAssembler @@ -81172,6 +81291,182 @@ rd } static void +CeilF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +ceilFloat32x4 +( +rs +rd +) +; +} +static +void +FloorF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +floorFloat32x4 +( +rs +rd +) +; +} +static +void +TruncF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +truncFloat32x4 +( +rs +rd +) +; +} +static +void +NearestF32x4 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +nearestFloat32x4 +( +rs +rd +) +; +} +static +void +CeilF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +ceilFloat64x2 +( +rs +rd +) +; +} +static +void +FloorF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +floorFloat64x2 +( +rs +rd +) +; +} +static +void +TruncF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +truncFloat64x2 +( +rs +rd +) +; +} +static +void +NearestF64x2 +( +MacroAssembler +& +masm +RegV128 +rs +RegV128 +rd +) +{ +masm +. +nearestFloat64x2 +( +rs +rd +) +; +} +static +void NotV128 ( MacroAssembler @@ -83964,6 +84259,101 @@ bool BaseCompiler : : +emitLoadZero +( +Scalar +: +: +Type +viewType +) +{ +/ +/ +LoadZero +has +the +structure +of +LoadSplat +LinearMemoryAddress +< +Nothing +> +addr +; +if +( +! +iter_ +. +readLoadSplat +( +Scalar +: +: +byteSize +( +viewType +) +& +addr +) +) +{ +return +false +; +} +if +( +deadCode_ +) +{ +return +true +; +} +MemoryAccessDesc +access +( +viewType +addr +. +align +addr +. +offset +bytecodeOffset +( +) +) +; +access +. +setZeroExtendSimd128Load +( +) +; +return +loadCommon +( +& +access +AccessCheck +( +) +ValType +: +: +V128 +) +; +} +bool +BaseCompiler +: +: emitLoadExtend ( Scalar @@ -85331,6 +85721,23 @@ while endif # define +CHECK_EXPERIMENTAL_SIMD +( +) +\ +if +( +! +SimdExperimentalEnabled +) +{ +\ +break +; +\ +} +# +define CHECK ( E @@ -92998,6 +93405,116 @@ uint32_t SimdOp : : +F32x4PMaxExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorBinary +( +emitVectorBinop +PMaxF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F32x4PMinExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorBinary +( +emitVectorBinop +PMinF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2PMaxExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorBinary +( +emitVectorBinop +PMaxF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2PMinExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorBinary +( +emitVectorBinop +PMinF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: +I32x4DotSI16x8Experimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorBinary +( +emitVectorBinop +DotI16x8 +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16Neg ) : @@ -93466,6 +93983,182 @@ uint32_t SimdOp : : +F32x4CeilExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +CeilF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F32x4FloorExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +FloorF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F32x4TruncExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +TruncF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F32x4NearestExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +NearestF32x4 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2CeilExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +CeilF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2FloorExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +FloorF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2TruncExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +TruncF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: +F64x2NearestExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +dispatchVectorUnary +( +emitVectorUnop +NearestF64x2 +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16Shl ) : @@ -93966,6 +94659,54 @@ uint32_t SimdOp : : +V128Load32ZeroExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +emitLoadZero +( +Scalar +: +: +Float32 +) +) +; +case +uint32_t +( +SimdOp +: +: +V128Load64ZeroExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK_NEXT +( +emitLoadZero +( +Scalar +: +: +Float64 +) +) +; +case +uint32_t +( +SimdOp +: +: V128Store ) : @@ -96324,6 +97065,9 @@ undef CHECK_POINTER_COUNT # undef +CHECK_EXPERIMENTAL_SIMD +# +undef dispatchBinary # undef diff --git a/js/src/wasm/WasmConstants.h b/js/src/wasm/WasmConstants.h index 20874be1911d2..f6c3e8102f364 100644 --- a/js/src/wasm/WasmConstants.h +++ b/js/src/wasm/WasmConstants.h @@ -1693,6 +1693,85 @@ in May 2020 . +/ +/ +Opcodes +with +suffix +' +Experimental +' +are +proposed +but +not +standardized +and +are +/ +/ +compatible +with +those +same +opcodes +in +V8 +. +No +opcode +labeled +' +Experimental +' +/ +/ +will +ship +in +a +Release +build +where +SIMD +is +enabled +by +default +. +/ +/ +/ +/ +Once +SIMD +ships +default +- +on +in +release +builds +the +following +flag +must +be +set +/ +/ +to +false +for +RELEASE_OR_BETA +. +static +constexpr +bool +SimdExperimentalEnabled += +true +; enum class SimdOp @@ -2329,9 +2408,7 @@ I32x4MaxS I32x4MaxU = 0xb9 -/ -/ -AvgrS +I32x4DotSI16x8Experimental = 0xba / @@ -2465,44 +2542,28 @@ MinS MinU = 0xd7 -/ -/ -MaxS +F32x4CeilExperimental = 0xd8 -/ -/ -MaxU +F32x4FloorExperimental = 0xd9 -/ -/ -AvgrS +F32x4TruncExperimental = 0xda -/ -/ -AvgrU +F32x4NearestExperimental = 0xdb -/ -/ -Unused +F64x2CeilExperimental = 0xdc -/ -/ -Unused +F64x2FloorExperimental = 0xdd -/ -/ -Unused +F64x2TruncExperimental = 0xde -/ -/ -Unused +F64x2NearestExperimental = 0xdf F32x4Abs @@ -2537,14 +2598,10 @@ F32x4Min F32x4Max = 0xe9 -/ -/ -PMin +F32x4PMinExperimental = 0xea -/ -/ -PMax +F32x4PMaxExperimental = 0xeb F64x2Abs @@ -2579,14 +2636,10 @@ F64x2Min F64x2Max = 0xf5 -/ -/ -PMin +F64x2PMinExperimental = 0xf6 -/ -/ -PMax +F64x2PMaxExperimental = 0xf7 I32x4TruncSSatF32x4 @@ -2601,11 +2654,17 @@ F32x4ConvertSI32x4 F32x4ConvertUI32x4 = 0xfb +V128Load32ZeroExperimental += +0xfc +V128Load64ZeroExperimental += +0xfd / / Unused = -0xfc +0xfe and up Limit diff --git a/js/src/wasm/WasmIonCompile.cpp b/js/src/wasm/WasmIonCompile.cpp index 8b04040519fdc..c5445b6ee2be1 100644 --- a/js/src/wasm/WasmIonCompile.cpp +++ b/js/src/wasm/WasmIonCompile.cpp @@ -5233,6 +5233,74 @@ op ) ; } +MDefinition +* +loadZeroSimd128 +( +Scalar +: +: +Type +viewType +size_t +numBytes +const +LinearMemoryAddress +< +MDefinition +* +> +& +addr +) +{ +if +( +inDeadCode +( +) +) +{ +return +nullptr +; +} +MemoryAccessDesc +access +( +viewType +addr +. +align +addr +. +offset +bytecodeIfNotAsmJS +( +) +) +; +access +. +setZeroExtendSimd128Load +( +) +; +return +load +( +addr +. +base +& +access +ValType +: +: +V128 +) +; +} # endif / @@ -25521,6 +25589,72 @@ return true ; } +static +bool +EmitLoadZeroSimd128 +( +FunctionCompiler +& +f +Scalar +: +: +Type +viewType +size_t +numBytes +) +{ +LinearMemoryAddress +< +MDefinition +* +> +addr +; +if +( +! +f +. +iter +( +) +. +readLoadSplat +( +numBytes +& +addr +) +) +{ +return +false +; +} +f +. +iter +( +) +. +setResult +( +f +. +loadZeroSimd128 +( +viewType +numBytes +addr +) +) +; +return +true +; +} # endif static @@ -25574,6 +25708,34 @@ false ; \ break +# +define +CHECK_EXPERIMENTAL_SIMD +( +) +\ +if +( +! +SimdExperimentalEnabled +) +{ +\ +return +f +. +iter +( +) +. +unrecognizedOpcode +( +& +op +) +; +\ +} while ( true @@ -30893,6 +31055,40 @@ uint32_t SimdOp : : +I32x4DotSI16x8Experimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +EmitBinarySimd128 +( +f +/ +* +commutative += +* +/ +true +SimdOp +( +op +. +b1 +) +) +) +; +case +uint32_t +( +SimdOp +: +: V128AndNot ) : @@ -31364,6 +31560,67 @@ uint32_t SimdOp : : +F32x4PMaxExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4PMinExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2PMaxExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2PMinExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +EmitBinarySimd128 +( +f +/ +* +commutative += +* +/ +false +SimdOp +( +op +. +b1 +) +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16Splat ) : @@ -31738,6 +31995,96 @@ uint32_t SimdOp : : +F32x4CeilExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4FloorExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4TruncExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4NearestExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2CeilExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2FloorExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2TruncExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2NearestExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +EmitUnarySimd128 +( +f +SimdOp +( +op +. +b1 +) +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16AnyTrue ) : @@ -32505,6 +32852,58 @@ b1 ) ) ; +case +uint32_t +( +SimdOp +: +: +V128Load32ZeroExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +EmitLoadZeroSimd128 +( +f +Scalar +: +: +Float32 +4 +) +) +; +case +uint32_t +( +SimdOp +: +: +V128Load64ZeroExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +EmitLoadZeroSimd128 +( +f +Scalar +: +: +Float64 +8 +) +) +; default : return @@ -35498,6 +35897,9 @@ unreachable # undef CHECK +# +undef +CHECK_EXPERIMENTAL_SIMD } bool wasm diff --git a/js/src/wasm/WasmOpIter.cpp b/js/src/wasm/WasmOpIter.cpp index 9bbfcc0a1746f..0a5116d34d76f 100644 --- a/js/src/wasm/WasmOpIter.cpp +++ b/js/src/wasm/WasmOpIter.cpp @@ -2578,6 +2578,36 @@ SimdOp : V8x16Swizzle : +case +SimdOp +: +: +F32x4PMinExperimental +: +case +SimdOp +: +: +F32x4PMaxExperimental +: +case +SimdOp +: +: +F64x2PMinExperimental +: +case +SimdOp +: +: +F64x2PMaxExperimental +: +case +SimdOp +: +: +I32x4DotSI16x8Experimental +: WASM_SIMD_OP ( OpKind @@ -2742,6 +2772,54 @@ SimdOp : I32x4Abs : +case +SimdOp +: +: +F32x4CeilExperimental +: +case +SimdOp +: +: +F32x4FloorExperimental +: +case +SimdOp +: +: +F32x4TruncExperimental +: +case +SimdOp +: +: +F32x4NearestExperimental +: +case +SimdOp +: +: +F64x2CeilExperimental +: +case +SimdOp +: +: +F64x2FloorExperimental +: +case +SimdOp +: +: +F64x2TruncExperimental +: +case +SimdOp +: +: +F64x2NearestExperimental +: WASM_SIMD_OP ( OpKind @@ -2938,6 +3016,18 @@ SimdOp : I64x2LoadU32x2 : +case +SimdOp +: +: +V128Load32ZeroExperimental +: +case +SimdOp +: +: +V128Load64ZeroExperimental +: WASM_SIMD_OP ( OpKind diff --git a/js/src/wasm/WasmValidate.cpp b/js/src/wasm/WasmValidate.cpp index 312fe5082ed8b..ef80d5b0158ab 100644 --- a/js/src/wasm/WasmValidate.cpp +++ b/js/src/wasm/WasmValidate.cpp @@ -2738,6 +2738,30 @@ false ; \ break +# +define +CHECK_EXPERIMENTAL_SIMD +( +) +\ +if +( +! +SimdExperimentalEnabled +) +{ +\ +return +iter +. +unrecognizedOpcode +( +& +op +) +; +\ +} while ( true @@ -7671,6 +7695,72 @@ uint32_t SimdOp : : +F32x4PMaxExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4PMinExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2PMaxExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2PMinExperimental +) +: +case +uint32_t +( +SimdOp +: +: +I32x4DotSI16x8Experimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +iter +. +readBinary +( +ValType +: +: +V128 +& +nothing +& +nothing +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16Neg ) : @@ -7920,6 +8010,97 @@ uint32_t SimdOp : : +F32x4CeilExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4FloorExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4TruncExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F32x4NearestExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2CeilExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2FloorExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2TruncExperimental +) +: +case +uint32_t +( +SimdOp +: +: +F64x2NearestExperimental +) +: +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +iter +. +readUnary +( +ValType +: +: +V128 +& +nothing +) +) +; +case +uint32_t +( +SimdOp +: +: I8x16Shl ) : @@ -8408,6 +8589,72 @@ nothing ) ; } +case +uint32_t +( +SimdOp +: +: +V128Load32ZeroExperimental +) +: +{ +LinearMemoryAddress +< +Nothing +> +addr +; +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +iter +. +readLoadSplat +( +4 +& +addr +) +) +; +} +case +uint32_t +( +SimdOp +: +: +V128Load64ZeroExperimental +) +: +{ +LinearMemoryAddress +< +Nothing +> +addr +; +CHECK_EXPERIMENTAL_SIMD +( +) +; +CHECK +( +iter +. +readLoadSplat +( +8 +& +addr +) +) +; +} default : return @@ -10703,6 +10950,9 @@ unreachable # undef CHECK +# +undef +CHECK_EXPERIMENTAL_SIMD } bool wasm