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OptionalProject.qsf
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OptionalProject.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 13:01:41 November 22, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# OptionalProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY OptionalProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:41 NOVEMBER 22, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_N3 -to vga_h_sync
set_location_assignment PIN_N1 -to vga_v_sync
set_location_assignment PIN_P11 -to clk
set_location_assignment PIN_B8 -to button_up
set_location_assignment PIN_A7 -to button_down
set_location_assignment PIN_F15 -to button_left
set_location_assignment PIN_C10 -to button_right
set_global_assignment -name VERILOG_FILE button_debouncer.v
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_location_assignment PIN_A14 -to button_reset
set_global_assignment -name ALLOW_REGISTER_RETIMING ON
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 1024
set_location_assignment PIN_AA1 -to vga_R[0]
set_location_assignment PIN_V1 -to vga_R[1]
set_location_assignment PIN_Y2 -to vga_R[2]
set_location_assignment PIN_Y1 -to vga_R[3]
set_location_assignment PIN_W1 -to vga_G[0]
set_location_assignment PIN_T2 -to vga_G[1]
set_location_assignment PIN_R2 -to vga_G[2]
set_location_assignment PIN_R1 -to vga_G[3]
set_location_assignment PIN_P1 -to vga_B[0]
set_location_assignment PIN_T1 -to vga_B[1]
set_location_assignment PIN_P4 -to vga_B[2]
set_location_assignment PIN_N2 -to vga_B[3]
set_global_assignment -name OPTIMIZE_TIMING OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top