{"payload":{"header_redesign_enabled":false,"results":[{"id":"511793998","archived":false,"color":"#DAE1C2","followers":1,"has_funding_file":false,"hl_name":"mauer4/Personal-Project-Verilog-CLOCK","hl_trunc_description":"This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous desi…","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":511793998,"name":"Personal-Project-Verilog-CLOCK","owner_id":89616796,"owner_login":"mauer4","updated_at":"2022-09-28T01:46:40.784Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","digital-logic","modelsim","system-verilog","quartus","hardware-design","verilog-testbenches"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":117,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amauer4%252FPersonal-Project-Verilog-CLOCK%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/mauer4/Personal-Project-Verilog-CLOCK/star":{"post":"AEA_vwoc3tBbMuAdy3vqFyVkTIb13kX1iDYi5J6AyGICYpXuuQsQbh77a-8QVL93_L_wE7aLsIwUDvZ4VII6EA"},"/mauer4/Personal-Project-Verilog-CLOCK/unstar":{"post":"YDSBnG_HAU8uQCo_S6VPRmdfxRo3dy6ZhkzTvJ-iUQkkss_Sax85xLWXyc-ggkTqUbl34WL3TrS7ZttleYz2IQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"zERA0VMmkAFVBXYi_Mf5j_YdKISSnvoqg_1ynTsdc6i6IZp9wHU3mWMk3Od7i3OI637Z9hU3Rwjapi7pOVNInQ"}}},"title":"Repository search results"}