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pci.c
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pci.c
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/******************************************************************************
*
* Copyright( c ) 2009-2012 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "core.h"
#include "pci.h"
#include "base.h"
#include "ps.h"
#include "efuse.h"
#include <linux/export.h>
#include <linux/kmemleak.h>
#include <linux/module.h>
MODULE_AUTHOR( "lizhaoming <chaoming_li@realsil.com.cn>" );
MODULE_AUTHOR( "Realtek WlanFAE <wlanfae@realtek.com>" );
MODULE_AUTHOR( "Larry Finger <Larry.FInger@lwfinger.net>" );
MODULE_LICENSE( "GPL" );
MODULE_DESCRIPTION( "PCI basic driver for rtlwifi" );
static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
PCI_VENDOR_ID_INTEL,
PCI_VENDOR_ID_ATI,
PCI_VENDOR_ID_AMD,
PCI_VENDOR_ID_SI
};
static const u8 ac_to_hwq[] = {
VO_QUEUE,
VI_QUEUE,
BE_QUEUE,
BK_QUEUE
};
static u8 _rtl_mac_to_hwqueue( struct ieee80211_hw *hw,
struct sk_buff *skb )
{
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
__le16 fc = rtl_get_fc( skb );
u8 queue_index = skb_get_queue_mapping( skb );
if ( unlikely( ieee80211_is_beacon( fc ) ) )
return BEACON_QUEUE;
if ( ieee80211_is_mgmt( fc ) || ieee80211_is_ctl( fc ) )
return MGNT_QUEUE;
if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE )
if ( ieee80211_is_nullfunc( fc ) )
return HIGH_QUEUE;
return ac_to_hwq[queue_index];
}
/* Update PCI dependent default settings*/
static void _rtl_pci_update_default_setting( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
struct rtl_ps_ctl *ppsc = rtl_psc( rtl_priv( hw ) );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
u8 init_aspm;
ppsc->reg_rfps_level = 0;
ppsc->support_aspm = false;
/*Update PCI ASPM setting */
ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
switch ( rtlpci->const_pci_aspm ) {
case 0:
/*No ASPM */
break;
case 1:
/*ASPM dynamically enabled/disable. */
ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
break;
case 2:
/*ASPM with Clock Req dynamically enabled/disable. */
ppsc->reg_rfps_level |= ( RT_RF_LPS_LEVEL_ASPM |
RT_RF_OFF_LEVL_CLK_REQ );
break;
case 3:
/*
* Always enable ASPM and Clock Req
* from initialization to halt.
* */
ppsc->reg_rfps_level &= ~( RT_RF_LPS_LEVEL_ASPM );
ppsc->reg_rfps_level |= ( RT_RF_PS_LEVEL_ALWAYS_ASPM |
RT_RF_OFF_LEVL_CLK_REQ );
break;
case 4:
/*
* Always enable ASPM without Clock Req
* from initialization to halt.
* */
ppsc->reg_rfps_level &= ~( RT_RF_LPS_LEVEL_ASPM |
RT_RF_OFF_LEVL_CLK_REQ );
ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
break;
}
ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
/*Update Radio OFF setting */
switch ( rtlpci->const_hwsw_rfoff_d3 ) {
case 1:
if ( ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM )
ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
break;
case 2:
if ( ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM )
ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
break;
case 3:
ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
break;
}
/*Set HW definition to determine if it supports ASPM. */
switch ( rtlpci->const_support_pciaspm ) {
case 0:{
/*Not support ASPM. */
bool support_aspm = false;
ppsc->support_aspm = support_aspm;
break;
}
case 1:{
/*Support ASPM. */
bool support_aspm = true;
bool support_backdoor = true;
ppsc->support_aspm = support_aspm;
/*if ( priv->oem_id == RT_CID_TOSHIBA &&
!priv->ndis_adapter.amd_l1_patch )
support_backdoor = false; */
ppsc->support_backdoor = support_backdoor;
break;
}
case 2:
/*ASPM value set by chipset. */
if ( pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ) {
bool support_aspm = true;
ppsc->support_aspm = support_aspm;
}
break;
default:
RT_TRACE( rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n" );
break;
}
/* toshiba aspm issue, toshiba will set aspm selfly
* so we should not set aspm in driver */
pci_read_config_byte( rtlpci->pdev, 0x80, &init_aspm );
if ( rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
init_aspm == 0x43 )
ppsc->support_aspm = false;
}
static bool _rtl_pci_platform_switch_device_pci_aspm(
struct ieee80211_hw *hw,
u8 value )
{
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
if ( rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE )
value |= 0x40;
pci_write_config_byte( rtlpci->pdev, 0x80, value );
return false;
}
/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
static void _rtl_pci_switch_clk_req( struct ieee80211_hw *hw, u8 value )
{
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
pci_write_config_byte( rtlpci->pdev, 0x81, value );
if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE )
udelay( 100 );
}
/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
static void rtl_pci_disable_aspm( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
struct rtl_ps_ctl *ppsc = rtl_psc( rtl_priv( hw ) );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
/*Retrieve original configuration settings. */
u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
pcibridge_linkctrlreg;
u16 aspmlevel = 0;
u8 tmp_u1b = 0;
if ( !ppsc->support_aspm )
return;
if ( pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN ) {
RT_TRACE( rtlpriv, COMP_POWER, DBG_TRACE,
"PCI(Bridge) UNKNOWN\n" );
return;
}
if ( ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ ) {
RT_CLEAR_PS_LEVEL( ppsc, RT_RF_OFF_LEVL_CLK_REQ );
_rtl_pci_switch_clk_req( hw, 0x0 );
}
/*for promising device will in L0 state after an I/O. */
pci_read_config_byte( rtlpci->pdev, 0x80, &tmp_u1b );
/*Set corresponding value. */
aspmlevel |= BIT( 0 ) | BIT( 1 );
linkctrl_reg &= ~aspmlevel;
pcibridge_linkctrlreg &= ~( BIT( 0 ) | BIT( 1 ) );
_rtl_pci_platform_switch_device_pci_aspm( hw, linkctrl_reg );
udelay( 50 );
/*4 Disable Pci Bridge ASPM */
pci_write_config_byte( rtlpci->pdev, ( num4bytes << 2 ),
pcibridge_linkctrlreg );
udelay( 50 );
}
/*
*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
*power saving We should follow the sequence to enable
*RTL8192SE first then enable Pci Bridge ASPM
*or the system will show bluescreen.
*/
static void rtl_pci_enable_aspm( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
struct rtl_ps_ctl *ppsc = rtl_psc( rtl_priv( hw ) );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
u16 aspmlevel;
u8 u_pcibridge_aspmsetting;
u8 u_device_aspmsetting;
if ( !ppsc->support_aspm )
return;
if ( pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN ) {
RT_TRACE( rtlpriv, COMP_POWER, DBG_TRACE,
"PCI(Bridge) UNKNOWN\n" );
return;
}
/*4 Enable Pci Bridge ASPM */
u_pcibridge_aspmsetting =
pcipriv->ndis_adapter.pcibridge_linkctrlreg |
rtlpci->const_hostpci_aspm_setting;
if ( pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL )
u_pcibridge_aspmsetting &= ~BIT( 0 );
pci_write_config_byte( rtlpci->pdev, ( num4bytes << 2 ),
u_pcibridge_aspmsetting );
RT_TRACE( rtlpriv, COMP_INIT, DBG_LOUD,
"PlatformEnableASPM(): Write reg[%x] = %x\n",
( pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10 ),
u_pcibridge_aspmsetting );
udelay( 50 );
/*Get ASPM level ( with/without Clock Req ) */
aspmlevel = rtlpci->const_devicepci_aspm_setting;
u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
/*_rtl_pci_platform_switch_device_pci_aspm( dev,*/
/*( priv->ndis_adapter.linkctrl_reg | ASPMLevel ) ); */
u_device_aspmsetting |= aspmlevel;
_rtl_pci_platform_switch_device_pci_aspm( hw, u_device_aspmsetting );
if ( ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ ) {
_rtl_pci_switch_clk_req( hw, ( ppsc->reg_rfps_level &
RT_RF_OFF_LEVL_CLK_REQ ) ? 1 : 0 );
RT_SET_PS_LEVEL( ppsc, RT_RF_OFF_LEVL_CLK_REQ );
}
udelay( 100 );
}
static bool rtl_pci_get_amd_l1_patch( struct ieee80211_hw *hw )
{
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
bool status = false;
u8 offset_e0;
unsigned offset_e4;
pci_write_config_byte( rtlpci->pdev, 0xe0, 0xa0 );
pci_read_config_byte( rtlpci->pdev, 0xe0, &offset_e0 );
if ( offset_e0 == 0xA0 ) {
pci_read_config_dword( rtlpci->pdev, 0xe4, &offset_e4 );
if ( offset_e4 & BIT( 23 ) )
status = true;
}
return status;
}
static bool rtl_pci_check_buddy_priv( struct ieee80211_hw *hw,
struct rtl_priv **buddy_priv )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
bool find_buddy_priv = false;
struct rtl_priv *tpriv = NULL;
struct rtl_pci_priv *tpcipriv = NULL;
if ( !list_empty( &rtlpriv->glb_var->glb_priv_list ) ) {
list_for_each_entry( tpriv, &rtlpriv->glb_var->glb_priv_list,
list ) {
if ( tpriv ) {
tpcipriv = ( struct rtl_pci_priv * )tpriv->priv;
RT_TRACE( rtlpriv, COMP_INIT, DBG_LOUD,
"pcipriv->ndis_adapter.funcnumber %x\n",
pcipriv->ndis_adapter.funcnumber );
RT_TRACE( rtlpriv, COMP_INIT, DBG_LOUD,
"tpcipriv->ndis_adapter.funcnumber %x\n",
tpcipriv->ndis_adapter.funcnumber );
if ( ( pcipriv->ndis_adapter.busnumber ==
tpcipriv->ndis_adapter.busnumber ) &&
( pcipriv->ndis_adapter.devnumber ==
tpcipriv->ndis_adapter.devnumber ) &&
( pcipriv->ndis_adapter.funcnumber !=
tpcipriv->ndis_adapter.funcnumber ) ) {
find_buddy_priv = true;
break;
}
}
}
}
RT_TRACE( rtlpriv, COMP_INIT, DBG_LOUD,
"find_buddy_priv %d\n", find_buddy_priv );
if ( find_buddy_priv )
*buddy_priv = tpriv;
return find_buddy_priv;
}
static void rtl_pci_get_linkcontrol_field( struct ieee80211_hw *hw )
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
struct rtl_pci *rtlpci = rtl_pcidev( pcipriv );
u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
u8 linkctrl_reg;
u8 num4bbytes;
num4bbytes = ( capabilityoffset + 0x10 ) / 4;
/*Read Link Control Register */
pci_read_config_byte( rtlpci->pdev, ( num4bbytes << 2 ), &linkctrl_reg );
pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
}
static void rtl_pci_parse_configuration( struct pci_dev *pdev,
struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *pcipriv = rtl_pcipriv( hw );
u8 tmp;
u16 linkctrl_reg;
/*Link Control Register */
pcie_capability_read_word( pdev, PCI_EXP_LNKCTL, &linkctrl_reg );
pcipriv->ndis_adapter.linkctrl_reg = ( u8 )linkctrl_reg;
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
pcipriv->ndis_adapter.linkctrl_reg );
pci_read_config_byte( pdev, 0x98, &tmp );
tmp |= BIT( 4 );
pci_write_config_byte( pdev, 0x98, tmp );
tmp = 0x17;
pci_write_config_byte( pdev, 0x70f, tmp );
}
static void rtl_pci_init_aspm( struct ieee80211_hw *hw )
{
struct rtl_ps_ctl *ppsc = rtl_psc( rtl_priv( hw ) );
_rtl_pci_update_default_setting( hw );
if ( ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM ) {
/*Always enable ASPM & Clock Req. */
rtl_pci_enable_aspm( hw );
RT_SET_PS_LEVEL( ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM );
}
}
static void _rtl_pci_io_handler_init( struct device *dev,
struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
rtlpriv->io.dev = dev;
rtlpriv->io.write8_async = pci_write8_async;
rtlpriv->io.write16_async = pci_write16_async;
rtlpriv->io.write32_async = pci_write32_async;
rtlpriv->io.read8_sync = pci_read8_sync;
rtlpriv->io.read16_sync = pci_read16_sync;
rtlpriv->io.read32_sync = pci_read32_sync;
}
static bool _rtl_update_earlymode_info( struct ieee80211_hw *hw,
struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct ieee80211_tx_info *info = IEEE80211_SKB_CB( skb );
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
struct sk_buff *next_skb;
u8 additionlen = FCS_LEN;
/* here open is 4, wep/tkip is 8, aes is 12*/
if ( info->control.hw_key )
additionlen += info->control.hw_key->icv_len;
/* The most skb num is 6 */
tcb_desc->empkt_num = 0;
spin_lock_bh( &rtlpriv->locks.waitq_lock );
skb_queue_walk( &rtlpriv->mac80211.skb_waitq[tid], next_skb ) {
struct ieee80211_tx_info *next_info;
next_info = IEEE80211_SKB_CB( next_skb );
if ( next_info->flags & IEEE80211_TX_CTL_AMPDU ) {
tcb_desc->empkt_len[tcb_desc->empkt_num] =
next_skb->len + additionlen;
tcb_desc->empkt_num++;
} else {
break;
}
if ( skb_queue_is_last( &rtlpriv->mac80211.skb_waitq[tid],
next_skb ) )
break;
if ( tcb_desc->empkt_num >= rtlhal->max_earlymode_num )
break;
}
spin_unlock_bh( &rtlpriv->locks.waitq_lock );
return true;
}
/* just for early mode now */
static void _rtl_pci_tx_chk_waitq( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
struct sk_buff *skb = NULL;
struct ieee80211_tx_info *info = NULL;
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
int tid;
if ( !rtlpriv->rtlhal.earlymode_enable )
return;
if ( rtlpriv->dm.supp_phymode_switch &&
( rtlpriv->easy_concurrent_ctl.switch_in_process ||
( rtlpriv->buddy_priv &&
rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process ) ) )
return;
/* we juse use em for BE/BK/VI/VO */
for ( tid = 7; tid >= 0; tid-- ) {
u8 hw_queue = ac_to_hwq[rtl_tid_to_ac( tid )];
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
while ( !mac->act_scanning &&
rtlpriv->psc.rfpwr_state == ERFON ) {
struct rtl_tcb_desc tcb_desc;
memset( &tcb_desc, 0, sizeof( struct rtl_tcb_desc ) );
spin_lock_bh( &rtlpriv->locks.waitq_lock );
if ( !skb_queue_empty( &mac->skb_waitq[tid] ) &&
( ring->entries - skb_queue_len( &ring->queue ) >
rtlhal->max_earlymode_num ) ) {
skb = skb_dequeue( &mac->skb_waitq[tid] );
} else {
spin_unlock_bh( &rtlpriv->locks.waitq_lock );
break;
}
spin_unlock_bh( &rtlpriv->locks.waitq_lock );
/* Some macaddr can't do early mode. like
* multicast/broadcast/no_qos data */
info = IEEE80211_SKB_CB( skb );
if ( info->flags & IEEE80211_TX_CTL_AMPDU )
_rtl_update_earlymode_info( hw, skb,
&tcb_desc, tid );
rtlpriv->intf_ops->adapter_tx( hw, NULL, skb, &tcb_desc );
}
}
}
static void _rtl_pci_tx_isr( struct ieee80211_hw *hw, int prio )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
while ( skb_queue_len( &ring->queue ) ) {
struct rtl_tx_desc *entry = &ring->desc[ring->idx];
struct sk_buff *skb;
struct ieee80211_tx_info *info;
__le16 fc;
u8 tid;
u8 own = ( u8 ) rtlpriv->cfg->ops->get_desc( ( u8 * ) entry, true,
HW_DESC_OWN );
/*beacon packet will only use the first
*descriptor by defaut, and the own may not
*be cleared by the hardware
*/
if ( own )
return;
ring->idx = ( ring->idx + 1 ) % ring->entries;
skb = __skb_dequeue( &ring->queue );
pci_unmap_single( rtlpci->pdev,
rtlpriv->cfg->ops->
get_desc( ( u8 * ) entry, true,
HW_DESC_TXBUFF_ADDR ),
skb->len, PCI_DMA_TODEVICE );
/* remove early mode header */
if ( rtlpriv->rtlhal.earlymode_enable )
skb_pull( skb, EM_HDR_LEN );
RT_TRACE( rtlpriv, ( COMP_INTR | COMP_SEND ), DBG_TRACE,
"new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
ring->idx,
skb_queue_len( &ring->queue ),
*( u16 * ) ( skb->data + 22 ) );
if ( prio == TXCMD_QUEUE ) {
dev_kfree_skb( skb );
goto tx_status_ok;
}
/* for sw LPS, just after NULL skb send out, we can
* sure AP knows we are sleeping, we should not let
* rf sleep
*/
fc = rtl_get_fc( skb );
if ( ieee80211_is_nullfunc( fc ) ) {
if ( ieee80211_has_pm( fc ) ) {
rtlpriv->mac80211.offchan_delay = true;
rtlpriv->psc.state_inap = true;
} else {
rtlpriv->psc.state_inap = false;
}
}
if ( ieee80211_is_action( fc ) ) {
struct ieee80211_mgmt *action_frame =
( struct ieee80211_mgmt * )skb->data;
if ( action_frame->u.action.u.ht_smps.action ==
WLAN_HT_ACTION_SMPS ) {
dev_kfree_skb( skb );
goto tx_status_ok;
}
}
/* update tid tx pkt num */
tid = rtl_get_tid( skb );
if ( tid <= 7 )
rtlpriv->link_info.tidtx_inperiod[tid]++;
info = IEEE80211_SKB_CB( skb );
ieee80211_tx_info_clear_status( info );
info->flags |= IEEE80211_TX_STAT_ACK;
/*info->status.rates[0].count = 1; */
ieee80211_tx_status_irqsafe( hw, skb );
if ( ( ring->entries - skb_queue_len( &ring->queue ) )
== 2 ) {
RT_TRACE( rtlpriv, COMP_ERR, DBG_LOUD,
"more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
prio, ring->idx,
skb_queue_len( &ring->queue ) );
ieee80211_wake_queue( hw,
skb_get_queue_mapping
( skb ) );
}
tx_status_ok:
skb = NULL;
}
if ( ( ( rtlpriv->link_info.num_rx_inperiod +
rtlpriv->link_info.num_tx_inperiod ) > 8 ) ||
( rtlpriv->link_info.num_rx_inperiod > 2 ) ) {
rtlpriv->enter_ps = false;
schedule_work( &rtlpriv->works.lps_change_work );
}
}
static void _rtl_receive_one( struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_rx_status rx_status )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct ieee80211_hdr *hdr = rtl_get_hdr( skb );
__le16 fc = rtl_get_fc( skb );
bool unicast = false;
struct sk_buff *uskb = NULL;
u8 *pdata;
memcpy( IEEE80211_SKB_RXCB( skb ), &rx_status, sizeof( rx_status ) );
if ( is_broadcast_ether_addr( hdr->addr1 ) ) {
;/*TODO*/
} else if ( is_multicast_ether_addr( hdr->addr1 ) ) {
;/*TODO*/
} else {
unicast = true;
rtlpriv->stats.rxbytesunicast += skb->len;
}
if ( ieee80211_is_data( fc ) ) {
rtlpriv->cfg->ops->led_control( hw, LED_CTL_RX );
if ( unicast )
rtlpriv->link_info.num_rx_inperiod++;
}
/* static bcn for roaming */
rtl_beacon_statistic( hw, skb );
rtl_p2p_info( hw, ( void * )skb->data, skb->len );
/* for sw lps */
rtl_swlps_beacon( hw, ( void * )skb->data, skb->len );
rtl_recognize_peer( hw, ( void * )skb->data, skb->len );
if ( ( rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ) &&
( rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G ) &&
( ieee80211_is_beacon( fc ) || ieee80211_is_probe_resp( fc ) ) )
return;
if ( unlikely( !rtl_action_proc( hw, skb, false ) ) )
return;
uskb = dev_alloc_skb( skb->len + 128 );
if ( !uskb )
return; /* exit if allocation failed */
memcpy( IEEE80211_SKB_RXCB( uskb ), &rx_status, sizeof( rx_status ) );
pdata = ( u8 * )skb_put( uskb, skb->len );
memcpy( pdata, skb->data, skb->len );
ieee80211_rx_irqsafe( hw, uskb );
}
static void _rtl_pci_rx_interrupt( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
struct ieee80211_rx_status rx_status = { 0 };
unsigned int count = rtlpci->rxringcount;
u8 own;
u8 tmp_one;
u32 bufferaddress;
struct rtl_stats stats = {
.signal = 0,
.rate = 0,
};
int index = rtlpci->rx_ring[rx_queue_idx].idx;
if ( rtlpci->driver_is_goingto_unload )
return;
/*RX NORMAL PKT */
while ( count-- ) {
/*rx descriptor */
struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
index];
/*rx pkt */
struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
index];
struct sk_buff *new_skb = NULL;
own = ( u8 ) rtlpriv->cfg->ops->get_desc( ( u8 * ) pdesc,
false, HW_DESC_OWN );
/*wait data to be filled by hardware */
if ( own )
break;
rtlpriv->cfg->ops->query_rx_desc( hw, &stats,
&rx_status,
( u8 * ) pdesc, skb );
if ( stats.crc || stats.hwerror )
goto done;
new_skb = dev_alloc_skb( rtlpci->rxbuffersize );
if ( unlikely( !new_skb ) ) {
RT_TRACE( rtlpriv, ( COMP_INTR | COMP_RECV ), DBG_DMESG,
"can't alloc skb for rx\n" );
goto done;
}
kmemleak_not_leak( new_skb );
pci_unmap_single( rtlpci->pdev,
*( ( dma_addr_t * ) skb->cb ),
rtlpci->rxbuffersize,
PCI_DMA_FROMDEVICE );
skb_put( skb, rtlpriv->cfg->ops->get_desc( ( u8 * ) pdesc, false,
HW_DESC_RXPKT_LEN ) );
skb_reserve( skb, stats.rx_drvinfo_size + stats.rx_bufshift );
/*
* NOTICE This can not be use for mac80211,
* this is done in mac80211 code,
* if you done here sec DHCP will fail
* skb_trim( skb, skb->len - 4 );
*/
_rtl_receive_one( hw, skb, rx_status );
if ( ( ( rtlpriv->link_info.num_rx_inperiod +
rtlpriv->link_info.num_tx_inperiod ) > 8 ) ||
( rtlpriv->link_info.num_rx_inperiod > 2 ) ) {
rtlpriv->enter_ps = false;
schedule_work( &rtlpriv->works.lps_change_work );
}
dev_kfree_skb_any( skb );
skb = new_skb;
rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
*( ( dma_addr_t * ) skb->cb ) =
pci_map_single( rtlpci->pdev, skb_tail_pointer( skb ),
rtlpci->rxbuffersize,
PCI_DMA_FROMDEVICE );
done:
bufferaddress = ( *( ( dma_addr_t * )skb->cb ) );
if ( pci_dma_mapping_error( rtlpci->pdev, bufferaddress ) )
return;
tmp_one = 1;
rtlpriv->cfg->ops->set_desc( hw, ( u8 * )pdesc, false,
HW_DESC_RXBUFF_ADDR,
( u8 * )&bufferaddress );
rtlpriv->cfg->ops->set_desc( hw, ( u8 * )pdesc, false,
HW_DESC_RXPKT_LEN,
( u8 * )&rtlpci->rxbuffersize );
if ( index == rtlpci->rxringcount - 1 )
rtlpriv->cfg->ops->set_desc( hw, ( u8 * )pdesc, false,
HW_DESC_RXERO,
&tmp_one );
rtlpriv->cfg->ops->set_desc( hw, ( u8 * )pdesc, false, HW_DESC_RXOWN,
&tmp_one );
index = ( index + 1 ) % rtlpci->rxringcount;
}
rtlpci->rx_ring[rx_queue_idx].idx = index;
}
static irqreturn_t _rtl_pci_interrupt( int irq, void *dev_id )
{
struct ieee80211_hw *hw = dev_id;
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
unsigned long flags;
u32 inta = 0;
u32 intb = 0;
irqreturn_t ret = IRQ_HANDLED;
spin_lock_irqsave( &rtlpriv->locks.irq_th_lock, flags );
/*read ISR: 4/8bytes */
rtlpriv->cfg->ops->interrupt_recognized( hw, &inta, &intb );
/*Shared IRQ or HW disappared */
if ( !inta || inta == 0xffff ) {
ret = IRQ_NONE;
goto done;
}
/*<1> beacon related */
if ( inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"beacon ok interrupt!\n" );
}
if ( unlikely( inta & rtlpriv->cfg->maps[RTL_IMR_TBDER] ) ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"beacon err interrupt!\n" );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_BDOK] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n" );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"prepare beacon for interrupt!\n" );
tasklet_schedule( &rtlpriv->works.irq_prepare_bcn_tasklet );
}
/*<3> Tx related */
if ( unlikely( inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW] ) )
RT_TRACE( rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n" );
if ( inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"Manage ok interrupt!\n" );
_rtl_pci_tx_isr( hw, MGNT_QUEUE );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"HIGH_QUEUE ok interrupt!\n" );
_rtl_pci_tx_isr( hw, HIGH_QUEUE );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK] ) {
rtlpriv->link_info.num_tx_inperiod++;
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"BK Tx OK interrupt!\n" );
_rtl_pci_tx_isr( hw, BK_QUEUE );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK] ) {
rtlpriv->link_info.num_tx_inperiod++;
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"BE TX OK interrupt!\n" );
_rtl_pci_tx_isr( hw, BE_QUEUE );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK] ) {
rtlpriv->link_info.num_tx_inperiod++;
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"VI TX OK interrupt!\n" );
_rtl_pci_tx_isr( hw, VI_QUEUE );
}
if ( inta & rtlpriv->cfg->maps[RTL_IMR_VODOK] ) {
rtlpriv->link_info.num_tx_inperiod++;
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"Vo TX OK interrupt!\n" );
_rtl_pci_tx_isr( hw, VO_QUEUE );
}
if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE ) {
if ( inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK] ) {
rtlpriv->link_info.num_tx_inperiod++;
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"CMD TX OK interrupt!\n" );
_rtl_pci_tx_isr( hw, TXCMD_QUEUE );
}
}
/*<2> Rx related */
if ( inta & rtlpriv->cfg->maps[RTL_IMR_ROK] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n" );
_rtl_pci_rx_interrupt( hw );
}
if ( unlikely( inta & rtlpriv->cfg->maps[RTL_IMR_RDU] ) ) {
RT_TRACE( rtlpriv, COMP_ERR, DBG_WARNING,
"rx descriptor unavailable!\n" );
_rtl_pci_rx_interrupt( hw );
}
if ( unlikely( inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW] ) ) {
RT_TRACE( rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n" );
_rtl_pci_rx_interrupt( hw );
}
/*fw related*/
if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE ) {
if ( inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD] ) {
RT_TRACE( rtlpriv, COMP_INTR, DBG_TRACE,
"firmware interrupt!\n" );
queue_delayed_work( rtlpriv->works.rtl_wq,
&rtlpriv->works.fwevt_wq, 0 );
}
}
if ( rtlpriv->rtlhal.earlymode_enable )
tasklet_schedule( &rtlpriv->works.irq_tasklet );
done:
spin_unlock_irqrestore( &rtlpriv->locks.irq_th_lock, flags );
return ret;
}
static void _rtl_pci_irq_tasklet( struct ieee80211_hw *hw )
{
_rtl_pci_tx_chk_waitq( hw );
}
static void _rtl_pci_prepare_bcn_tasklet( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci *rtlpci = rtl_pcidev( rtl_pcipriv( hw ) );
struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) );
struct rtl8192_tx_ring *ring = NULL;
struct ieee80211_hdr *hdr = NULL;
struct ieee80211_tx_info *info = NULL;
struct sk_buff *pskb = NULL;
struct rtl_tx_desc *pdesc = NULL;
struct rtl_tcb_desc tcb_desc;
/*This is for new trx flow*/
struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
u8 temp_one = 1;
memset( &tcb_desc, 0, sizeof( struct rtl_tcb_desc ) );
ring = &rtlpci->tx_ring[BEACON_QUEUE];
pskb = __skb_dequeue( &ring->queue );
if ( pskb ) {
struct rtl_tx_desc *entry = &ring->desc[ring->idx];
pci_unmap_single( rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
( u8 * ) entry, true, HW_DESC_TXBUFF_ADDR ),
pskb->len, PCI_DMA_TODEVICE );
kfree_skb( pskb );
}