How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib?

[amarioguy]

Hello,

I'm bringing up Project Mu on a platform (https://github.com/AppleWOA/apple_silicon_platforms_mu), and I'm having a bit of trouble with PCIe bringup. I've been following the example of QemuSbsaPkg as defined in mu_tiano_platforms and making a PciHostBridgeLib library class to use in conjunction with the PciHostBridgeDxe driver, however when I test boot this, the PCIe driver wrongly assumes the address space granularity is in 32 bit address space (when it should be in 64 bit address space as default, the platform i'm bringing up on does have a 32-bit aperture, but adding the translation to make that work in PciHostBridgeLib isn't working either, hitting an ASSERT in a mu_basecore component if I do that, so i'm trying to just use the 64-bit address space), which is causing the device to do an invalid memory access.

Is there a way I can set the host bridge's address space granularity and force it to be 64-bit? I tried defining the bridge in the DSDT, but it didn't seem to really have any effect, and looking at the mu_basecore driver seems to show that the address space granularity is defined when an autogenerated ACPI descriptor is made. (of note is that it sets a default size/default alignment which I can't find values for anywhere in the source) Any help would be appreciated.

apple_silicon_platforms_mu_bootlog.txt

Device boot log attached in case it helps