forked from robinsonb5/fpgagen
-
Notifications
You must be signed in to change notification settings - Fork 6
/
fpgagen.qip
30 lines (30 loc) · 2.72 KB
/
fpgagen.qip
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/fpgagen_top.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/fpgagen_sdram_top.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/os_rom.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/gen_io.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/gen_ctrl.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/gen_lightgun.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/SinglePortRAM.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/DualPortRAM.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/vdp_common.vhd]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/vdp.vhd]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) src/obj_cache.qip]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) src/sdram.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) src/sdram_alt.sv]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/sdram.vhd]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) src/fx68k/uaddrPla.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) src/fx68k/fx68kAlu.sv]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) src/fx68k/fx68k.sv]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) src/SVP/SVP.qip]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) src/T80/T80.qip]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt89/hdl/jt89.qip]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt12/hdl/jt12.qip]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/Guest_Toplevel.vhd]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) Board/mist/mist-modules/mist_core.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) Board/mist/mist-modules/data_io.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) Board/mist/hybrid_pwm_sd.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) src/hybrid_pwm_sd_2ndorder.v]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) build_id.vhd]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) constraints.sdc]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) src/throbber.v]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) src/demistify_config_pkg.vhd]