From 7c0ca01e62a43efc94d85f432d60adb020c57cfa Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 24 Feb 2021 10:15:06 -0800 Subject: [PATCH] [spectext] Add i32x4.dot_i16x8_s (#475) This instruction was added in #127. Co-authored-by: Andreas Rossberg --- .../core/appendix/gen-index-instructions.py | 1 + document/core/appendix/index-instructions.rst | 1 + document/core/binary/instructions.rst | 1 + document/core/exec/instructions.rst | 33 +++++++++++++++++++ document/core/syntax/instructions.rst | 1 + document/core/text/instructions.rst | 1 + document/core/util/macros.def | 1 + document/core/valid/instructions.rst | 14 ++++++++ 8 files changed, 53 insertions(+) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index 3ed07b7477..75e25e8041 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -488,6 +488,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VMIN\K{\_u}', r'\hex{FD}~~183', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_u'), Instruction(r'\I32X4.\VMAX\K{\_s}', r'\hex{FD}~~184', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_s'), Instruction(r'\I32X4.\VMAX\K{\_u}', r'\hex{FD}~~185', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_u'), + Instruction(r'\I32X4.\DOT\K{\_i16x8\_s}', r'\hex{FD}~~186', r'[\V128~\V128] \to [\V128]', r'valid-simd-dot', r'exec-simd-dot'), Instruction(r'\I32X4.\EXTMUL\K{\_low\_i16x8\_s}', r'\hex{FD}~~187', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I32X4.\EXTMUL\K{\_high\_i16x8\_s}', r'\hex{FD}~~189', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I32X4.\EXTMUL\K{\_low\_i16x8\_u}', r'\hex{FD}~~190', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index e9d3f15697..bd37fb5a26 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -436,6 +436,7 @@ Instruction Binary Opcode Type :math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~183` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~184` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~185` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~186` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~187` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~189` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~190` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index 7a411158c4..0ed683e3fe 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -687,6 +687,7 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~183{:}\Bu32 &\Rightarrow& \I32X4.\VMIN\K{\_u} \\ &&|& \hex{FD}~~184{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_s} \\ &&|& \hex{FD}~~185{:}\Bu32 &\Rightarrow& \I32X4.\VMAX\K{\_u} \\ &&|& + \hex{FD}~~186{:}\Bu32 &\Rightarrow& \I32X4.\DOT\K{\_i16x8\_s}\\ &&|& \hex{FD}~~187{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_s}\\ &&|& \hex{FD}~~189{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_high\_i16x8\_s}\\ &&|& \hex{FD}~~190{:}\Bu32 &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_u}\\ &&|& diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 9a900de96a..c542c6c87b 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -725,6 +725,39 @@ SIMD instructions are defined in terms of generic numeric operators applied lane \end{array} +.. _exec-simd-dot: + +:math:`\K{i32x4.}\DOT\K{\_i16x8\_s}` +.................................... + +1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| is on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +4. Let :math:`(i_1~i_2)^\ast` be the result of computing :math:`\imul_{32}(\extend^s_{16,32}(\lanes_{\I16X8}(c_1)), \extend^s_{16,32}(\lanes_{\I16X8}(c_2)))` + +5. Let :math:`j^\ast` be the result of computing :math:`\iadd_{32}(i_1, i_2)^\ast`. + +6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I32X4}(j^\ast)`. + +8. Push the value :math:`\V128.\VCONST~c` onto the stack. + +.. math:: + \begin{array}{l} + \begin{array}{lcl@{\qquad}l} + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i32x4.}\DOT\K{\_i16x8\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & (i_1~i_2)^\ast = \imul_{32}(\extend^s_{16,32}(\lanes_{\I16X8}(c_1)), \extend^s_{16,32}(\lanes_{\I16X8}(c_2))) \\ + \wedge & j^\ast = \iadd_{32}(i_1, i_2)^\ast \\ + \wedge & c = \lanes^{-1}_{\I32X4}(j^\ast) + \end{array} + \end{array} + + .. _exec-simd-vextmul: :math:`t_2\K{x}N\K{.}\EXTMUL\_\K{low}\_t_1\K{x}M\_\sx` and :math:`t_2\K{x}N\K{.}\EXTMUL\_\K{high}\_t_1\K{x}M\_\sx` diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 4dbd2b5463..0d97c76e2d 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -237,6 +237,7 @@ SIMD instructions provide basic operations over :ref:`values ` of \K{i64x2.}\viunop \\&&|& \K{i8x16.}\VPOPCNT \\&&|& \K{i16x8.}\Q15MULRSAT\K{\_s} \\ &&|& + \K{i32x4.}\DOT\K{\_i16x8\_s} \\ &&|& \fshape\K{.}\vfunop \\&&|& \ishape\K{.}\vitestop \\ &&|& \ishape\K{.}\BITMASK \\ &&|& diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index 5158d4970a..36c2763601 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -720,6 +720,7 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{i32x4.min\_u} &\Rightarrow& \I32X4.\VMIN\K{\_u}\\ &&|& \text{i32x4.max\_s} &\Rightarrow& \I32X4.\VMAX\K{\_s}\\ &&|& \text{i32x4.max\_u} &\Rightarrow& \I32X4.\VMAX\K{\_u}\\ &&|& + \text{i32x4.dot\_i16x8\_s} &\Rightarrow& \I32X4.\DOT\K{\_i16x8\_s}\\ &&|& \text{i32x4.extmul\_low\_i16x8\_s} &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_s}\\ &&|& \text{i32x4.extmul\_high\_i16x8\_s} &\Rightarrow& \I32X4.\EXTMUL\K{\_high\_i16x8\_s}\\ &&|& \text{i32x4.extmul\_low\_i16x8\_u} &\Rightarrow& \I32X4.\EXTMUL\K{\_low\_i16x8\_u}\\ &&|& diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 6f61458f8e..1007fd508f 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -425,6 +425,7 @@ .. |NARROW| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{narrow}} .. |VEXTEND| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extend}} .. |AVGR| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{avgr}} +.. |DOT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{dot}} .. |EXTMUL| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extmul}} .. |VTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{trunc}} .. |VCONVERT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{convert}} diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index 5a8602d648..ccdb506fee 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -450,6 +450,20 @@ We also define an auxiliary function to get number of packed numeric types in a } +.. _valid-simd-dot: + +:math:`\K{i32x4.}\DOT\K{\_i16x8\_s}` +.................................... + +* The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \K{i32x4.}\DOT\K{\_i16x8\_s} : [\V128~\V128] \to [\V128] + } + + .. _valid-simd-vextmul: :math:`\ishape\K{.}\vextmul\K{\_}\ishape\K{\_}\sx`