Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
Team members: Nikola Aleksić, Ema Pajić and I (Jovan Nikolov)
Development boards: Terasic DE0
Data input via PS/2 keyboard and data display via built-in 7-segment displays.
More information available in Serbian in docs\ folder.
Made for an intermediate-level course in Fundamentals of Computer Engineering at the University of Belgrade, School of Electrical Engineering. (https://rti.etf.bg.ac.rs/rti/ir2ort2/index.html)