From 1359f60338c6d012d9796e46e9f98e49f3110e3f Mon Sep 17 00:00:00 2001 From: Lu Yahan Date: Mon, 21 Feb 2022 11:25:32 +0800 Subject: [PATCH] deps: V8: cherry-pick 77d515484864 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Original commit message: [riscv64] Move explicit specialization into .cc file Building with Gcc-10 causes error "explicit specialization in non-namespace scope". This change fixes it. Bug: v8:12649 Change-Id: I36b2b042b336c2dfd32ba5541fdbbdb8dc8b4fd7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3473997 Reviewed-by: ji qiu Commit-Queue: ji qiu Cr-Commit-Position: refs/heads/main@{#79185} Refs: https://github.com/v8/v8/commit/77d515484864984f721d6726610f314982ac44d2 PR-URL: https://github.com/nodejs/node/pull/42067 Refs: https://github.com/v8/v8/commit/b66334313c8bd73b253d0779f59f3e8656967043 Reviewed-By: Michaël Zasso Reviewed-By: Jiawen Geng Reviewed-By: Richard Lau Reviewed-By: Colin Ihrig Reviewed-By: Mary Marchini Reviewed-By: Juan José Arboleda Reviewed-By: James M Snell Reviewed-By: Stewart X Addison --- common.gypi | 2 +- .../execution/riscv64/simulator-riscv64.cc | 203 ++++++++++++++++++ .../src/execution/riscv64/simulator-riscv64.h | 133 ------------ 3 files changed, 204 insertions(+), 134 deletions(-) diff --git a/common.gypi b/common.gypi index cd519730daf068..702eea8395f4db 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.14', + 'v8_embedder_string': '-node.15', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/execution/riscv64/simulator-riscv64.cc b/deps/v8/src/execution/riscv64/simulator-riscv64.cc index 4d289c4d20d028..a212ed24e00ab0 100644 --- a/deps/v8/src/execution/riscv64/simulator-riscv64.cc +++ b/deps/v8/src/execution/riscv64/simulator-riscv64.cc @@ -86,6 +86,209 @@ // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +static inline bool is_aligned(const unsigned val, const unsigned pos) { + return pos ? (val & (pos - 1)) == 0 : true; +} + +static inline bool is_overlapped(const int astart, int asize, const int bstart, + int bsize) { + asize = asize == 0 ? 1 : asize; + bsize = bsize == 0 ? 1 : bsize; + + const int aend = astart + asize; + const int bend = bstart + bsize; + + return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; +} +static inline bool is_overlapped_widen(const int astart, int asize, + const int bstart, int bsize) { + asize = asize == 0 ? 1 : asize; + bsize = bsize == 0 ? 1 : bsize; + + const int aend = astart + asize; + const int bend = bstart + bsize; + + if (astart < bstart && is_overlapped(astart, asize, bstart, bsize) && + !is_overlapped(astart, asize, bstart + bsize, bsize)) { + return false; + } else { + return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; + } +} + +#ifdef DEBUG +#define require_align(val, pos) \ + if (!is_aligned(val, pos)) { \ + std::cout << val << " " << pos << std::endl; \ + } \ + CHECK_EQ(is_aligned(val, pos), true) +#else +#define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true) +#endif + +// RVV +// The following code about RVV was based from: +// https://github.com/riscv/riscv-isa-sim +// Copyright (c) 2010-2017, The Regents of the University of California +// (Regents). All Rights Reserved. + +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// 3. Neither the name of the Regents nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. + +// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, +// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF +// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +template +struct type_usew_t; +template <> +struct type_usew_t<8> { + using type = uint8_t; +}; + +template <> +struct type_usew_t<16> { + using type = uint16_t; +}; + +template <> +struct type_usew_t<32> { + using type = uint32_t; +}; + +template <> +struct type_usew_t<64> { + using type = uint64_t; +}; + +template <> +struct type_usew_t<128> { + using type = __uint128_t; +}; +template +struct type_sew_t; + +template <> +struct type_sew_t<8> { + using type = int8_t; +}; + +template <> +struct type_sew_t<16> { + using type = int16_t; +}; + +template <> +struct type_sew_t<32> { + using type = int32_t; +}; + +template <> +struct type_sew_t<64> { + using type = int64_t; +}; + +template <> +struct type_sew_t<128> { + using type = __int128_t; +}; + +#define VV_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VV_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type rs1 = (type_usew_t::type)(get_register(rs1_reg())); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_PARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type uimm5 = (type_sew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_UPARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VXI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); + +#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i + off); + +#define VI_XI_SLIDEUP_PARAMS(x, offset) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i - offset); + +/* Vector Integer Extension */ +#define VI_VIE_PARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_VIE_UPARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define require_noover(astart, asize, bstart, bsize) \ + CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true) +#define require_noover_widen(astart, asize, bstart, bsize) \ + CHECK_EQ(!is_overlapped_widen(astart, asize, bstart, bsize), true) + #define RVV_VI_GENERAL_LOOP_BASE \ for (uint64_t i = rvv_vstart(); i < rvv_vl(); i++) { #define RVV_VI_LOOP_END \ diff --git a/deps/v8/src/execution/riscv64/simulator-riscv64.h b/deps/v8/src/execution/riscv64/simulator-riscv64.h index fce6cdca0adc30..b0ed702bb59f05 100644 --- a/deps/v8/src/execution/riscv64/simulator-riscv64.h +++ b/deps/v8/src/execution/riscv64/simulator-riscv64.h @@ -645,139 +645,6 @@ class Simulator : public SimulatorBase { } } - // RVV - // The following code about RVV was based from: - // https://github.com/riscv/riscv-isa-sim - // Copyright (c) 2010-2017, The Regents of the University of California - // (Regents). All Rights Reserved. - - // Redistribution and use in source and binary forms, with or without - // modification, are permitted provided that the following conditions are met: - // 1. Redistributions of source code must retain the above copyright - // notice, this list of conditions and the following disclaimer. - // 2. Redistributions in binary form must reproduce the above copyright - // notice, this list of conditions and the following disclaimer in the - // documentation and/or other materials provided with the distribution. - // 3. Neither the name of the Regents nor the - // names of its contributors may be used to endorse or promote products - // derived from this software without specific prior written permission. - - // IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - // SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, - // ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - // REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - // REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED - // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - template - struct type_usew_t; - template <> - struct type_usew_t<8> { - using type = uint8_t; - }; - - template <> - struct type_usew_t<16> { - using type = uint16_t; - }; - - template <> - struct type_usew_t<32> { - using type = uint32_t; - }; - - template <> - struct type_usew_t<64> { - using type = uint64_t; - }; - - template <> - struct type_usew_t<128> { - using type = __uint128_t; - }; - template - struct type_sew_t; - - template <> - struct type_sew_t<8> { - using type = int8_t; - }; - - template <> - struct type_sew_t<16> { - using type = int16_t; - }; - - template <> - struct type_sew_t<32> { - using type = int32_t; - }; - - template <> - struct type_sew_t<64> { - using type = int64_t; - }; - - template <> - struct type_sew_t<128> { - using type = __int128_t; - }; - -#define VV_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VV_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VX_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VX_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type rs1 = (type_usew_t::type)(get_register(rs1_reg())); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VI_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VI_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VXI_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); \ - type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ - type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); - -#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i + off); - -#define VI_XI_SLIDEUP_PARAMS(x, offset) \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i - offset); - inline void rvv_trace_vd() { if (::v8::internal::FLAG_trace_sim) { __int128_t value = Vregister_[rvv_vd_reg()];