From 97efe401edbfb6cedebb7db58a5e854c6b1e4dfc Mon Sep 17 00:00:00 2001
From: Olivier Giniaux <oginiaux@gmail.com>
Date: Mon, 27 May 2024 22:54:59 +0200
Subject: [PATCH] Add check on sse2 and neon (#76)

* Add missing check on sse2 feature

* 3.3.2

* Cleanup
---
 Cargo.toml                 | 2 +-
 src/gxhash/platform/arm.rs | 3 +++
 src/gxhash/platform/mod.rs | 2 --
 src/gxhash/platform/x86.rs | 6 ++++++
 src/lib.rs                 | 6 ------
 5 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index 8a2b686..33fda76 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 name = "gxhash"
 authors = ["Olivier Giniaux"]
-version = "3.3.1"
+version = "3.3.2"
 edition = "2021"
 description = "GxHash non-cryptographic algorithm"
 license = "MIT"
diff --git a/src/gxhash/platform/arm.rs b/src/gxhash/platform/arm.rs
index a262583..c7a550e 100644
--- a/src/gxhash/platform/arm.rs
+++ b/src/gxhash/platform/arm.rs
@@ -1,3 +1,6 @@
+#[cfg(not(any(all(target_feature = "aes", target_feature = "neon"), docsrs)))] // docs.rs bypasses the target_feature check
+compile_error!{"Gxhash requires aes and neon intrinsics. Make sure the processor supports it and build with RUSTFLAGS=\"-C target-cpu=native\" or RUSTFLAGS=\"-C target-feature=+aes,+neon\"."}
+
 #[cfg(target_arch = "arm")]
 use core::arch::arm::*;
 #[cfg(target_arch = "aarch64")]
diff --git a/src/gxhash/platform/mod.rs b/src/gxhash/platform/mod.rs
index 7b050fe..2dc7071 100644
--- a/src/gxhash/platform/mod.rs
+++ b/src/gxhash/platform/mod.rs
@@ -1,10 +1,8 @@
 #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
-#[cfg(all(target_feature = "aes", target_feature = "neon"))]
 #[path = "arm.rs"]
 mod platform;
 
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-#[cfg(any(all(target_feature = "aes", target_feature = "sse2"), docsrs))] // docsrs bypasses the target_feature check
 #[path = "x86.rs"]
 mod platform;
 
diff --git a/src/gxhash/platform/x86.rs b/src/gxhash/platform/x86.rs
index 67f52cf..c85c521 100644
--- a/src/gxhash/platform/x86.rs
+++ b/src/gxhash/platform/x86.rs
@@ -1,3 +1,9 @@
+#[cfg(not(any(all(target_feature = "aes", target_feature = "sse2"), docsrs)))] // docs.rs bypasses the target_feature check
+compile_error!{"Gxhash requires aes and sse2 intrinsics. Make sure the processor supports it and build with RUSTFLAGS=\"-C target-cpu=native\" or RUSTFLAGS=\"-C target-feature=+aes,+sse2\"."}
+
+#[cfg(all(feature = "hybrid", not(any(target_feature = "aes", target_feature = "vaes", target_feature = "avx2"))))]
+compile_error!{"Hybrid feature is only available on x86 processors with avx2 and vaes intrinsics."}
+
 #[cfg(target_arch = "x86")]
 use core::arch::x86::*;
 #[cfg(target_arch = "x86_64")]
diff --git a/src/lib.rs b/src/lib.rs
index 9b59d44..705a0bf 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -2,12 +2,6 @@
 // Hybrid SIMD width usage currently requires unstable 'stdsimd'
 #![cfg_attr(feature = "hybrid", feature(stdarch_x86_avx512))]
 
-#[cfg(all(feature = "hybrid", not(any(target_arch = "x86_64", target_feature = "aes", target_feature = "vaes", target_feature = "avx2"))))]
-compile_error!{"Hybrid feature is only available on x86 processors with avx2 and vaes intrinsics."}
-
-#[cfg(not(target_feature = "aes"))]
-compile_error!{"Gxhash requires aes intrinsics. Make sure the processor supports it and build with RUSTFLAGS=\"-C target-cpu=native\" or RUSTFLAGS=\"-C target-feature=+aes\"."}
-
 #[rustfmt::skip]
 mod gxhash;
 pub use crate::gxhash::*;