corescore.core

CAPI=2:

name: ::corescore:0

filesets:
  base:
    files:
      - rtl/wb2axis.v
      - rtl/base.v
    file_type: verilogSource
    depend: ["=::serv:1.0.2", "=::serving:1.0.2", verilog-axis]

  emitter_serv:
    files:
      - sw/emitter.hex: { file_type: user, copyto: emitter.hex }
      - rtl/axis2wb.v
      - rtl/emitter_mux.v
      - rtl/emitter.v
    file_type: verilogSource
    depend: ["=::servant:1.0.2-r1"]

  emitter_uart:
    files: [rtl/emitter_uart.v : {file_type: verilogSource}]

  agilex5_dk-a5e065bb32aes1:
    files:
      - data/agilex5_dk-a5e065bb32aes1.tcl: { file_type: tclSource }
      - data/intel_agilex7.sdc: { file_type: SDC }
      - rtl/corescore_intel_agilex7.v: { file_type: verilogSource }

  alhambra_II:
    files:
      - rtl/corescore_alhambra_II.v: { file_type: verilogSource }
      - data/alhambra_II.pcf: { file_type: PCF }
    depend: ["fusesoc:utils:generators"]

  arty_a7:
    files:
      - rtl/arty_a7_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_arty_a7.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/arty_a7.xdc: { file_type: xdc }

  chameleon96:
    files:
      - data/chameleon96/chameleon96.sdc : {file_type : SDC}
      - data/chameleon96/pinmap.tcl   : {file_type: tclSource}
      - data/chameleon96/HPS.sv : {file_type : systemVerilogSource}
      - data/chameleon96/CV_96.v : {file_type : verilogSource}
      - rtl/chameleon96_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_chameleon96.v: { file_type: verilogSource }

  cisco-hwic-3g-cdma:
    files:
      - data/cisco-hwic-3g-cdma.tcl: { file_type: tclSource }
      - data/cisco-hwic-3g-cdma.sdc: { file_type: SDC }
      - rtl/cisco_hwic_3g_cdma_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_cisco_hwic_3g_cdma.v: { file_type: verilogSource }

  cmod_a7:
    files:
      - rtl/cmod_a7_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_cmod_a7.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/cmod_a7.xdc: { file_type: xdc }

  colorlight:
    files:
      - data/colorlight_5a75b.lpf: { file_type: LPF }
      - rtl/ecppll.v: { file_type: verilogSource }
      - rtl/corescore_colorlight_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_colorlight.v: { file_type: verilogSource }

  cyc1000:
    files:
      - data/cyc1000.tcl: { file_type: tclSource }
      - data/cyc1000.sdc: { file_type: SDC }
      - rtl/cyc1000_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_cyc1000.v: { file_type: verilogSource }

  de0_nano:
    files:
      - data/de0_nano.sdc: { file_type: SDC }
      - data/de0_nano.tcl: { file_type: tclSource }
      - rtl/de0_nano_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_de0_nano.v: { file_type: verilogSource }

  de10_nano:
    files:
      - data/de10_nano.sdc: { file_type: SDC }
      - data/de10_nano.tcl: { file_type: tclSource }
      - rtl/de0_nano_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_de10_nano.v: { file_type: verilogSource }

  de5_net:
    files:
      - data/de5_net.sdc: { file_type: SDC }
      - data/de5_net.tcl: { file_type: tclSource }
      - rtl/de5_net_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_de5_net.v: { file_type: verilogSource }

  deca:
    files:
      - data/deca.sdc: { file_type: SDC }
      - data/deca.tcl: { file_type: tclSource }
      - rtl/de0_nano_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_deca.v: { file_type: verilogSource }

  ebaz4205:
    files:
      - rtl/ebaz4205_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_ebaz4205.v: { file_type: verilogSource }
      - data/ebaz4205.xdc: { file_type: xdc }

  ep2c5t144_devboard:
    files:
      - data/ep2c5t144_devboard.tcl : {file_type : tclSource}
      - data/ep2c5t144_devboard.sdc : {file_type : SDC}
      - rtl/ep2c5t144_devboard_clock_gen.v : {file_type : verilogSource}
      - rtl/corescore_ep2c5t144_devboard.v : {file_type : verilogSource}

  fpc_iii:
    files:
      - data/fpc_iii.lpf: { file_type: LPF }
      - rtl/ecppll.v: { file_type: verilogSource }
      - rtl/corescore_fpc_iii_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_fpc_iii.v: { file_type: verilogSource }

  generic:
    files:
      - rtl/corescore_generic.v: { file_type: verilogSource }

  genesys2:
    files:
      - rtl/genesys2_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_genesys2.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/genesys2.xdc: { file_type: xdc }

  go_board:
    files:
      - rtl/corescore_go_board.v: { file_type: verilogSource }
      - data/go_board.pcf: { file_type: PCF }

  haps_dx7:
    files:
      - rtl/corescore_haps_dx7_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_haps_dx7.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/haps_dx7.xdc: { file_type: xdc }

  hpc_k7:
    files:
      - rtl/hpc_k7_clock_gen.v : {file_type : verilogSource}
      - rtl/corescore_hpc_k7.v : {file_type : verilogSource}
      - data/vivado_waive.tcl : {file_type : tclSource}
      - data/hpc_k7.xdc : {file_type : xdc}

  hpc_ku:
    files:
      - rtl/hpc_ku_clock_gen.v : {file_type : verilogSource}
      - rtl/corescore_hpc_ku.v : {file_type : verilogSource}
      - data/vivado_waive.tcl : {file_type : tclSource}
      - data/hpc_ku.xdc : {file_type : xdc}

  hx8k:
    files:
      - rtl/corescore_hx8k.v: { file_type: verilogSource }
      - data/hx8k.pcf: { file_type: PCF }
    depend: ["fusesoc:utils:generators"]

  icebreaker:
    files:
      - rtl/corescore_icebreaker.v: { file_type: verilogSource }
      - data/icebreaker.pcf: { file_type: PCF }
    depend: ["fusesoc:utils:generators"]

  icestick:
    files:
      - rtl/corescore_icestick.v: { file_type: verilogSource }
      - data/icestick.pcf: { file_type: PCF }
    depend: ["fusesoc:utils:generators"]

  icesugar:
    files:
      - rtl/corescore_icesugar.v: { file_type: verilogSource }
      - data/icesugar.pcf: { file_type: PCF }

  intel_a10gx_devkit:
    files:
      - data/intel_a10gx_devkit.tcl: { file_type: tclSource }
      - data/intel_a10gx_devkit.sdc: { file_type: SDC }
      - rtl/intel_a10gx_devkit_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_intel_a10gx_devkit.v: { file_type: verilogSource }

  intel_agilex7:
    files:
      - data/intel_agilex7.tcl: { file_type: tclSource }
      - data/intel_agilex7.sdc: { file_type: SDC }
      - rtl/corescore_intel_agilex7.v: { file_type: verilogSource }

  intel_cyc10lp_devkit:
    files:
      - data/intel_cyc10lp_devkit.tcl: { file_type: tclSource }
      - data/intel_cyc10lp_devkit.sdc: { file_type: SDC }
      - rtl/intel_cyc10lp_devkit_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_intel_cyc10lp_devkit.v: { file_type: verilogSource }

  intel_dk-dev-agf014ea:
    files:
      - data/intel_dk-dev-agf014ea.tcl: { file_type: tclSource }
      - data/intel_agilex7.sdc: { file_type: SDC }
      - rtl/corescore_intel_agilex7.v: { file_type: verilogSource }

  intel_dk-si-agi027fb:
    files:
      - data/intel_dk-si-agi027fb.tcl: { file_type: tclSource }
      - data/intel_agilex7.sdc: { file_type: SDC }
      - rtl/corescore_intel_agilex7.v: { file_type: verilogSource }

  intel_dk-si-agi040fes:
    files:
      - data/intel_dk-si-agi040fes.tcl: { file_type: tclSource }
      - data/intel_agilex7.sdc: { file_type: SDC }
      - rtl/corescore_intel_agilex7.v: { file_type: verilogSource }

  intel_max10_devkit:
    files:
      - data/intel_max10_devkit.tcl: { file_type: tclSource }
      - data/intel_max10_devkit.sdc: { file_type: SDC }
      - rtl/intel_max10_devkit_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_intel_max10_devkit.v: { file_type: verilogSource }

  intel_s10gx_devkit:
    files:
      - data/intel_s10gx_devkit.tcl: { file_type: tclSource }
      - data/intel_s10gx_devkit.sdc: { file_type: SDC }
      - data/intel_s10gx_pll.ip: { file_type: IP }
      - rtl/corescore_intel_s10gx_devkit.v: { file_type: verilogSource }

  kc705:
    files:
      - rtl/corescore_kc705.v: { file_type: verilogSource }
      - rtl/corescore_kc705_clock_gen.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/kc705.xdc: { file_type: xdc }

  marble:
    files:
      - rtl/corescore_marble.v : {file_type : verilogSource}
      - data/vivado_waive.tcl : {file_type : tclSource}
      - data/marble.xdc : {file_type : xdc}

  max1000:
    files:
      - data/max1000.tcl: { file_type: tclSource }
      - data/max1000.sdc: { file_type: SDC }
      - rtl/max1000_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_max1000.v: { file_type: verilogSource }

  nexys_a7:
    files:
      - rtl/nexys_a7_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_nexys_a7.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/nexys_a7.xdc: { file_type: xdc }

  nexys_video:
    files:
      - rtl/nexys_video_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_nexys_video.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/nexys_video.xdc: { file_type: xdc }

  polarfireeval:
    files:
      - rtl/corescore_polarfire_eval_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_polarfire.v: { file_type: verilogSource }
      - data/polarfire_eval.pdc: { file_type: PDC }
      - data/libero-post-instructions.txt:
          { file_type: user, copyto: post-instructions.txt }

  sockit:
    files:
      - data/sockit.sdc: { file_type: SDC }
      - data/sockit.tcl: { file_type: tclSource }
      - rtl/de0_nano_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_sockit.v: { file_type: verilogSource }

  storeypeak:
    files:
      - data/storeypeak.tcl: { file_type: tclSource }
      - data/storeypeak.sdc: { file_type: SDC }
      - rtl/storeypeak_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_storeypeak.v: { file_type: verilogSource }

  tb:
    files:
      - tb/corescore_tb.cpp: { file_type: cppSource }

  tinyfpga_bx:
    files:
      - data/tinyfpga_bx.pcf: { file_type: PCF }
      - data/tinyfpga_bx.py: { file_type: user, copyto: constraints.py }
      - rtl/corescore_tinyfpga_bx.v: { file_type: verilogSource }
    depend: [usbserial, "fusesoc:utils:generators"]

  ulx3s:
    files:
      - data/ulx3s.lpf: { file_type: LPF }
      - rtl/ecppll.v: { file_type: verilogSource }
      - rtl/corescore_ulx3s_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_ulx3s.v: { file_type: verilogSource }

  upduino2:
    files:
      - rtl/corescore_upduino2.v: { file_type: verilogSource }
      - data/upduino2.pcf: { file_type: PCF }

  vcu118:
    files:
      - rtl/corescore_vcu118_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_vcu118.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/vcu118.xdc: { file_type: xdc }

  vcu128:
    files:
      - rtl/corescore_vcu128_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_vcu128.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/vcu128.xdc: { file_type: xdc }

  vu19p:
    files:
      - rtl/corescore_vu19p_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_vu19p.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/vu19p.xdc: { file_type: xdc }

  xyloni:
    files:
      - rtl/corescore_xyloni.v : {file_type: verilogSource}
      - data/xyloni.isf: {file_type : ISF}

  zcu106:
    files:
      - rtl/corescore_zcu106_clock_gen.v: { file_type: verilogSource }
      - rtl/corescore_zcu106.v: { file_type: verilogSource }
      - data/vivado_waive.tcl: { file_type: tclSource }
      - data/zcu106.xdc: { file_type: xdc }

targets:

  agilex5_dk-a5e065bb32aes1:
    default_tool: quartus
    description: Agilex 5 E-Seried Premium Development Kit with Jtag UART
    filesets: [base, agilex5_dk-a5e065bb32aes1]
    generate: [corescorecore: {count: 1327}]
    tools:
      quartus:
        family: Agilex
        device: A5ED065BB32AE6SR0
    toplevel: corescore_intel_agilex7

  alhambra_II:
    default_tool: icestorm
    description: Alhambra II iCE40-HX4K based open-source hardware board
    filesets: [base, emitter_serv, alhambra_II]
    generate:
      - corescorecore: {count: 12}
      - ice40pll: {freq_in : 12}
    tools:
      icestorm:
        nextpnr_options: [--hx8k, --package, "tq144:4k", --freq, 16]
        pnr: next
    toplevel: corescore_alhambra_II

  arty_a7_35t:
    default_tool: vivado
    description: Digilent Arty A7 35t with 104 cores
    filesets: [base, emitter_serv, arty_a7]
    generate: [corescorecore : {count: 104}]
    tools:
      vivado: { part: xc7a35ticsg324-1L }
    toplevel: corescore_arty_a7

  arty_a7_100t:
    default_tool: vivado
    description: Digilent Arty A7 100t with 306 cores + SERV emitter
    filesets: [base, emitter_uart, arty_a7]
    generate: [corescorecore: {count: 306}]
    tools:
      vivado: { part: xc7a100tcsg324-1 }
    toplevel: corescore_arty_a7

  chameleon96:
    default_tool : quartus
    description : Chameleon96 (Arrow 96 CV SoC Board)
    filesets : [base, emitter_serv, chameleon96]
    generate: [corescorecore: {count: 270}]
    tools:
      quartus:
        family : Cyclone V
        device : 5CSEBA6U19I7
        board_device_index : 2
    toplevel: CV_96

  cisco-hwic-3g-cdma:
    default_tool: quartus
    description: Cisco HWIC-3G-CMDA with 84 cores + SERV emitter
    filesets: [base, emitter_serv, cisco-hwic-3g-cdma]
    generate: [corescorecore: {count: 84}]
    tools:
      quartus:
        family: Cyclone II
        device: EP2C35F484C8
    toplevel: corescore_cisco_hwic_3g_cdma

  cmod_a7_35t:
    default_tool: vivado
    description: Digilent CMOD A7 35t with 100 cores + SERV emitter
    filesets: [base, emitter_serv, cmod_a7]
    generate: [corescorecore: {count: 100}]
    tools:
      vivado: { part: xc7a35tcpg236-1 }
    toplevel: corescore_cmod_a7

  colorlight_5a75b:
    default_tool: trellis
    description: colorlight 5a75b version
    filesets: [base, emitter_serv, colorlight]
    generate: [corescorecore: {count: 55}]
    tools:
      diamond:
        part: LFE5U-25F-6BG256C
      trellis:
        nextpnr_options: [--package, CABGA256, --25k]
    toplevel: corescore_colorlight

  cyc1000:
    default_tool: quartus
    description: TrenzElectronics cyc1000 with 60 cores + SERV emitter
    filesets: [base, emitter_serv, cyc1000]
    generate: [corescorecore: {count: 60}]
    tools:
      quartus:
        family: Cyclone 10 LP
        device: 10CL025YU256C8G
    toplevel: corescore_cyc1000

  de0_nano:
    default_tool: quartus
    filesets: [base, emitter_serv, de0_nano]
    generate: [corescorecore: {count: 61}]
    tools:
      quartus:
        family: Cyclone IV E
        device: EP4CE22F17C6
    toplevel: corescore_de0_nano

  de10_nano:
    default_tool: quartus
    description : Terasic DE10 Nano Kit
    filesets: [base, emitter_serv, de10_nano]
    generate: [corescorecore: {count: 271}]
    tools:
      quartus:
        family: Cyclone V
        device: 5CSEBA6U23I7
        board_device_index : 2
    toplevel: corescore_de10_nano

  de5_net:
    default_tool: quartus
    filesets: [base, emitter_serv, de5_net]
    generate: [corescorecore: {count: 1568}]
    tools:
      quartus:
        family: Stratix V
        device: 5SGXEA7N2F45C2
    toplevel: corescore_de5_net

  deca:
    default_tool: quartus
    description: DECA development kit by Arrow / Terasic with 139 cores  + SERV emitter
    filesets: [base, emitter_serv, deca]
    generate: [corescorecore: {count: 139}]
    tools:
      quartus:
        family: MAX 10
        device: 10M50DAF484C6GES
    toplevel: corescore_deca

  ebaz4205:
    default_tool: vivado
    description: EBAZ4205 'Development' Board + SERV emitter
    filesets: [base, emitter_serv, ebaz4205]
    generate: [corescorecore: {count: 85}]
    tools:
      vivado: { part: xc7z010clg400-1 }
    toplevel: corescore_ebaz4205

  ep2c5t144_devboard:
    default_tool: quartus
    description : EP2C5T144 development board with 11 cores + SERV emitter
    filesets : [base, emitter_serv, ep2c5t144_devboard]
    generate : [corescorecore: {count: 11}]
    tools:
      quartus:
        family : Cyclone II
        device : EP2C5T144C6
    toplevel : corescore_ep2c5t144_devboard

  fpc_iii:
    default_tool: trellis
    description: FPC-III with 128 cores + SERV emitter
    filesets: [base, emitter_serv, fpc_iii]
    generate: [corescorecore: {count: 128}]
    tools:
      trellis:
        nextpnr_options: [--package, CABGA381, --85k, --speed, 8]
    toplevel: corescore_fpc_iii

  genesys2:
    default_tool: vivado
    description: Digilent Genesys 2 with 967 cores + SERV emitter
    filesets: [base, emitter_serv, genesys2]
    generate: [corescorecore: {count: 967}]
    tools:
      vivado: { part: xc7k325tffg900-2 }
    toplevel: corescore_genesys2

  go_board:
    default_tool: icestorm
    description: Nandland Go Board + Verilog emitter
    filesets: [base, emitter_uart, go_board]
    generate: [corescorecore: {count: 2}]
    tools:
      icestorm:
        nextpnr_options: [--hx1k, --package, vq100, --freq, 25]
        pnr: next
        yosys_synth_options: [-dffe_min_ce_use, 8]
    toplevel: corescore_go_board

  haps_dx7:
    default_tool: vivado
    filesets: [base, emitter_serv, haps_dx7]
    generate: [corescorecore: {count: 3040}]
    tools:
      vivado: { part: xc7vx980tffg1926-2 }
    toplevel: corescore_haps_dx7

  hpc_k7:
    default_tool: vivado
    description: HPCV2 Kintex7 k7420 with 1024 cores@128MHz + SERV emitter (460800bps UART)
    filesets : [base, emitter_serv, hpc_k7]
    generate : [corescorecore: {count : 1024}]
    tools:
      vivado: {part : xc7k420tffg901-2}
    toplevel : corescore_hpc_k7

  hpc_ku:
    default_tool: vivado
    description: HPCV2 KintexUltraScale ku040 with 1024 cores@128MHz + SERV emitter (460800bps UART)
    filesets : [base, emitter_serv, hpc_ku]
    generate : [corescorecore: {count : 1024}]
    tools:
      vivado: {part : xcku040-ffva1156-2-i}
    toplevel : corescore_hpc_ku

  hx8k:
    default_tool: icestorm
    description: Lattice iCE40-HX8K development board
    filesets: [base, emitter_serv, hx8k]
    generate:
      - corescorecore: {count: 12}
      - ice40pll : {freq_in: 12}
    tools:
      icestorm:
        nextpnr_options: [--hx8k, --package, "ct256", --freq, 16]
        pnr: next
    toplevel: corescore_hx8k

  icebreaker:
    default_tool: icestorm
    description: 1BitSquared iCE40UP5K based open-source hardware board
    filesets: [base, emitter_serv, icebreaker]
    generate: [corescorecore: {count: 10}]
    tools:
      icestorm:
        nextpnr_options: [--package, sg48, --up5k, --freq, 16]
        pnr: next
        yosys_synth_options: [-dffe_min_ce_use, 8]
    toplevel: corescore_icebreaker

  icestick:
    default_tool: icestorm
    description: Lattice iCEstick development board
    filesets: [base, emitter_uart, icestick]
    generate:
      - corescorecore: {count: 2}
      - ice40pll: {freq_in: 12}
    tools:
      icestorm:
        nextpnr_options: [--hx1k, --package, "tq144", --freq, 16]
        pnr: next
    toplevel: corescore_icestick

  icesugar:
    default_tool: icestorm
    description: iCE40UP5K Development Board by MuseLab
    filesets: [base, emitter_serv, icesugar]
    generate: [corescorecore: {count: 10}]
    tools:
      icestorm:
        nextpnr_options: [--package, sg48, --up5k, --freq, 16]
        pnr: next
        yosys_synth_options: [-dffe_min_ce_use, 8]
    toplevel: corescore_icesugar

  intel_a10gx_devkit:
    default_tool: quartus
    description: Intel Arria 10 GX FPGA Development Kit with 2600 cores + Jtag UART
    filesets: [base, intel_a10gx_devkit]
    generate: [corescorecore: {count: 2600}]
    tools:
      quartus:
        family: Arria 10
        device: 10AX115S2F45I1SG
    toplevel: corescore_intel_a10gx_devkit

  intel_cyc10lp_devkit:
    default_tool: quartus
    description: Intel Cyclone 10LP FPGA Development Kit with 64 cores  + SERV emitter
    filesets: [base, emitter_serv, intel_cyc10lp_devkit]
    generate: [corescorecore: {count: 64}]
    tools:
      quartus:
        family: Intel Cyclone 10 LP
        device: 10CL025YU256I7G
    toplevel: corescore_intel_cyc10lp_devkit

  intel_dk-dev-agf014ea:
    default_tool: quartus
    description: Intel Agilex 7 FPGA F-Series Development Kit with 2970 cores + Jtag UART
    filesets: [base, intel_dk-dev-agf014ea]
    generate: [corescorecore: {count: 2970}]
    tools:
      quartus:
        family: Agilex
        device: AGFB014R24B2E2V
    toplevel: corescore_intel_agilex7

  intel_dk-si-agi027fb:
    default_tool: quartus
    description: Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit 5525 cores + Jtag UART
    filesets: [base, intel_dk-si-agi027fb]
    generate: [corescorecore: {count: 5525}]
    tools:
      quartus:
        family: Agilex
        device: AGIB027R31B1E1VAA
    toplevel: corescore_intel_agilex7

  intel_dk-si-agi040fes:
    default_tool: quartus
    description: Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit 8225 cores + Jtag UART
    filesets: [base, intel_dk-si-agi040fes]
    generate: [corescorecore: {count: 8225}]
    tools:
      quartus:
        family: Agilex
        device: AGIC040R39A2E2VR0
    toplevel: corescore_intel_agilex7

  intel_max10_devkit:
    default_tool: quartus
    description: Intel Max10 10M50 Devkit with 133 cores  + SERV emitter
    filesets: [base, emitter_serv, intel_max10_devkit]
    generate: [corescorecore: {count: 133}]
    tools:
      quartus:
        family: Intel Max10
        device: 10M50DAF484C6GES
    toplevel: corescore_intel_max10_devkit

  intel_s10gx_devkit:
    default_tool: quartus
    description: Intel Stratix 10 GX FPGA Development Kit with 5600 cores + Jtag UART
    filesets: [base, intel_s10gx_devkit]
    generate: [corescorecore: {count: 5600}]
    tools:
      quartus:
        family: Stratix 10
        device: 1SG280HU2F50E2VG
    toplevel: corescore_intel_s10gx_devkit

  kc705:
    default_tool: vivado
    description: Xilinx KC705 evaluation board with 960 cores + SERV emitter
    filesets: [base, emitter_serv, kc705]
    generate: [corescorecore: {count: 960}]
    tools:
      vivado: { part: xc7k325tffg900-2 }
    toplevel: corescore_kc705

  marble:
    default_tool: vivado
    description: Marble board Kintex7 with 481 cores@100MHz + SERV emitter (360000bps UART)
    filesets : [base, emitter_serv, marble]
    generate : [corescorecore: {count : 481}]
    tools:
      vivado: {part : xc7k160tffg676-2}
    toplevel : corescore_marble

  max1000:
    default_tool: quartus
    description: TrenzElectronics max1000 with 20 cores + SERV emitter
    filesets: [base, emitter_serv, max1000]
    generate: [corescorecore: {count: 20}]
    tools:
      quartus:
        family: Intel Max10
        device: 10M08SAU169C8G
    toplevel: corescore_max1000

  nexys_a7:
    default_tool: vivado
    description: Digilent Nexys A7 with 268 cores + SERV emitter
    filesets: [base, emitter_serv, nexys_a7]
    generate: [corescorecore: {count: 268}]
    tools:
      vivado: { part: xc7a100tcsg324-1 }
    toplevel: corescore_nexys_a7

  nexys_video:
    default_tool: vivado
    description: Digilent Nexys Video with 652 cores + SERV emitter
    filesets: [base, emitter_serv, nexys_video]
    generate: [corescorecore: {count: 652}]
    tools:
      vivado: { part: xc7a200tsbg484-1 }
    toplevel: corescore_nexys_video

  polarfireeval: &polarfireeval
    default_tool: libero
    description: Microsemi Polarfire Evaluation Kit
    filesets: [base, emitter_serv, polarfireeval]
    hooks:
      post_run: [libero_post]
    generate: [corescorecore: {count: 882}]
    tools:
      libero: &liberoMPF300
        family: PolarFire
        die: MPF300TS
        package: FCG1152
    toplevel: corescore_polarfire

  polarfireeval_es:
    <<: *polarfireeval
    tools:
      libero:
        <<: *liberoMPF300
        die: MPF300TS_ES

  sim:
    default_tool: verilator
    description: Verilator testbench with 10 cores + SERV emitter
    filesets: [base, emitter_serv, generic, tb]
    generate: [corescorecore: {count: 10}]
    parameters: [uart_baudrate=57600, vcd]
    tools:
      verilator:
        verilator_options: [--trace, -Wno-timescalemod]
    toplevel: corescore_generic

  sockit:
    default_tool: quartus
    description: Arrow Sockit Development kit by Terasic with 284 cores  + SERV emitter
    filesets: [base, emitter_serv, sockit]
    generate: [corescorecore: {count: 284}]
    tools:
      quartus:
        family: Cyclone V
        device: 5CSXFC6D6F31C6
    toplevel: corescore_sockit

  storeypeak:
    default_tool: quartus
    description: Microsoft Storey Peak card
    filesets: [base, emitter_serv, storeypeak]
    generate: [corescorecore: {count: 1152}]
    tools:
      quartus:
        family: Stratix V
        device: 5SGSMD5K1F40C2
    toplevel: corescore_storeypeak

  tinyfpga_bx:
    default_tool: icestorm
    description: TinyFPGA BX with 11 cores + USB emitter
    filesets: [base, emitter_serv, tinyfpga_bx]
    generate:
      - corescorecore: {count: 11}
      - ice40pll: {freq_in: 16, freq_out: 48}
    tools:
      icestorm:
        pnr: next
        nextpnr_options: [--pre-pack, constraints.py, --lp8k, --package, cm81]
    toplevel: corescore_tinyfpga_bx

  ulx3s_85:
    default_tool: trellis
    description: ULX3S 85k version with 135 cores + SERV emitter
    filesets: [base, emitter_serv, ulx3s]
    generate: [corescorecore: {count: 135}]
    tools:
      diamond:
        part: LFE5U-85F-6BG381C
      trellis:
        nextpnr_options: [--package, CABGA381, --85k]
    toplevel: corescore_ulx3s

  upduino2:
    default_tool: icestorm
    filesets: [base, emitter_serv, upduino2]
    generate: [corescorecore: {count: 10}]
    tools:
      icestorm:
        nextpnr_options: [--package, sg48, --up5k, --freq, 16]
        pnr: next
        yosys_synth_options: [-dffe_min_ce_use, 8]
    toplevel: corescore_upduino2

  vcu118:
    default_tool: vivado
    filesets: [base, emitter_serv, vcu118]
    generate: [corescorecore: {count: 5087}]
    tools:
      vivado: { part: xcvu9p-flga2104-2l-e }
    toplevel: corescore_vcu118

  vcu128:
    default_tool: vivado
    filesets: [base, emitter_serv, vcu128]
    generate: [corescorecore: {count: 6000}]
    tools:
      vivado: { part: xcvu37p-fsvh2892-2-e }
    toplevel: corescore_vcu128

  vu19p:
    default_tool: vivado
    filesets: [base, emitter_serv, vu19p]
    generate: [corescorecore: {count: 10000}]
    tools:
      vivado: { part: xcvu19p-fsva3824-2-e }
    toplevel: corescore_vu19p

  xyloni:
    description: Efinix Xyloni Board
    filesets: [base, emitter_serv, xyloni]
    flow: efinity
    flow_options:
      family: Trion
      part: T8F81
      timing: C2
    generate: [corescorecore : {count: 17}]
    toplevel : corescore_xyloni

  zcu106:
    default_tool: vivado
    filesets: [base, emitter_serv, zcu106]
    generate: [corescorecore: {count: 940}]
    tools:
      vivado: { part: xczu7ev-ffvc1156-2-e }
    toplevel: corescore_zcu106

generate:
  corescorecore:
    generator: corescorecore
    parameters:
      count: 10

  ice40pll:
    generator: icepll
    parameters:
      freq_out: 16
      module: true

generators:
  corescorecore:
    interpreter: python3
    command: sw/corescorecore_gen.py

parameters:
  uart_baudrate:
    datatype: int
    description: Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
    paramtype: plusarg

  vcd:
    datatype: bool
    paramtype: plusarg

scripts:
  libero_post:
    cmd: ["python3", "-c", "print(open('post-instructions.txt','r').read())"]