RISCV V extension cycle simulation w/ GEM5

[js4ngu]

Hello,

I'm a student deeply interested in RISC-V cycle simulation using GEM5.

I'm particularly curious about simulating the RISC-V V extension (RVV).

I intend to perform cycle simulation using the O3CPU model.

From my understanding, it seems that FuncUnitConfig.py is responsible for calculating cycles for each instruction.
If I'm mistaken, Please correct me...

(FuncUnitConfig.py is locate at /gem5/src/cpu/o3/FuncUnitConfig.py)

However, I've noticed that the SIMD Unit executing RVV instructions doesn't seem to have a defined OpLat (Operation Latency).
It appears to assume a default of 1 cycle.

Based on this understanding, I have a few questions:

Q1. In actual hardware, different instructions likely have varying execution times.
If my understanding is correct, doesn't this mean that cycle simulation for RVV using the current implementation of GEM5 is not meaningful?

Q2. It seems that OpLat is defined for SIMD operations in ARM and x86 architectures.
For RISC-V, what would be a reasonable assumption for the number of cycles used in LWE.V, SWE.V, and SIMD CONFIG(e,g. VSETVLI) operations?
While I understand there may be implementation dependencies, is there a baseline or general guideline you could suggest or advise on?

[zhuanshulz]

Did you figure out the problem? I also found this problem when I was browsing the code today, but I couldn't find the answer on the Internet.