From 00aebcf29d9407949e1d821c70b29d921175f1aa Mon Sep 17 00:00:00 2001 From: Richard Winterton Date: Fri, 3 May 2019 10:01:33 -0700 Subject: [PATCH] Introduce Load and Extend Incorporate review suggestions from WebAssembly/simd#77 --- proposals/simd/BinarySIMD.md | 8 +++++++- proposals/simd/ImplementationStatus.md | 6 ++++++ proposals/simd/SIMD.md | 11 +++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index ff51a7f0f..865a62a27 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -166,5 +166,11 @@ The `v8x16.shuffle2_imm` instruction has 16 bytes after `simdop`. | `f32x4.convert_u/i32x4` | `0xb0`| - | | `f64x2.convert_s/i64x2` | `0xb1`| - | | `f64x2.convert_u/i64x2` | `0xb2`| - | +| `i16x8.load8x8_u` | `0xb3`| m:memarg | +| `i16x8.load8x8_s` | `0xb4`| m:memarg | +| `i32x4.load16x4_u` | `0xb5`| m:memarg | +| `i32x4.load16x4_s` | `0xb6`| m:memarg | +| `i64x2.load32x2_u` | `0xb7`| m:memarg | +| `i64x2.load32x2_s` | `0xb8`| m:memarg | | `v8x16.shuffle1` | `0xc0`| - | -| `v8x16.shuffle2_imm` | `0xc1`| s:LaneIdx32[16] | \ No newline at end of file +| `v8x16.shuffle2_imm` | `0xc1`| s:LaneIdx32[16] | diff --git a/proposals/simd/ImplementationStatus.md b/proposals/simd/ImplementationStatus.md index 7d612fee7..e3c0db649 100644 --- a/proposals/simd/ImplementationStatus.md +++ b/proposals/simd/ImplementationStatus.md @@ -139,6 +139,12 @@ | `f32x4.convert_u/i32x4` | `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.convert_s/i64x2` | `-munimplemented-simd128` | | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.convert_u/i64x2` | `-munimplemented-simd128` | | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.load8x8_u` | | | | | +| `i16x8.load8x8_s` | | | | | +| `i32x4.load16x4_u` | | | | | +| `i32x4.load16x4_s` | | | | | +| `i64x2.load32x2_u` | | | | | +| `i64x2.load32x2_s` | | | | | | `v8x16.shuffle1` | | | :heavy_check_mark: | | | `v8x16.shuffle2_imm` | | | :heavy_check_mark: | :heavy_check_mark: | diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md index 4862364e8..0afc118e0 100644 --- a/proposals/simd/SIMD.md +++ b/proposals/simd/SIMD.md @@ -666,6 +666,17 @@ natural alignment. Load a `v128` vector from the given heap address. +### Load and Extend + +Fetch consequtive integers up to 32-bit wide and produce a vector with lanes up to 64 bits: + +* `i16x8.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane +* `i16x8.load8x8_s(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane +* `i32x4.load16x4_u(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane +* `i32x4.load16x4_s(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane +* `i64x2.load32x2_u(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane +* `i64x2.load32x2_s(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane + ### Store * `v128.store(memarg, data: v128)`