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cpu_isolated_mode.ucl
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cpu_isolated_mode.ucl
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module common {
// address type: an uninterpreted type.
type addr_t;
// word type: a bitvector type.
type word_t = bv32;
// type of operations supported by the CPU.
type op_t = enum {
op_alu, op_load, op_store,
op_imode_enter, op_nmode_exit
};
// CPU mode.
type mode_t = enum { normal_mode, isolated_mode };
// CPU memory type: an array type.
type mem_t = [addr_t]word_t;
// define zero constant of the word_t type.
const k0_word_t : word_t;
axiom k0_word_t == 0bv32;
// the entry address for isolated mode.
const imode_enter_addr : addr_t;
// the exit address for isolated mode.
const nmode_exit_addr : addr_t;
// the above two constants MUST be different.
axiom imode_enter_addr != nmode_exit_addr;
}
module cpu {
// import all types from module common
type * = common.*;
type regindex_t;
type regs_t = [regindex_t]word_t;
input imem : mem_t; // program memory.
var dmem : mem_t; // data memory.
var regs : regs_t; // registers.
var pc : addr_t; // program counter.
var inst, result : word_t; // inst reg, result
var mode : mode_t; // normal/isolated mode?
// rng of isolated memory.
const isolated_rng_lo, isolated_rng_hi : addr_t;
// uninterpreted func. (predicate) for the above.
function in_rng (a : addr_t, b1 : addr_t, b2 : addr_t) : boolean;
// uninterpreted functions for decoding insns.
function inst2op
(i : word_t) : op_t;
function inst2reg0
(i : word_t) : regindex_t;
function inst2reg1
(i : word_t) : regindex_t;
function inst2addr
(i : word_t, r0 : word_t, r1 : word_t) : addr_t;
// uninterpreted functions for insn. execution
function aluOp
(i : word_t, r0 : word_t, r1 : word_t) : word_t;
function nextPC
(i : word_t, pc : addr_t, r0 : word_t) : addr_t;
// macro: is an addr in isolated memory?
define in_isolated_memory (a : addr_t) : boolean
= in_rng(a, isolated_rng_lo, isolated_rng_hi);
// assumptions on imode entry and exit addresses
axiom (forall (a : addr_t) ::
(a == common.imode_enter_addr)
==> in_isolated_memory(a));
axiom (forall (a : addr_t) ::
(a == common.nmode_exit_addr)
==> !in_isolated_memory(a));
// code removed for formatting reasons:
// 1. code for procedure exec_inst (see Example 3)
// 2. init and next blocks (see Example 4)
procedure exec_inst(instr : word_t, pc : addr_t)
returns (pc_next : addr_t)
modifies regs, result, dmem, mode;
{
var op : op_t;
var r0ind, r1ind : regindex_t;
var r0, r1 : word_t;
var addr : addr_t;
// get opcode.
op = inst2op(instr);
// get operands.
r0ind, r1ind = inst2reg0(instr), inst2reg1(instr);
r0, r1 = regs[r0ind], regs[r1ind];
// get next pc (overwritten by imode/nmode).
pc_next = nextPC(instr, pc, r0);
// get memory address
addr = inst2addr(instr, r0, r1);
// If we are in isolated mode, we only
// set pc_next to isolated address.
assume (mode == isolated_mode) ==> (in_isolated_memory(pc_next));
// If we are in isolated mode, we only
// read from isolated memory.
assume (mode == isolated_mode && op == op_load) ==> in_isolated_memory(addr);
// If we are already in isolated mode,
// we don't execute imodes.
assume (mode == isolated_mode) ==> (op != op_imode_enter);
case
// alu operation.
(op == op_alu) : {
result = aluOp(instr, r0, r1);
regs[r0ind] = result;
}
// load instruction.
(op == op_load) : {
// check permissions.
if (mode == isolated_mode ||
!in_isolated_memory(addr))
{
// perform load
result = dmem[addr];
} else {
// load failed, return 0.
result = common.k0_word_t;
}
regs[r0ind] = result;
}
// store instruction.
(op == op_store) : {
result = common.k0_word_t;
// check permissions.
if (mode == isolated_mode ||
!in_isolated_memory(addr))
{
// perform store.
dmem[addr] = r0;
}
}
// enter isolated mode.
(op == op_imode_enter) : {
assert (mode == normal_mode);
result = common.k0_word_t;
// zero out registers.
havoc regs;
assume (forall (r : regindex_t)
:: regs[r] == common.k0_word_t);
// set pc.
pc_next = common.imode_enter_addr;
mode = isolated_mode;
}
// exit to normal mode.
(op == op_nmode_exit) : {
result = common.k0_word_t;
// zero out registers.
havoc regs;
assume (forall (r : regindex_t)
:: regs[r] == common.k0_word_t);
// set pc.
pc_next = common.nmode_exit_addr;
mode = normal_mode;
}
esac
}
init {
// reset registers.
assume (forall (r : regindex_t)
:: regs[r] == common.k0_word_t);
// set instruction to some deterministic value.
inst = common.k0_word_t;
// start off execution at a deterministic address.
pc = common.nmode_exit_addr;
// in normal mode.
mode = normal_mode;
}
next {
inst' = imem[pc];
call (pc') = exec_inst(inst', pc);
}
}
module main {
// Import types.
type * = common.*;
type regindex_t = cpu.regindex_t;
// Instruction memory for the CPUs.
var imem1, imem2 : mem_t;
// Create two instances of the CPU module.
instance cpu1 : cpu(imem : (imem1));
instance cpu2 : cpu(imem : (imem2));
init {
// Assume same isolated rngs.
assume (cpu1.isolated_rng_lo == cpu2.isolated_rng_lo);
assume (cpu1.isolated_rng_hi == cpu2.isolated_rng_hi);
// Supervisor memory starts off identical.
assume (forall (a : addr_t) :: (cpu.in_rng(a, cpu1.isolated_rng_lo, cpu2.isolated_rng_hi)) ==> (cpu1.dmem[a] == cpu2.dmem[a]));
assume (forall (a : addr_t) :: (cpu.in_rng(a, cpu1.isolated_rng_lo, cpu1.isolated_rng_hi)) ==> (imem1[a] == imem2[a]));
}
next {
next (cpu1); next (cpu2);
// imodes are taken in sync
assume (cpu.inst2op(cpu1.inst) == op_imode_enter || cpu.inst2op(cpu2.inst) == op_imode_enter) ==> (cpu1.inst == cpu2.inst);
}
// PROPERTY: isolated mode memory is identical.
property eq_dmem : (forall (a : addr_t) :: (cpu.in_rng(a, cpu1.isolated_rng_lo, cpu2.isolated_rng_hi)) ==> (cpu1.dmem[a] == cpu2.dmem[a]));
control {
v = induction;
check;
print_results;
v.print_cex(
cpu.inst2op(cpu1.inst), cpu.inst2op(cpu2.inst), cpu1.result, cpu2.result, cpu1.mode, cpu2.mode, cpu1.pc, cpu2.pc, cpu1.isolated_rng_lo, cpu2.isolated_rng_lo, cpu1.isolated_rng_hi, cpu2.isolated_rng_hi, cpu.in_rng(cpu1.pc, cpu1.isolated_rng_lo, cpu1.isolated_rng_hi), cpu.in_rng(cpu2.pc, cpu2.isolated_rng_lo, cpu2.isolated_rng_hi));
}
}