From 4aa2ef7838840e310a1e9a1d23e39929e4245eca Mon Sep 17 00:00:00 2001 From: Nicole Narr Date: Thu, 27 Oct 2022 20:29:03 +0200 Subject: [PATCH] Fix dma_core_wrap, idma_reg64_frontend #15 --- src/frontends/register_64bit/idma_reg64_frontend.sv | 4 +--- src/systems/cva6_reg/dma_core_wrap.sv | 4 ++-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/frontends/register_64bit/idma_reg64_frontend.sv b/src/frontends/register_64bit/idma_reg64_frontend.sv index 30242014..a9a7f3ee 100644 --- a/src/frontends/register_64bit/idma_reg64_frontend.sv +++ b/src/frontends/register_64bit/idma_reg64_frontend.sv @@ -7,8 +7,6 @@ // Description: DMA frontend module that includes 64bit config and status reg handling module idma_reg64_frontend #( - /// address width of the DMA AXI Master port - parameter int unsigned DmaAddrWidth = -1, /// register_interface request type parameter type dma_regs_req_t = logic, /// register_interface response type @@ -38,7 +36,7 @@ module idma_reg64_frontend #( idma_reg64_frontend_reg_pkg::idma_reg64_frontend_hw2reg_t dma_hw2reg; // transaction id - logic [DmaAddrWidth-1:0] next_id, done_id; + logic [DmaRegisterWidth-1:0] next_id, done_id; logic issue; dma_regs_rsp_t dma_ctrl_rsp_tmp; diff --git a/src/systems/cva6_reg/dma_core_wrap.sv b/src/systems/cva6_reg/dma_core_wrap.sv index 7cccdb1c..a7910a05 100644 --- a/src/systems/cva6_reg/dma_core_wrap.sv +++ b/src/systems/cva6_reg/dma_core_wrap.sv @@ -57,7 +57,7 @@ module dma_core_wrap #( `REG_BUS_TYPEDEF_ALL(dma_regs, logic[5:0], logic[63:0], logic[7:0]) - burst_req_t burst_req; + idma_req_t burst_req; logic be_valid, be_ready, be_trans_complete; idma_pkg::idma_busy_t idma_busy; @@ -91,7 +91,7 @@ module dma_core_wrap #( .DmaAddrWidth ( AXI_ADDR_WIDTH ), .dma_regs_req_t ( dma_regs_req_t ), .dma_regs_rsp_t ( dma_regs_rsp_t ), - .burst_req_t ( burst_req_t ) + .burst_req_t ( idma_req_t ) ) i_dma_frontend ( .clk_i, .rst_ni,