From 4456785021e14013f0606276a255f55cd454b83b Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Mon, 31 Oct 2022 12:43:32 +0100 Subject: [PATCH] fixes: Various improvements and fixes --- Bender.yml | 1 - README.md | 4 +-- .../desc64/idma_desc64_reg_wrapper.sv | 8 +++-- src/idma_backend.sv | 9 +++--- src/idma_error_handler.sv | 5 ++++ src/idma_stream_fifo.sv | 13 +++++---- src/include/idma/guard.svh | 29 +++++++++++++++++++ src/legacy/axi_dma_backend.sv | 7 ++--- src/midends/idma_nd_midend.sv | 7 ++--- src/systems/cva6_desc/dma_desc_wrap.sv | 25 ---------------- src/systems/cva6_desc/dma_reg_to_axi.sv | 10 ++++--- src/systems/pulpopen/dmac_wrap.sv | 5 ---- test/tb_idma_backend.sv | 26 +++++++++++++---- test/tb_idma_nd_backend.sv | 26 +++++++++++++---- 14 files changed, 105 insertions(+), 70 deletions(-) create mode 100644 src/include/idma/guard.svh diff --git a/Bender.yml b/Bender.yml index 77610606..610786d6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -76,7 +76,6 @@ sources: - target: cva6 files: - - src/legacy/axi_dma_backend.sv - src/systems/cva6_reg/dma_core_wrap.sv - target: synthesis diff --git a/README.md b/README.md index f6486efe..923ae239 100644 --- a/README.md +++ b/README.md @@ -54,12 +54,12 @@ We currently do not include any free and open-source simulation setup. However, [*Questa advanced simulator*](https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/), a simulation can be launched using: -``` +```bash make prepare_sim vsim -c -do "source scripts/compile_vsim.tcl; quit" vsim -c -t 1ps -voptargs=+acc \ +job_file=jobs/backend/man_simple.txt \ - -logfile logs/backend.simple.vsim.log + -logfile logs/backend.simple.vsim.log \ -wlf logs/backend.simple.wlf \ tb_idma_backend \ -do "source scripts/start_vsim.tcl; run -all" diff --git a/src/frontends/desc64/idma_desc64_reg_wrapper.sv b/src/frontends/desc64/idma_desc64_reg_wrapper.sv index 1c06a1c6..24457b24 100644 --- a/src/frontends/desc64/idma_desc64_reg_wrapper.sv +++ b/src/frontends/desc64/idma_desc64_reg_wrapper.sv @@ -5,12 +5,14 @@ // Axel Vanoni `include "common_cells/registers.svh" -import idma_desc64_reg_pkg::idma_desc64_reg2hw_t; -import idma_desc64_reg_pkg::idma_desc64_hw2reg_t; + + /// This module implements backpressure via ready/valid handshakes /// for the regbus registers and exposes it to the descriptor fifo -module idma_desc64_reg_wrapper #( +module idma_desc64_reg_wrapper +import idma_desc64_reg_pkg::idma_desc64_reg2hw_t; +import idma_desc64_reg_pkg::idma_desc64_hw2reg_t; #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic ) ( diff --git a/src/idma_backend.sv b/src/idma_backend.sv index e181c91a..82d3b461 100644 --- a/src/idma_backend.sv +++ b/src/idma_backend.sv @@ -5,6 +5,7 @@ // Thomas Benz `include "axi/typedef.svh" +`include "idma/guard.svh" /// The iDMA backend implements an arbitrary 1D copy engine using the AXI4 protocol. module idma_backend #( @@ -478,7 +479,9 @@ module idma_backend #( assign busy_o.eh_cnt_busy = 1'b0; end else begin : gen_param_error + `IDMA_NONSYNTH_BLOCK( $fatal(1, "Unexpected Error Capability"); + ) end @@ -672,8 +675,7 @@ module idma_backend #( //-------------------------------------- // Assertions //-------------------------------------- - // pragma translate_off - `ifndef VERILATOR + `IDMA_NONSYNTH_BLOCK( initial begin : proc_assert_params axi_addr_width : assert(AddrWidth >= 32'd12) else $fatal(1, "Parameter `AddrWidth` has to be >= 12!"); @@ -693,7 +695,6 @@ module idma_backend #( tf_len_width_max : assert(TFLenWidth <= AddrWidth) else $fatal(1, "Parameter `TFLenWidth` has to be <= `AddrWidth`!"); end - `endif - // pragma translate_on + ) endmodule : idma_backend diff --git a/src/idma_error_handler.sv b/src/idma_error_handler.sv index 26a61499..4cbe8880 100644 --- a/src/idma_error_handler.sv +++ b/src/idma_error_handler.sv @@ -5,6 +5,7 @@ // Thomas Benz `include "common_cells/registers.svh" +`include "idma/guard.svh" /// Handles AXI read and write error on the manager interface. /// Currently two modes are supported: @@ -297,7 +298,9 @@ module idma_error_handler #( // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin + `IDMA_NONSYNTH_BLOCK( $fatal(1, "No active transfer to handle!"); + ) end end end @@ -330,7 +333,9 @@ module idma_error_handler #( // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin + `IDMA_NONSYNTH_BLOCK( $fatal(1, "No active transfer to handle!"); + ) end end end diff --git a/src/idma_stream_fifo.sv b/src/idma_stream_fifo.sv index b6de92d9..73f7d335 100644 --- a/src/idma_stream_fifo.sv +++ b/src/idma_stream_fifo.sv @@ -5,6 +5,7 @@ // Thomas Benz `include "common_cells/assertions.svh" +`include "idma/guard.svh" /// Optimal implementation of a stream FIFO based on the common cells modules. module idma_stream_fifo #( @@ -36,13 +37,13 @@ module idma_stream_fifo #( // Prevent Depth 0 and 1 //-------------------------------------- // Throw an error if depth is 0 or 1 - // pragma translate off + `IDMA_NONSYNTH_BLOCK( if (Depth < 32'd2) begin : gen_fatal initial begin $fatal(1, "FIFO of depth %d does not make any sense!", Depth); end end - // pragma translate on + ) //-------------------------------------- // Spill register (depth 2) @@ -51,13 +52,13 @@ module idma_stream_fifo #( if (Depth == 32'd2) begin : gen_spill // print info - // pragma translate off + `IDMA_NONSYNTH_BLOCK( if (PrintInfo) begin : gen_info initial begin $display("[%m] Instantiate spill register (of depth %d)", Depth); end end - // pragma translate on + ) // spill register spill_register_flushable #( @@ -92,13 +93,13 @@ module idma_stream_fifo #( if (Depth > 32'd2) begin : gen_fifo // print info - // pragma translate off + `IDMA_NONSYNTH_BLOCK( if (PrintInfo) begin : gen_info initial begin $info("[%m] Instantiate stream FIFO of depth %d", Depth); end end - // pragma translate on + ) // stream fifo stream_fifo #( diff --git a/src/include/idma/guard.svh b/src/include/idma/guard.svh new file mode 100644 index 00000000..cddea6ad --- /dev/null +++ b/src/include/idma/guard.svh @@ -0,0 +1,29 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Thomas Benz + +// Guard macros for non-synthesizable code + +`ifndef IDMA_GUARD_SVH_ +`define IDMA_GUARD_SVH_ + +`define IDMA_NONSYNTH_BLOCK(__block) \ +`ifndef TARGET_SYNTHESIS \ +`ifndef TARGET_VERILATOR \ +`ifndef TARGET_XSIM \ +`ifndef VERILATOR \ +`ifndef SYNTHESIS \ +`ifndef XSIM \ +/* pragma translate_off */ \ +__block \ +/* pragma translate_on */ \ +`endif \ +`endif \ +`endif \ +`endif \ +`endif \ +`endif + +`endif diff --git a/src/legacy/axi_dma_backend.sv b/src/legacy/axi_dma_backend.sv index 1cea794b..20cce510 100644 --- a/src/legacy/axi_dma_backend.sv +++ b/src/legacy/axi_dma_backend.sv @@ -5,6 +5,7 @@ // Michael Rogenmoser `include "idma/typedef.svh" +`include "idma/guard.svh" /// This is a wrapper for the new backend to emulate the old one module axi_dma_backend #( @@ -72,13 +73,11 @@ module axi_dma_backend #( // This wrapper emulates the old (v.0.1.0) backend which is deprecated. Throw a warning here // to inform the user in simulation - // pragma translate_off - `ifndef VERILATOR + `IDMA_NONSYNTH_BLOCK( initial begin : proc_deprecated_warning $warning("You are using the deprecated interface of the backend. Please update ASAP!"); end - `endif - // pragma translate_on + ) // Parameters unavailable to old backend localparam int unsigned TFLenWidth = AddrWidth; diff --git a/src/midends/idma_nd_midend.sv b/src/midends/idma_nd_midend.sv index aa8107d3..c7b47956 100644 --- a/src/midends/idma_nd_midend.sv +++ b/src/midends/idma_nd_midend.sv @@ -5,6 +5,7 @@ // Thomas Benz `include "common_cells/registers.svh" +`include "idma/guard.svh" /// ND midend for the iDMA. This module takes an n-dimensional transfer and splits it into /// individual 1d transfers handed to the backend. @@ -236,14 +237,12 @@ module idma_nd_midend #( //-------------------------------------- // Assertions //-------------------------------------- - // pragma translate_off - `ifndef VERILATOR + `IDMA_NONSYNTH_BLOCK( initial begin : proc_assert_params num_dim : assert(NumDim >= 32'd2) else $fatal(1, "Parameter `NumDim` has to be >= 2!"); end - `endif - // pragma translate_on + ) endmodule : idma_nd_midend diff --git a/src/systems/cva6_desc/dma_desc_wrap.sv b/src/systems/cva6_desc/dma_desc_wrap.sv index 5e361baf..7d3b86cc 100644 --- a/src/systems/cva6_desc/dma_desc_wrap.sv +++ b/src/systems/cva6_desc/dma_desc_wrap.sv @@ -138,31 +138,6 @@ module dma_desc_wrap #( .busy_o ( idma_busy ) ); - // axi_dma_backend #( - // .DataWidth (AxiDataWidth), - // .AddrWidth (AxiAddrWidth), - // .IdWidth (AxiIdWidth-1), - // .AxReqFifoDepth(4), - // .TransFifoDepth(4), - // .BufferDepth (4), - // .axi_req_t (dma_axi_mst_post_mux_req_t), - // .axi_res_t (dma_axi_mst_post_mux_resp_t), - // .burst_req_t (burst_req_t), - // .DmaIdWidth (1), - // .DmaTracing (0) - // ) i_dma_backend ( - // .clk_i (clk_i), - // .rst_ni (rst_ni), - // .axi_dma_req_o (axi_be_mst_req), - // .axi_dma_res_i (axi_be_mst_rsp), - // .burst_req_i (dma_be_req), - // .valid_i (dma_be_valid), - // .ready_o (dma_be_ready), - // .backend_idle_o (dma_be_idle), - // .trans_complete_o(dma_be_tx_complete), - // .dma_id_i (1'h1) - // ); - axi_mux #( .SlvAxiIDWidth(AxiIdWidth - 1), .slv_aw_chan_t(dma_axi_mst_post_mux_aw_chan_t), diff --git a/src/systems/cva6_desc/dma_reg_to_axi.sv b/src/systems/cva6_desc/dma_reg_to_axi.sv index 5ed3be85..10d199c1 100644 --- a/src/systems/cva6_desc/dma_reg_to_axi.sv +++ b/src/systems/cva6_desc/dma_reg_to_axi.sv @@ -5,6 +5,8 @@ // Axel Vanoni `include "common_cells/registers.svh" +`include "idma/guard.svh" + /// Hacky register interface to AXI converter module dma_reg_to_axi #( parameter type axi_req_t = logic, @@ -86,13 +88,13 @@ module dma_reg_to_axi #( /* Ignore axi_rsp_i.r.last (ever only bursts of size 1) */ /* Ignore axi_rsp_i.r.user */ assign reg_rsp_o.error = '0; /* swallow errors */ + /* check that we don't get any errors in the simulation */ - // pragma translate_off -`ifndef VERILATOR + `IDMA_NONSYNTH_BLOCK( assert property (@(posedge clk_i) (axi_rsp_i.r_valid && axi_req_o.r_ready) |-> \ (axi_rsp_i.r.resp == axi_pkg::RESP_OKAY)); -`endif - // pragma translate_on + ) + assign reg_rsp_o.ready = ( reg_req_i.write && axi_rsp_i.w_ready) || (!reg_req_i.write && axi_rsp_i.r_valid); diff --git a/src/systems/pulpopen/dmac_wrap.sv b/src/systems/pulpopen/dmac_wrap.sv index 2428269c..800d953d 100644 --- a/src/systems/pulpopen/dmac_wrap.sv +++ b/src/systems/pulpopen/dmac_wrap.sv @@ -432,11 +432,6 @@ module dmac_wrap #( tcdm_master[2].r_data, tcdm_master[3].r_data } ) ); - // tie-off TCDM master port - // for (genvar i = 0; i < 4; i++) begin : gen_tie_off_unused_tcdm_master - // assign tcdm_master[i].r_opc = '0; - // end - // flip we polarity assign tcdm_master[0].wen = !tcdm_master_we_0; assign tcdm_master[1].wen = !tcdm_master_we_1; diff --git a/test/tb_idma_backend.sv b/test/tb_idma_backend.sv index a5dd7e4b..8219c3b2 100644 --- a/test/tb_idma_backend.sv +++ b/test/tb_idma_backend.sv @@ -190,10 +190,24 @@ module tb_idma_backend import idma_pkg::*; #( .ApplDelay ( TA ), .AcqDelay ( TT ) ) i_axi_sim_mem ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_req_i ( axi_req_mem ), - .axi_rsp_o ( axi_rsp_mem ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( axi_req_mem ), + .axi_rsp_o ( axi_rsp_mem ), + .mon_r_last_o ( /* NOT CONNECTED */ ), + .mon_r_beat_count_o ( /* NOT CONNECTED */ ), + .mon_r_user_o ( /* NOT CONNECTED */ ), + .mon_r_id_o ( /* NOT CONNECTED */ ), + .mon_r_data_o ( /* NOT CONNECTED */ ), + .mon_r_addr_o ( /* NOT CONNECTED */ ), + .mon_r_valid_o ( /* NOT CONNECTED */ ), + .mon_w_last_o ( /* NOT CONNECTED */ ), + .mon_w_beat_count_o ( /* NOT CONNECTED */ ), + .mon_w_user_o ( /* NOT CONNECTED */ ), + .mon_w_id_o ( /* NOT CONNECTED */ ), + .mon_w_data_o ( /* NOT CONNECTED */ ), + .mon_w_addr_o ( /* NOT CONNECTED */ ), + .mon_w_valid_o ( /* NOT CONNECTED */ ) ); @@ -213,8 +227,8 @@ module tb_idma_backend import idma_pkg::*; #( signal_highlighter #(.T(idma_eh_req_t)) i_eh_hl (.ready_i(eh_req_ready), .valid_i(eh_req_valid), .data_i(idma_eh_req)); // Watchdogs - stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_w_watchdog (.clk_i(clk), .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready)); - stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_r_watchdog (.clk_i(clk), .valid_i(axi_rsp.r_valid), .ready_i(axi_req.r_ready)); + stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_w_watchdog (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready)); + stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_r_watchdog (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_rsp.r_valid), .ready_i(axi_req.r_ready)); //-------------------------------------- diff --git a/test/tb_idma_nd_backend.sv b/test/tb_idma_nd_backend.sv index ef347659..be82339e 100644 --- a/test/tb_idma_nd_backend.sv +++ b/test/tb_idma_nd_backend.sv @@ -232,10 +232,24 @@ module tb_idma_nd_backend import idma_pkg::*; #( .ApplDelay ( TA ), .AcqDelay ( TT ) ) i_axi_sim_mem ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_req_i ( axi_req_mem ), - .axi_rsp_o ( axi_rsp_mem ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( axi_req_mem ), + .axi_rsp_o ( axi_rsp_mem ), + .mon_r_last_o ( /* NOT CONNECTED */ ), + .mon_r_beat_count_o ( /* NOT CONNECTED */ ), + .mon_r_user_o ( /* NOT CONNECTED */ ), + .mon_r_id_o ( /* NOT CONNECTED */ ), + .mon_r_data_o ( /* NOT CONNECTED */ ), + .mon_r_addr_o ( /* NOT CONNECTED */ ), + .mon_r_valid_o ( /* NOT CONNECTED */ ), + .mon_w_last_o ( /* NOT CONNECTED */ ), + .mon_w_beat_count_o ( /* NOT CONNECTED */ ), + .mon_w_user_o ( /* NOT CONNECTED */ ), + .mon_w_id_o ( /* NOT CONNECTED */ ), + .mon_w_data_o ( /* NOT CONNECTED */ ), + .mon_w_addr_o ( /* NOT CONNECTED */ ), + .mon_w_valid_o ( /* NOT CONNECTED */ ) ); @@ -257,8 +271,8 @@ module tb_idma_nd_backend import idma_pkg::*; #( signal_highlighter #(.T(idma_eh_req_t)) i_eh_hl (.ready_i(eh_req_ready), .valid_i(eh_req_valid), .data_i(idma_eh_req)); // Watchdogs - stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_w_watchdog (.clk_i(clk), .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready)); - stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_r_watchdog (.clk_i(clk), .valid_i(axi_rsp.r_valid), .ready_i(axi_req.r_ready)); + stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_w_watchdog (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready)); + stream_watchdog #(.NumCycles(WatchDogNumCycles)) i_axi_r_watchdog (.clk_i(clk), .rst_ni(rst_n), .valid_i(axi_rsp.r_valid), .ready_i(axi_req.r_ready)); //--------------------------------------