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                          Copyright 2012-2020 / Enjoy-Digital

License

Welcome to LiteX!

LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU). The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.

Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.

Want to get started and/or looking for documentation? Make sure to visit the Wiki!

A question or want to get in touch? Our IRC channel is #litex at freenode.net

Typical LiteX design flow:

                                      +---------------+
                                      |FPGA toolchains|
                                      +----^-----+----+
                                           |     |
                                        +--+-----v--+
                       +-------+        |           |
                       | Migen +-------->           |
                       +-------+        |           |        Your design
                                        |   LiteX   +---> ready to be used!
                                        |           |
              +----------------------+  |           |
              |LiteX Cores Ecosystem +-->           |
              +----------------------+  +-^-------^-+
               (Eth, SATA, DRAM, USB,     |       |
                PCIe, Video, etc...)      +       +
                                         board   target
                                         file    file

LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:

Name Build Status Description
LiteX-Boards Boards support
LiteDRAM DRAM
LiteEth Ethernet
LitePCIe PCIe
LiteSATA SATA
LiteSDCard SD card
LiteICLink Inter-Chip communication
LiteJESD204B JESD204B
LiteVideo VGA, DVI, HDMI
LiteScope Logic analyzer

By combining LiteX with the ecosystem of cores, creating complex SoCs becomes easier than with traditional tools while providing better portability and flexibility. Here are some projects created recently with the tools:

A Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA and integrated with LiteX: For more info, have a look at Linux-on-LiteX-Vexriscv project and try running Linux on your FPGA board!

A custom PCIe SDI Capture/Playback board built around LitePCIe and integrated with LiteX, allowing full control of the SDI flow and very low latency. To discover more products/projects built with LiteX, visit the projects page on the Wiki.

Papers, Presentations, Tutorials, Links

FPGA lessons/tutorials:

Migen tutorial:

OSDA 2019 paper/slides:

Linux on LiteX-Vexriscv:

RISC-V Getting Started Guide:

LiteX vs. Vivado First Impressions:

35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:

Tim has to many projects - LatchUp Edition: https://www.youtube.com/watch?v=v7WrTmexod0

Sub-packages

litex.gen Provides specific or experimental modules to generate HDL that are not integrated in Migen.

litex.build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.

litex.soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.

Quick start guide

  1. Install Python 3.6+ and FPGA vendor's development tools and/or Verilator.
  2. Install Migen/LiteX and the LiteX's cores:
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ ./litex_setup.py init install --user (--user to install to user directory)

Later, if you need to update all repositories:

$ ./litex_setup.py update

Note: On MacOS, make sure you have HomeBrew installed. Then do, brew install wget.

Note: On Windows, it's possible you'll have to set SHELL environment variable to SHELL=cmd.exe.

  1. Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):
$ ./litex_setup.py gcc
  1. Build the target of your board...:

Go to litex-boards/litex_boards/targets and execute the target you want to build.

  1. ... and/or install Verilator and test LiteX directly on your computer without any FPGA board:

On Linux (Ubuntu):

$ sudo apt install libevent-dev libjson-c-dev verilator
$ lxsim --cpu-type=vexriscv

On MacOS:

$ brew install json-c verilator libevent
$ brew cask install tuntap
$ lxsim --cpu-type=vexriscv
  1. Run a terminal program on the board's serial port at 115200 8-N-1.

You should get the BIOS prompt like the one below.

Community

LiteX has been initially developed by EnjoyDigital to create custom SoCs/Systems for our clients (and we are still using it for that purpose :)); but over the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found at https://github.com/litex-hub.

Contact

E-mail: florent@enjoy-digital.fr