Updated tb.v VPWR/VGND ports to match newer template tb.v

rejunity · Nov 2, 2024 · 2fe68df · 2fe68df
1 parent 105013b
commit 2fe68df
Showing 1 changed file with 9 additions and 4 deletions.
diff --git a/test/tb.v b/test/tb.v
@@ -25,14 +25,19 @@ module tb ();
     wire clk;
     wire rst_n;
     wire ena;
+`ifdef GL_TEST
+    wire VPWR = 1'b1;
+    wire VGND = 1'b0;
+`endif
+
 
     tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut 
     (
         // include power ports for the Gate Level test
-        `ifdef GL_TEST
-            .VPWR( 1'b1),
-            .VGND( 1'b0),
-        `endif
+`ifdef GL_TEST
+        .VPWR(VPWR),
+        .VGND(VGND),
+`endif
         .ui_in      (ui_in),    // Dedicated inputs
         .uo_out     (uo_out),   // Dedicated outputs
         .uio_in     (uio_in),   // IOs: Input path