From 2fe68df12bd6692c738accb0b81e35b68fffb5a4 Mon Sep 17 00:00:00 2001 From: rej Date: Sat, 2 Nov 2024 23:04:30 +0100 Subject: [PATCH] Updated tb.v VPWR/VGND ports to match newer template tb.v --- test/tb.v | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/test/tb.v b/test/tb.v index 105b2bb..f7af20a 100644 --- a/test/tb.v +++ b/test/tb.v @@ -25,14 +25,19 @@ module tb (); wire clk; wire rst_n; wire ena; +`ifdef GL_TEST + wire VPWR = 1'b1; + wire VGND = 1'b0; +`endif + tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut ( // include power ports for the Gate Level test - `ifdef GL_TEST - .VPWR( 1'b1), - .VGND( 1'b0), - `endif +`ifdef GL_TEST + .VPWR(VPWR), + .VGND(VGND), +`endif .ui_in (ui_in), // Dedicated inputs .uo_out (uo_out), // Dedicated outputs .uio_in (uio_in), // IOs: Input path