From 1b4a994e3f524e6c9f48f7f2a59ece61d9bbebf6 Mon Sep 17 00:00:00 2001 From: Flex Software Development Robot Date: Thu, 9 Nov 2023 22:44:57 +0000 Subject: [PATCH] Release v5.0.1 --- README.md | 4 +- SUPPORTED_SOFTWARE.md | 2 +- ra/fsp/inc/fsp_version.h | 6 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.c | 26 +++++++- ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h | 9 +-- .../rm_at_transport_da16xxx_uart.c | 22 +++---- ra/fsp/src/rm_emwin_port/GUI_X_OS.c | 12 ++-- ra/fsp/src/rm_freertos_port/port.c | 61 +++++++++++-------- .../tx_port_wait_thread_ready.c | 47 ++++++++------ .../src/rm_threadx_port/tx_thread_schedule.c | 57 +++++++++-------- 10 files changed, 146 insertions(+), 100 deletions(-) diff --git a/README.md b/README.md index 58d3af45a..f3b83a259 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v5.0.0](https://github.com/renesas/fsp/releases/tag/v5.0.0) +[FSP v5.0.1](https://github.com/renesas/fsp/releases/tag/v5.0.1) ### Supported RA MCU Kits @@ -85,7 +85,7 @@ When using the zipped version of the packs the zip file should be extracted into #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.0.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.0.1). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index e2e281b94..85a2601b3 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -361,7 +361,7 @@ * [Crypto AES2](https://renesas.github.io/fsp/) * [Crypto RA2](https://renesas.github.io/fsp/) * [FreeRTOS MbedTLS Port](https://renesas.github.io/fsp/) - * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___s_c_e___k_e_y___i_n_j_e_c_t_i_o_n.html) + * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___r_s_i_p___k_e_y___i_n_j_e_c_t_i_o_n.html) * [MCUBoot TinyCrypt H/W Acceleration (rm_mcuboot_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html) * [MCUboot TinyCrypt (H/W Accelerated)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst) * [MCUboot TinyCrypt (S/W Only)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst) diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index a35315706..09e06ddab 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -48,16 +48,16 @@ extern "C" { #define FSP_VERSION_MINOR (0U) /** FSP pack patch version. */ - #define FSP_VERSION_PATCH (0U) + #define FSP_VERSION_PATCH (1U) /** FSP pack version build number (currently unused). */ #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("5.0.0") + #define FSP_VERSION_STRING ("5.0.1") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.0.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.0.1") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index ff9144daf..195e3d154 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -954,6 +954,8 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR]) { #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + bool post_div_set_delay = false; + if ((clock_freq_hz_post_change > SystemCoreClock) && ((clock_freq_hz_post_change - SystemCoreClock) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) { @@ -995,6 +997,9 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) /* Wait for settling delay. */ SystemCoreClockUpdate(); R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Trigger delay after setting dividers */ + post_div_set_delay = true; } /* Continue and set clock to actual target speed. */ #endif @@ -1002,8 +1007,21 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) /* Set the clock dividers before switching to the new clock source. */ prv_clock_dividers_set(sckdivcr, sckdivcr2); - /* Switch to the new clock source. */ - R_SYSTEM->SCKSCR = (uint8_t) clock; +#if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + if (post_div_set_delay) + { + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + /* Wait for settling delay. */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else +#endif + { + /* Switch to the new clock source. */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + } } /* Switching to a slower source clock. */ else @@ -1206,6 +1224,10 @@ static void bsp_prv_clock_set_hard_reset (void) /* Continue and set clock to actual target speed. */ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); #else #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h index 8e3fe9357..3e4c2dc32 100644 --- a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h @@ -30,12 +30,13 @@ **********************************************************************************************************************/ /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#define CGC_MOMCR_RESERVED_MASK (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */ #if (BSP_CFG_XTAL_HZ > (24000000)) - #define CGC_MAINCLOCK_DRIVE (0x05U) + #define CGC_MAINCLOCK_DRIVE (0x05U | CGC_MOMCR_RESERVED_MASK) #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000)) - #define CGC_MAINCLOCK_DRIVE (0x03U) + #define CGC_MAINCLOCK_DRIVE (0x03U | CGC_MOMCR_RESERVED_MASK) #else - #define CGC_MAINCLOCK_DRIVE (0x00U) + #define CGC_MAINCLOCK_DRIVE (0x00U | CGC_MOMCR_RESERVED_MASK) #endif /*********************************************************************************************************************** @@ -185,7 +186,7 @@ #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) -#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) +#define BSP_FEATURE_CGC_MODRV_MASK (0x1EU) #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) #define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) #define BSP_FEATURE_CGC_PLL_OUT_P_MAX_HZ (480000000U) diff --git a/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c b/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c index 1c06d9618..89444c68f 100644 --- a/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c +++ b/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c @@ -928,6 +928,12 @@ static void rm_at_transport_da16xxx_cleanup_open (at_transport_da16xxx_ctrl_t * p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT] = NULL; } + uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT]; + if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) + { + p_uart->p_api->close(p_uart->p_ctrl); + } + if (p_instance_ctrl->num_uarts > 1) { if (NULL != p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT]) @@ -935,18 +941,12 @@ static void rm_at_transport_da16xxx_cleanup_open (at_transport_da16xxx_ctrl_t * vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT]); p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT] = NULL; } - } - - uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT]; - if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) - { - p_uart->p_api->close(p_uart->p_ctrl); - } - p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT]; - if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) - { - p_uart->p_api->close(p_uart->p_ctrl); + p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT]; + if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) + { + p_uart->p_api->close(p_uart->p_ctrl); + } } } diff --git a/ra/fsp/src/rm_emwin_port/GUI_X_OS.c b/ra/fsp/src/rm_emwin_port/GUI_X_OS.c index 8529c0abc..b6b124b76 100644 --- a/ra/fsp/src/rm_emwin_port/GUI_X_OS.c +++ b/ra/fsp/src/rm_emwin_port/GUI_X_OS.c @@ -83,19 +83,15 @@ void GUI_X_Delay (int Period) #else uint32_t time_start = g_gui_time_ms; - #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); - #endif - /* Wait for the specified number of ticks */ do { + #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP __WFI(); - } while ((int) (g_gui_time_ms - time_start) < Period); - - #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bsp_prv_clock_prepare_post_sleep(clock_slowed); + #else + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); #endif + } while ((int) (g_gui_time_ms - time_start) < Period); #endif } diff --git a/ra/fsp/src/rm_freertos_port/port.c b/ra/fsp/src/rm_freertos_port/port.c index e20ef4c1b..2eb2f16be 100644 --- a/ra/fsp/src/rm_freertos_port/port.c +++ b/ra/fsp/src/rm_freertos_port/port.c @@ -1297,7 +1297,9 @@ void vPortExitCritical (void) **********************************************************************************************************************/ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) { + #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP uint32_t saved_lpm_state = 0U; + #endif /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can * set its parameter to 0 to indicate that its implementation contains @@ -1307,16 +1309,18 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) configPRE_SLEEP_PROCESSING(xExpectedIdleTime); if (xExpectedIdleTime > 0) { + #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP + /* Save LPM Mode */ - #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY saved_lpm_state = R_SYSTEM->SBYCR; - #elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR saved_lpm_state = R_SYSTEM->LPSCR; - #endif + #endif /** Check if the LPM peripheral is set to go to Software Standby mode with WFI instruction. * If so, change the LPM peripheral to go to Sleep mode. */ - #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (R_SYSTEM_SBYCR_SSBY_Msk & saved_lpm_state) { /* Save register protect value */ @@ -1332,43 +1336,39 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); } - #elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR if (R_SYSTEM_LPSCR_LPMD_Msk & saved_lpm_state) { - #if BSP_TZ_NONSECURE_BUILD + #if BSP_TZ_NONSECURE_BUILD /* Save register protect value */ uint32_t saved_prcr = R_SYSTEM->PRCR_NS; /* Unlock LPM peripheral registers */ R_SYSTEM->PRCR_NS = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS; - #else + #else /* Save register protect value */ uint32_t saved_prcr = R_SYSTEM->PRCR; /* Unlock LPM peripheral registers */ R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS; - #endif + #endif /* Clear to set to sleep low power mode (not standby or deep standby) */ R_SYSTEM->LPSCR = 0U; - #if BSP_TZ_NONSECURE_BUILD + #if BSP_TZ_NONSECURE_BUILD /* Restore register lock */ R_SYSTEM->PRCR_NS = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); - #else + #else /* Restore register lock */ R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); - #endif + #endif } - #endif - - #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); - #endif + #endif /** * DSB should be last instruction executed before WFI @@ -1384,10 +1384,14 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) /* Instruction Synchronization Barrier. */ __ISB(); + #else - #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bsp_prv_clock_prepare_post_sleep(clock_slowed); - #endif + /* Wait for an interrupt to be pending without going to sleep if BSP is configured to not sleep when idle for RTOS. */ + while (0 == (SCB->ICSR & SCB_ICSR_VECTPENDING_Msk)) + { + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);; + } + #endif /* !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP */ /* Re-enable interrupts to allow the interrupt that brought the MCU * out of sleep mode to execute immediately. This will not cause a @@ -1401,9 +1405,11 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) configPOST_SLEEP_PROCESSING(xExpectedIdleTime); + #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP + /** Check if the LPM peripheral was supposed to go to Software Standby mode with WFI instruction. * If yes, restore the LPM peripheral setting. */ - #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (R_SYSTEM_SBYCR_SSBY_Msk & saved_lpm_state) { /* Save register protect value */ @@ -1419,38 +1425,39 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime) R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); } - #elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR if (R_SYSTEM_LPSCR_LPMD_Msk & saved_lpm_state) { - #if BSP_TZ_NONSECURE_BUILD + #if BSP_TZ_NONSECURE_BUILD /* Save register protect value */ uint32_t saved_prcr = R_SYSTEM->PRCR_NS; /* Unlock LPM peripheral registers */ R_SYSTEM->PRCR_NS = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS; - #else + #else /* Save register protect value */ uint32_t saved_prcr = R_SYSTEM->PRCR; /* Unlock LPM peripheral registers */ R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS; - #endif + #endif /* Restore LPM Mode */ R_SYSTEM->LPSCR = (uint8_t) saved_lpm_state; - #if BSP_TZ_NONSECURE_BUILD + #if BSP_TZ_NONSECURE_BUILD /* Restore register lock */ R_SYSTEM->PRCR_NS = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); - #else + #else /* Restore register lock */ R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr); - #endif + #endif } + #endif #endif } diff --git a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c index f08ab3467..1d93c1902 100644 --- a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c +++ b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c @@ -81,8 +81,10 @@ extern TX_THREAD * volatile _tx_thread_execute_ptr; /* These variables are global because this function is called from PendSV_Handler, which is a stackless * function. */ +#if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP static volatile uint16_t g_saved_lpm_state = 0U; static volatile uint32_t g_prcr = 0U; +#endif void * _tx_port_wait_thread_ready (void) { /* The following compile time assertions validate offsets used in the assembly code @@ -111,6 +113,24 @@ void * _tx_port_wait_thread_ready (void) TX_THREAD * new_thread_ptr; +#if defined(BSP_CFG_RTOS_IDLE_SLEEP) && (0 == BSP_CFG_RTOS_IDLE_SLEEP) + while (1) + { + /* Make the new thread the current thread. */ + new_thread_ptr = _tx_thread_execute_ptr; + _tx_thread_current_ptr = new_thread_ptr; + + /* If non-NULL, a new thread is ready! */ + if (new_thread_ptr != 0) + { + /* At this point, we have a new thread ready to go. */ + break; + } + + /* Short delay to prevent bus thrashing */ + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); + } +#else while (1) { /* Disable interrupts - The next block is critical. Interrupts are disabled with PRIMASK event if @@ -138,13 +158,13 @@ void * _tx_port_wait_thread_ready (void) } /* Save LPM Mode */ -#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY g_saved_lpm_state = R_SYSTEM->SBYCR; -#elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR g_saved_lpm_state = R_SYSTEM->LPSCR; -#endif + #endif -#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY /* Check if the LPM peripheral is set to go to Software Standby mode with WFI instruction. * If yes, change the LPM peripheral to go to Sleep mode. Otherwise skip following procedures @@ -161,7 +181,7 @@ void * _tx_port_wait_thread_ready (void) /* Clear to set to sleep low power mode (not standby or deep standby) */ R_SYSTEM->SBYCR = g_saved_lpm_state & (uint16_t) ~R_SYSTEM_SBYCR_SSBY_Msk; } -#elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR if (R_SYSTEM_LPSCR_LPMD_Msk & g_saved_lpm_state) { /* Save register protect value */ @@ -173,11 +193,7 @@ void * _tx_port_wait_thread_ready (void) /* Clear to set to sleep low power mode (not standby or deep standby) */ R_SYSTEM->LPSCR = 0U; } -#endif - -#if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); -#endif + #endif /** * DSB should be last instruction executed before WFI @@ -193,11 +209,7 @@ void * _tx_port_wait_thread_ready (void) /* Instruction Synchronization Barrier. */ __ISB(); -#if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - bsp_prv_clock_prepare_post_sleep(clock_slowed); -#endif - -#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY /* Check if the LPM peripheral was supposed to go to Software Standby mode with WFI instruction. * If yes, restore the LPM peripheral setting. Otherwise skip following procedures to avoid the @@ -211,7 +223,7 @@ void * _tx_port_wait_thread_ready (void) /* Restore register lock */ R_SYSTEM->PRCR = (uint16_t) (RM_THREADX_PORT_PRCR_LOCK_LPM_REGISTER_ACCESS | g_prcr); } -#elif BSP_FEATURE_LPM_HAS_LPSCR + #elif BSP_FEATURE_LPM_HAS_LPSCR if (R_SYSTEM_LPSCR_LPMD_Msk & g_saved_lpm_state) { /* Restore LPM Mode */ @@ -220,12 +232,13 @@ void * _tx_port_wait_thread_ready (void) /* Restore register lock */ R_SYSTEM->PRCR = (uint16_t) (RM_THREADX_PORT_PRCR_LOCK_LPM_REGISTER_ACCESS | g_prcr); } -#endif + #endif /* Re-enable interrupts. */ __enable_irq(); __ISB(); } +#endif return new_thread_ptr; } diff --git a/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c b/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c index fd86e75ae..d657dcfcf 100644 --- a/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c +++ b/ra/fsp/src/rm_threadx_port/tx_thread_schedule.c @@ -1,4 +1,5 @@ /**************************************************************************/ + /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ @@ -9,7 +10,6 @@ /* */ /**************************************************************************/ - /**************************************************************************/ /**************************************************************************/ /** */ @@ -69,9 +69,9 @@ * overflow because PSP is not used in handler mode. TX_PORT_SCHEDULER_STACK is used to move PSPLIM to account for * this. TX_PORT_SCHEDULER_STACK must be a multiple of 8. */ #if __FPU_USED -#define TX_PORT_SCHEDULER_STACK 40 + #define TX_PORT_SCHEDULER_STACK 40 #else -#define TX_PORT_SCHEDULER_STACK 32 + #define TX_PORT_SCHEDULER_STACK 32 #endif /* The following macros are defined as hard coded numbers so they can be converted to strings in the @@ -115,7 +115,6 @@ extern volatile UINT _tx_thread_preempt_disable; const uint32_t g_secure_stack_offset = offsetof(TX_THREAD, tx_thread_secure_stack_context); #endif - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -238,7 +237,7 @@ VOID _tx_thread_schedule (VOID) /* These variables are global because this function is called from PendSV_Handler, which is a stackless * function. */ -__attribute((weak)) void * _tx_port_wait_thread_ready (VOID) +__attribute((weak)) void * _tx_port_wait_thread_ready(VOID) { /* The following is the idle wait processing. In this case, no threads are ready for execution and the * system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts @@ -246,6 +245,24 @@ __attribute((weak)) void * _tx_port_wait_thread_ready (VOID) TX_THREAD * new_thread_ptr; +#if defined(BSP_CFG_RTOS_IDLE_SLEEP) && (0 == BSP_CFG_RTOS_IDLE_SLEEP) + while (1) + { + /* Make the new thread the current thread. */ + new_thread_ptr = _tx_thread_execute_ptr; + _tx_thread_current_ptr = new_thread_ptr; + + /* If non-NULL, a new thread is ready! */ + if (new_thread_ptr != 0) + { + /* At this point, we have a new thread ready to go. */ + break; + } + + /* Short delay to prevent bus thrashing */ + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); + } +#else while (1) { /* Disable interrupts - The next block is critical. Interrupts are disabled with PRIMASK event if @@ -272,11 +289,6 @@ __attribute((weak)) void * _tx_port_wait_thread_ready (VOID) break; } -#if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - - bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); -#endif - /** * DSB should be last instruction executed before WFI * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html @@ -291,15 +303,11 @@ __attribute((weak)) void * _tx_port_wait_thread_ready (VOID) /* Instruction Synchronization Barrier. */ __ISB(); -#if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE - - bsp_prv_clock_prepare_post_sleep(clock_slowed); -#endif - /* Re-enable interrupts. */ __enable_irq(); __ISB(); } +#endif return new_thread_ptr; } @@ -376,21 +384,21 @@ TX_PORT_NAKED_FUNCTION VOID PendSV_Handler (VOID) "MOV r5, r9 \n" "MOV r6, r10 \n" "MOV r7, r11 \n" - "SUBS r3, r3, #32 \n" // Allocate stack space + "SUBS r3, r3, #32 \n" // Allocate stack space "STM r3!, {r4-r7} \n" - "SUBS r3, r3, #16 \n" // Allocate stack space + "SUBS r3, r3, #16 \n" // Allocate stack space #endif #if __FPU_USED - "TST LR, #0x10 \n" // Determine if the VFP extended frame is present - "BNE _skip_vfp_save \n" // No, skip additional VFP save + "TST LR, #0x10 \n" // Determine if the VFP extended frame is present + "BNE _skip_vfp_save \n" // No, skip additional VFP save #if defined(TX_PORT_VENDOR_STACK_MONITOR_ENABLE) - "SUB r3, r3, #64 \n" // Calculate the amount of room required to save s16-s31 - "MSR PSP, r3 \n" // Update PSP to utilize the HW stack monitor - "ADD r3, r3, #64 \n" // Restore original PSP to r3 so we can continue stacking + "SUB r3, r3, #64 \n" // Calculate the amount of room required to save s16-s31 + "MSR PSP, r3 \n" // Update PSP to utilize the HW stack monitor + "ADD r3, r3, #64 \n" // Restore original PSP to r3 so we can continue stacking #endif - "VSTMDB r3!, {s16-s31} \n" // Yes, save additional VFP registers + "VSTMDB r3!, {s16-s31} \n" // Yes, save additional VFP registers "_skip_vfp_save: \n" - "STMDB r3!, {LR} \n" // Save LR on the stack + "STMDB r3!, {LR} \n" // Save LR on the stack #endif // [r1, #TX_PORT_OFFSET_STACK_PTR] == _tx_thread_current_ptr->tx_thread_stack_ptr @@ -766,7 +774,6 @@ void _tx_port_svc_handler (UINT * caller_stack_ptr) } } - /**************************************************************************/ /* */ /* FUNCTION RELEASE */