From 60940c2e5d12a167fe808b1b2779663be72a5945 Mon Sep 17 00:00:00 2001 From: Flex Software Development Robot Date: Fri, 27 Oct 2023 16:11:43 +0000 Subject: [PATCH] Release v5.0.0 --- README.md | 8 +- SUPPORTED_SOFTWARE.md | 27 +- .../mbedtls_bio_freertos_cellular.c | 97 - ra/board/ra2e3_fpb/board.h | 61 + ra/board/ra2e3_fpb/board_init.c | 62 + ra/board/ra2e3_fpb/board_init.h | 58 + ra/board/ra2e3_fpb/board_leds.c | 70 + ra/board/ra2e3_fpb/board_leds.h | 74 + ra/board/ra6m2_ek/board_ethernet_phy.h | 1 - ra/board/ra6m3_ek/board_ethernet_phy.h | 2 +- ra/board/ra6m3g_ek/board_ethernet_phy.h | 1 - ra/board/ra6m4_ek/board_ethernet_phy.h | 1 - ra/board/ra6m5_ck/board_ethernet_phy.h | 1 - ra/board/ra6m5_ck_v2/board.h | 62 + ra/board/ra6m5_ck_v2/board_ethernet_phy.h | 61 + ra/board/ra6m5_ck_v2/board_init.c | 62 + ra/board/ra6m5_ck_v2/board_init.h | 58 + ra/board/ra6m5_ck_v2/board_leds.c | 74 + ra/board/ra6m5_ck_v2/board_leds.h | 78 + ra/board/ra6m5_ek/board_ethernet_phy.h | 1 - ra/board/ra8m1_ek/board.h | 62 + ra/board/ra8m1_ek/board_ethernet_phy.h | 61 + ra/board/ra8m1_ek/board_init.c | 62 + ra/board/ra8m1_ek/board_init.h | 58 + ra/board/ra8m1_ek/board_leds.c | 71 + ra/board/ra8m1_ek/board_leds.h | 75 + ra/fsp/inc/api/bsp_api.h | 34 +- ra/fsp/inc/api/r_adc_api.h | 76 +- ra/fsp/inc/api/r_ble_api.h | 6551 +++- ra/fsp/inc/api/r_cac_api.h | 19 +- ra/fsp/inc/api/r_can_api.h | 32 +- ra/fsp/inc/api/r_capture_api.h | 158 + ra/fsp/inc/api/r_cec_api.h | 16 - ra/fsp/inc/api/r_cgc_api.h | 80 +- ra/fsp/inc/api/r_comparator_api.h | 21 - ra/fsp/inc/api/r_crc_api.h | 75 +- ra/fsp/inc/api/r_ctsu_api.h | 26 +- ra/fsp/inc/api/r_dac_api.h | 21 - ra/fsp/inc/api/r_display_api.h | 109 +- ra/fsp/inc/api/r_doc_api.h | 20 +- ra/fsp/inc/api/r_elc_api.h | 24 +- ra/fsp/inc/api/r_ether_api.h | 76 +- ra/fsp/inc/api/r_ether_phy_api.h | 104 +- ra/fsp/inc/api/r_external_irq_api.h | 61 +- ra/fsp/inc/api/r_flash_api.h | 60 +- ra/fsp/inc/api/r_i2c_master_api.h | 69 +- ra/fsp/inc/api/r_i2c_slave_api.h | 33 +- ra/fsp/inc/api/r_i2s_api.h | 44 +- ra/fsp/inc/api/r_i3c_api.h | 32 +- ra/fsp/inc/api/r_iir_api.h | 14 - ra/fsp/inc/api/r_ioport_api.h | 246 +- ra/fsp/inc/api/r_jpeg_api.h | 32 +- ra/fsp/inc/api/r_keymatrix_api.h | 12 - ra/fsp/inc/api/r_lpm_api.h | 86 +- ra/fsp/inc/api/r_lvd_api.h | 21 +- ra/fsp/inc/api/r_opamp_api.h | 16 - ra/fsp/inc/api/r_pdc_api.h | 191 - ra/fsp/inc/api/r_poeg_api.h | 34 +- ra/fsp/inc/api/r_ptp_api.h | 32 - ra/fsp/inc/api/r_rsip_key_injection_api.h | 480 + ra/fsp/inc/api/r_rtc_api.h | 57 +- ra/fsp/inc/api/r_sce_key_injection_api.h | 68 - ra/fsp/inc/api/r_sdmmc_api.h | 34 +- ra/fsp/inc/api/r_slcdc_api.h | 18 - ra/fsp/inc/api/r_smci_api.h | 24 +- ra/fsp/inc/api/r_spi_api.h | 88 +- ra/fsp/inc/api/r_spi_flash_api.h | 40 +- ra/fsp/inc/api/r_three_phase_api.h | 20 +- ra/fsp/inc/api/r_timer_api.h | 67 +- ra/fsp/inc/api/r_transfer_api.h | 79 +- ra/fsp/inc/api/r_uart_api.h | 44 +- ra/fsp/inc/api/r_usb_basic_api.h | 208 +- ra/fsp/inc/api/r_usb_hcdc_api.h | 65 +- ra/fsp/inc/api/r_usb_hhid_api.h | 16 +- ra/fsp/inc/api/r_usb_hmsc_api.h | 24 +- ra/fsp/inc/api/r_usb_pcdc_api.h | 2 - ra/fsp/inc/api/r_usb_phid_api.h | 2 - ra/fsp/inc/api/r_usb_pmsc_api.h | 2 - ra/fsp/inc/api/r_usb_pprn_api.h | 2 - ra/fsp/inc/api/r_wdt_api.h | 49 +- ra/fsp/inc/api/rm_adpcm_decoder_api.h | 12 - ra/fsp/inc/api/rm_audio_playback_api.h | 14 - ra/fsp/inc/api/rm_ble_abs_api.h | 58 +- ra/fsp/inc/api/rm_ble_mesh_access_api.h | 156 - ra/fsp/inc/api/rm_ble_mesh_api.h | 20 - ra/fsp/inc/api/rm_ble_mesh_bearer_api.h | 32 - .../inc/api/rm_ble_mesh_config_client_api.h | 12 - .../inc/api/rm_ble_mesh_health_server_api.h | 12 - ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h | 18 - ra/fsp/inc/api/rm_ble_mesh_model_client_api.h | 124 - ra/fsp/inc/api/rm_ble_mesh_model_server_api.h | 85 - ra/fsp/inc/api/rm_ble_mesh_network_api.h | 32 - ra/fsp/inc/api/rm_ble_mesh_provision_api.h | 30 - ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h | 12 +- ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h | 42 - ra/fsp/inc/api/rm_block_media_api.h | 53 - ra/fsp/inc/api/rm_comms_api.h | 23 +- ra/fsp/inc/api/rm_filex_block_media_api.h | 6 - ra/fsp/inc/api/rm_freertos_plus_fat_api.h | 14 - ra/fsp/inc/api/rm_fsxxxx_api.h | 12 - ra/fsp/inc/api/rm_hs300x_api.h | 22 - ra/fsp/inc/api/rm_hs400x_api.h | 16 - ra/fsp/inc/api/rm_littlefs_api.h | 8 - ra/fsp/inc/api/rm_mesh_bearer_platform_api.h | 18 - ra/fsp/inc/api/rm_motor_120_control_api.h | 45 - ra/fsp/inc/api/rm_motor_120_driver_api.h | 26 - ra/fsp/inc/api/rm_motor_angle_api.h | 78 - ra/fsp/inc/api/rm_motor_api.h | 79 - ra/fsp/inc/api/rm_motor_current_api.h | 28 - ra/fsp/inc/api/rm_motor_driver_api.h | 20 - .../inc/api/rm_motor_inertia_estimate_api.h | 24 - ra/fsp/inc/api/rm_motor_position_api.h | 32 - ra/fsp/inc/api/rm_motor_return_origin_api.h | 22 - ra/fsp/inc/api/rm_motor_speed_api.h | 24 - ra/fsp/inc/api/rm_ob1203_api.h | 34 - ra/fsp/inc/api/rm_rai_data_collector_api.h | 28 +- ra/fsp/inc/api/rm_rai_data_shipper_api.h | 17 +- ra/fsp/inc/api/rm_touch_api.h | 26 +- ra/fsp/inc/api/rm_vee_api.h | 26 +- ra/fsp/inc/api/rm_zmod4xxx_api.h | 111 +- ra/fsp/inc/fsp_version.h | 8 +- ra/fsp/inc/instances/r_adc_b.h | 2 +- ra/fsp/inc/instances/r_agt.h | 1 + ra/fsp/inc/instances/r_cac.h | 2 +- ra/fsp/inc/instances/r_ceu.h | 182 + ra/fsp/inc/instances/r_cgc.h | 21 + ra/fsp/inc/instances/r_dmac.h | 4 + ra/fsp/inc/instances/r_dtc.h | 4 + ra/fsp/inc/instances/r_ether_phy.h | 29 +- ra/fsp/inc/instances/r_glcdc.h | 9 +- ra/fsp/inc/instances/r_gpt.h | 12 +- ra/fsp/inc/instances/r_iic_b_slave.h | 4 + ra/fsp/inc/instances/r_iic_slave.h | 4 + ra/fsp/inc/instances/r_ioport.h | 173 +- ra/fsp/inc/instances/r_ospi.h | 1 + ra/fsp/inc/instances/r_ospi_b.h | 249 + ra/fsp/inc/instances/r_pdc.h | 92 +- ra/fsp/inc/instances/r_rsip_key_injection.h | 172 + ra/fsp/inc/instances/r_sdadc_b.h | 244 + ra/fsp/inc/instances/r_usb_hcdc.h | 63 + .../inc/instances/rm_at_transport_da16xxx.h | 204 + .../instances/rm_at_transport_da16xxx_uart.h | 97 + .../instances/rm_mesh_generic_battery_clt.h | 3 - .../inc/instances/rm_mesh_generic_dtt_clt.h | 4 - .../inc/instances/rm_mesh_generic_level_clt.h | 4 - .../inc/instances/rm_mesh_generic_loc_clt.h | 4 - .../instances/rm_mesh_generic_on_off_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h | 4 - .../inc/instances/rm_mesh_generic_poo_clt.h | 4 - .../inc/instances/rm_mesh_generic_prop_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_health_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_light_lc_clt.h | 4 - .../instances/rm_mesh_light_lightness_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_scene_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_scheduler_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_sensor_clt.h | 4 - ra/fsp/inc/instances/rm_mesh_time_clt.h | 4 - ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h | 3 + ra/fsp/inc/instances/rm_wifi_da16xxx.h | 258 + ra/fsp/inc/instances/rm_wifi_onchip_da16xxx.h | 290 - ra/fsp/inc/instances/rm_wifi_onchip_silex.h | 1 + .../cmsis/Device/RENESAS/Include/R7FA2A1AB.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA2E1A9.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA2E2A7.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA2E307.h | 15532 ++++++++ .../cmsis/Device/RENESAS/Include/R7FA2L1AB.h | 1400 +- .../cmsis/Device/RENESAS/Include/R7FA4E10D.h | 13070 +++--- .../cmsis/Device/RENESAS/Include/R7FA4E2B9.h | 1546 +- .../cmsis/Device/RENESAS/Include/R7FA4M1AB.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA4M2AD.h | 5250 +-- .../cmsis/Device/RENESAS/Include/R7FA4M3AF.h | 5250 +-- .../cmsis/Device/RENESAS/Include/R7FA4T1BB.h | 13880 +++---- .../cmsis/Device/RENESAS/Include/R7FA4W1AD.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA6E10F.h | 5800 +-- .../cmsis/Device/RENESAS/Include/R7FA6E2BB.h | 1546 +- .../cmsis/Device/RENESAS/Include/R7FA6M1AD.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA6M2AF.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA6M3AH.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA6M4AF.h | 5236 +-- .../cmsis/Device/RENESAS/Include/R7FA6M5BH.h | 17156 ++++---- .../cmsis/Device/RENESAS/Include/R7FA6T1AD.h | 1152 +- .../cmsis/Device/RENESAS/Include/R7FA6T2BD.h | 5828 +-- .../cmsis/Device/RENESAS/Include/R7FA6T3BB.h | 5844 +-- .../cmsis/Device/RENESAS/Include/R7FA8M1AH.h | 32676 ++++++++++++++++ .../cmsis/Device/RENESAS/Include/renesas.h | 17 +- .../bsp/cmsis/Device/RENESAS/Source/system.c | 193 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.c | 404 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.h | 13 + ra/fsp/src/bsp/mcu/all/bsp_common.c | 127 + ra/fsp/src/bsp/mcu/all/bsp_common.h | 123 +- ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h | 2 +- ra/fsp/src/bsp/mcu/all/bsp_delay.c | 7 +- ...{bsp_arm_exceptions.h => bsp_exceptions.h} | 4 +- ra/fsp/src/bsp/mcu/all/bsp_group_irq.c | 12 +- ra/fsp/src/bsp/mcu/all/bsp_guard.c | 2 +- ra/fsp/src/bsp/mcu/all/bsp_io.h | 4 +- ra/fsp/src/bsp/mcu/all/bsp_irq.c | 20 +- ra/fsp/src/bsp/mcu/all/bsp_irq.h | 2 +- ra/fsp/src/bsp/mcu/all/bsp_module_stop.h | 46 +- .../src/bsp/mcu/all/bsp_register_protection.c | 20 +- ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c | 23 +- ra/fsp/src/bsp/mcu/all/bsp_security.c | 260 +- ra/fsp/src/bsp/mcu/all/bsp_tfu.h | 84 +- ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h | 14 +- ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h | 14 +- ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h | 173 + ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h | 448 + ra/fsp/src/bsp/mcu/ra2e3/bsp_icu.h | 162 + ra/fsp/src/bsp/mcu/ra2e3/bsp_mcu_info.h | 59 + ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h | 13 +- ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h | 13 +- ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h | 12 +- ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h | 365 + ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h | 451 + ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h | 58 + ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h | 97 + ra/fsp/src/r_acmphs/r_acmphs.c | 3 +- ra/fsp/src/r_agt/r_agt.c | 5 +- ra/fsp/src/r_ble/r_ble.c | 336 + ra/fsp/src/r_cac/r_cac.c | 2 +- ...ers##all##{module_variant}####4.6.0.xml.j2 | 838 - ...#all##{module_variant}####4.6.0.xml.j2.yml | 2 - .../.module_descriptions/bit_timing.js.j2 | 171 - .../ram_usage_constraint.js.j2 | 15 - .../ram_usage_export.js.j2 | 10 - ra/fsp/src/r_canfd/r_canfd.c | 36 +- ra/fsp/src/r_ceu/r_ceu.c | 496 + ra/fsp/src/r_cgc/r_cgc.c | 330 +- ra/fsp/src/r_ctsu/r_ctsu.c | 13 +- ra/fsp/src/r_dmac/r_dmac.c | 19 + ra/fsp/src/r_dtc/r_dtc.c | 56 +- ra/fsp/src/r_elc/r_elc.c | 44 +- ra/fsp/src/r_ether/r_ether.c | 16 +- ra/fsp/src/r_ether_phy/r_ether_phy.c | 233 +- .../DP83620/r_ether_phy_target_dp83620.c | 10 +- .../ICS1894/r_ether_phy_target_ics1894.c | 6 +- .../KSZ8041/r_ether_phy_target_ksz8041.c | 15 +- .../r_ether_phy_target_ksz8091rnb.c | 18 +- ra/fsp/src/r_flash_hp/r_flash_hp.c | 33 +- ra/fsp/src/r_flash_lp/r_flash_lp.c | 103 +- ra/fsp/src/r_glcdc/r_glcdc.c | 141 +- ra/fsp/src/r_icu/r_icu.c | 2 +- ra/fsp/src/r_iic_b_master/r_iic_b_master.c | 2 - ra/fsp/src/r_iic_b_slave/r_iic_b_slave.c | 326 +- ra/fsp/src/r_iic_master/r_iic_master.c | 9 +- ra/fsp/src/r_iic_slave/r_iic_slave.c | 290 +- ra/fsp/src/r_ioport/r_ioport.c | 57 +- ra/fsp/src/r_lpm/r_lpm.c | 46 +- ra/fsp/src/r_lvd/r_lvd.c | 28 +- ra/fsp/src/r_ospi/r_ospi.c | 41 +- ra/fsp/src/r_ospi_b/r_ospi_b.c | 1310 + ra/fsp/src/r_pdc/r_pdc.c | 229 +- ra/fsp/src/r_ptp/r_ptp.c | 58 +- ra/fsp/src/r_qspi/r_qspi.c | 20 +- .../r_rsip_key_injection.c | 1289 + ra/fsp/src/r_rtc/r_rtc.c | 4 +- ra/fsp/src/r_sce/common/hw_sce_common.h | 1 + .../src/rsip7/plainkey/adaptors/r_sce_adapt.c | 226 +- .../rsip7/plainkey/primitive/DomainParams.c | 577 + .../plainkey/primitive/hw_sce_p_func012.c | 318 + .../plainkey/primitive/hw_sce_p_func013.c | 299 + .../plainkey/primitive/hw_sce_p_func016.c | 98 + .../plainkey/primitive/hw_sce_p_func017.c | 92 + .../plainkey/primitive/hw_sce_p_func052.c | 998 + .../plainkey/primitive/hw_sce_p_func053.c | 301 + .../plainkey/primitive/hw_sce_p_func054.c | 998 + .../plainkey/primitive/hw_sce_p_func055.c | 301 + .../plainkey/primitive/hw_sce_p_func302.c | 139 + .../plainkey/primitive/hw_sce_p_func303.c | 139 + .../plainkey/primitive/hw_sce_p_func304.c | 139 + .../plainkey/primitive/hw_sce_p_func305.c | 139 + .../plainkey/primitive/hw_sce_p_func401.c | 62 + .../plainkey/primitive/hw_sce_p_func402.c | 92 + .../plainkey/primitive/hw_sce_p_func403.c | 204 + .../plainkey/primitive/hw_sce_p_func404.c | 231 + .../plainkey/primitive/hw_sce_p_func405.c | 37 + .../plainkey/primitive/hw_sce_p_func406.c | 117 + .../rsip7/plainkey/primitive/hw_sce_p_p11.c | 26 +- .../rsip7/plainkey/primitive/hw_sce_p_p13.c | 4 +- .../rsip7/plainkey/primitive/hw_sce_p_p18.c | 982 + .../rsip7/plainkey/primitive/hw_sce_p_p19.c | 1379 + .../rsip7/plainkey/primitive/hw_sce_p_p1b.c | 328 + .../rsip7/plainkey/primitive/hw_sce_p_p2b.c | 1696 + .../rsip7/plainkey/primitive/hw_sce_p_p2c.c | 173 + .../rsip7/plainkey/primitive/hw_sce_p_p2d.c | 168 + .../rsip7/plainkey/primitive/hw_sce_p_p2e.c | 144 + .../rsip7/plainkey/primitive/hw_sce_p_p31.c | 241 + .../rsip7/plainkey/primitive/hw_sce_p_p74.c | 391 + .../rsip7/plainkey/primitive/hw_sce_p_p75.c | 388 + .../rsip7/plainkey/primitive/hw_sce_p_p7d.c | 16 +- .../rsip7/plainkey/primitive/hw_sce_p_pf6.c | 10 +- .../plainkey/private/inc/hw_sce_ra_private.h | 331 +- .../src/rsip7/plainkey/public/inc/r_sce_if.h | 466 +- .../src/sce5/plainkey/adaptors/r_sce_adapt.c | 26 +- .../src/sce5/plainkey/primitive/hw_sce_p71.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p72.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p74.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p75.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p77.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p78.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p80.c | 2 +- .../src/sce5/plainkey/primitive/hw_sce_p81.c | 2 +- .../plainkey/private/inc/hw_sce_ra_private.h | 42 +- .../src/sce5b/plainkey/adaptors/r_sce_adapt.c | 28 +- .../sce5b/plainkey/primitive/hw_sce_p95f.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_p95u.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_p98f.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_p98u.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_pa1f.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_pa1u.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_pa4f.c | 2 +- .../sce5b/plainkey/primitive/hw_sce_pa4u.c | 2 +- .../plainkey/private/inc/hw_sce_ra_private.h | 48 +- .../src/sce7/plainkey/adaptors/r_sce_adapt.c | 115 +- .../sce7/plainkey/primitive/hw_sce_p_p95f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_p95u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_p98f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_p98u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa1f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa1u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa4f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa4u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa7f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pa7u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pb0f.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pb0u.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pf5.c | 2 +- .../sce7/plainkey/primitive/hw_sce_p_pf6.c | 2 +- .../plainkey/private/inc/hw_sce_ra_private.h | 70 +- .../src/sce9/plainkey/adaptors/r_sce_adapt.c | 108 +- .../sce9/plainkey/primitive/hw_sce_p_p95f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_p95u.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_p98f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_p98u.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa1f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa1u.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa4f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa4u.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa7f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pa7u.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pb0f.c | 2 +- .../sce9/plainkey/primitive/hw_sce_p_pb0u.c | 2 +- .../plainkey/private/inc/hw_sce_ra_private.h | 69 +- ra/fsp/src/r_sce/hw_sce_aes_private.h | 9 +- ra/fsp/src/r_sce/hw_sce_ecc_private.h | 10 +- ra/fsp/src/r_sce/hw_sce_hash_private.h | 20 + ra/fsp/src/r_sci_b_i2c/r_sci_b_i2c.c | 3 +- ra/fsp/src/r_sdadc_b/r_sdadc_b.c | 912 + ra/fsp/src/r_slcdc/r_slcdc.c | 4 +- ra/fsp/src/r_usb_basic/r_usb_basic.c | 18 +- .../r_usb_basic/src/driver/r_usb_cstd_rtos.c | 2 +- .../r_usb_basic/src/driver/r_usb_hmanager.c | 34 + .../src/driver/r_usb_hstdfunction.c | 2 +- .../src/driver/r_usb_pstdrequest.c | 2 +- ra/fsp/src/r_usb_hcdc/r_usb_hcdc.c | 246 + .../inc/{r_usb_hcdc.h => r_usb_hcdc_driver.h} | 7 +- ra/fsp/src/r_usb_hcdc/src/r_usb_hcdc_driver.c | 46 +- ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc.h | 6 +- .../rm_at_transport_da16xxx_uart.c | 1091 + ...ockets_wrapper.c => tcp_sockets_wrapper.c} | 110 +- .../tcp_sockets_wrapper.h} | 51 +- ...ockets_wrapper.c => tcp_sockets_wrapper.c} | 74 +- .../tcp_sockets_wrapper.h} | 51 +- .../rm_block_media_ram/rm_block_media_ram.c | 4 + ra/fsp/src/rm_emwin_port/GUI_X_OS.c | 8 + .../rm_freertos_plus_tcp/NetworkInterface.c | 169 +- .../rm_freertos_plus_tcp/pack_struct_end.h | 9 +- .../rm_freertos_plus_tcp/pack_struct_start.h | 9 +- ra/fsp/src/rm_freertos_port/port.c | 51 +- ra/fsp/src/rm_freertos_port/portmacro.h | 4 +- ra/fsp/src/rm_mcuboot_port/flash_map.c | 12 + .../flash_map_backend/flash_map_backend.h | 2 + ra/fsp/src/rm_mcuboot_port/rm_mcuboot_port.c | 2 +- .../rm_motor_120_driver/rm_motor_120_driver.c | 32 +- .../rm_mqtt_onchip_da16xxx.c | 333 +- .../rm_netx_secure_crypto/nx_crypto_aes_alt.c | 12 +- .../nx_crypto_aes_alt_process.c | 4 +- .../nx_crypto_cbc_alt_process.c | 320 +- .../rm_netx_secure_crypto/nx_crypto_ccm_alt.c | 8 +- .../nx_crypto_ccm_alt_process.c | 46 +- .../nx_crypto_ctr_alt_process.c | 2 +- .../nx_crypto_ecdh_alt_process.c | 13 +- .../nx_crypto_ecdsa_alt_process.c | 18 +- .../rm_netx_secure_crypto/nx_crypto_gcm_alt.c | 12 +- .../nx_crypto_gcm_alt_process.c | 13 +- .../rm_netx_secure_crypto.c | 9 +- ra/fsp/src/rm_psa_crypto/ccm_alt_process.c | 2 +- ra/fsp/src/rm_psa_crypto/cipher_alt.c | 6 +- ra/fsp/src/rm_psa_crypto/ecdsa_alt.c | 133 +- ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c | 98 +- ra/fsp/src/rm_psa_crypto/ecp_alt.c | 2 +- ra/fsp/src/rm_psa_crypto/ecp_alt_process.c | 52 +- ra/fsp/src/rm_psa_crypto/gcm_alt_process.c | 80 +- ra/fsp/src/rm_psa_crypto/inc/sha256_alt.h | 19 +- ra/fsp/src/rm_psa_crypto/platform_alt.c | 5 +- ra/fsp/src/rm_psa_crypto/rsa_alt_process.c | 30 +- ra/fsp/src/rm_psa_crypto/sha256_alt.c | 165 +- ra/fsp/src/rm_psa_crypto/sha256_alt_process.c | 121 +- .../ra/CMSIS_Driver/Driver_Flash.c | 11 +- .../ra/Device/Include/platform_irq.h | 2 +- ra/fsp/src/rm_tfm_port/ra/boot_hal_bl2.c | 52 - .../rm_tfm_port/ra/partition/flash_layout.h | 30 +- .../rm_tfm_port/ra/partition/region_defs.h | 10 - ra/fsp/src/rm_tfm_port/ra/provisioning.c | 53 +- ra/fsp/src/rm_tfm_port/ra/tfm_hal_isolation.c | 4 +- ra/fsp/src/rm_threadx_port/tx_cmsis.h | 14 +- .../rm_threadx_port/tx_initialize_low_level.c | 2 +- ra/fsp/src/rm_threadx_port/tx_port_vendor.h | 2 +- .../tx_port_wait_thread_ready.c | 8 + .../src/rm_threadx_port/tx_thread_schedule.c | 12 +- ra/fsp/src/rm_usbx_port/fx_port.h | 211 - ra/fsp/src/rm_usbx_port/rm_usbx_port.c | 26 +- ra/fsp/src/rm_vee_flash/rm_vee_flash.c | 5 +- .../rm_wifi_api_da16xxx.c | 32 +- ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c | 2140 + .../rm_wifi_onchip_da16xxx.c | 3196 -- .../rm_wifi_onchip_silex.c | 190 +- .../src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h | 14 +- .../iaq_2nd_gen/zmod4410_config_iaq2.h | 2 +- .../iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h | 2 +- .../zmod4410_config_iaq2_ulp.h | 2 +- ra/fsp/src/rm_zmod4xxx/rel_iaq/rel_iaq.h | 2 +- .../rel_iaq/zmod4410_config_rel_iaq.h | 2 +- .../src/rm_zmod4xxx/rel_iaq_ulp/rel_iaq_ulp.h | 2 +- .../rel_iaq_ulp/zmod4410_config_rel_iaq_ulp.h | 2 +- 444 files changed, 136541 insertions(+), 52022 deletions(-) delete mode 100644 ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c create mode 100644 ra/board/ra2e3_fpb/board.h create mode 100644 ra/board/ra2e3_fpb/board_init.c create mode 100644 ra/board/ra2e3_fpb/board_init.h create mode 100644 ra/board/ra2e3_fpb/board_leds.c create mode 100644 ra/board/ra2e3_fpb/board_leds.h create mode 100644 ra/board/ra6m5_ck_v2/board.h create mode 100644 ra/board/ra6m5_ck_v2/board_ethernet_phy.h create mode 100644 ra/board/ra6m5_ck_v2/board_init.c create mode 100644 ra/board/ra6m5_ck_v2/board_init.h create mode 100644 ra/board/ra6m5_ck_v2/board_leds.c create mode 100644 ra/board/ra6m5_ck_v2/board_leds.h create mode 100644 ra/board/ra8m1_ek/board.h create mode 100644 ra/board/ra8m1_ek/board_ethernet_phy.h create mode 100644 ra/board/ra8m1_ek/board_init.c create mode 100644 ra/board/ra8m1_ek/board_init.h create mode 100644 ra/board/ra8m1_ek/board_leds.c create mode 100644 ra/board/ra8m1_ek/board_leds.h create mode 100644 ra/fsp/inc/api/r_capture_api.h delete mode 100644 ra/fsp/inc/api/r_pdc_api.h create mode 100644 ra/fsp/inc/api/r_rsip_key_injection_api.h create mode 100644 ra/fsp/inc/instances/r_ceu.h create mode 100644 ra/fsp/inc/instances/r_ospi_b.h create mode 100644 ra/fsp/inc/instances/r_rsip_key_injection.h create mode 100644 ra/fsp/inc/instances/r_sdadc_b.h create mode 100644 ra/fsp/inc/instances/r_usb_hcdc.h create mode 100644 ra/fsp/inc/instances/rm_at_transport_da16xxx.h create mode 100644 ra/fsp/inc/instances/rm_at_transport_da16xxx_uart.h create mode 100644 ra/fsp/inc/instances/rm_wifi_da16xxx.h delete mode 100644 ra/fsp/inc/instances/rm_wifi_onchip_da16xxx.h create mode 100644 ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h create mode 100644 ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h rename ra/fsp/src/bsp/mcu/all/{bsp_arm_exceptions.h => bsp_exceptions.h} (98%) create mode 100644 ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h create mode 100644 ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h create mode 100644 ra/fsp/src/bsp/mcu/ra2e3/bsp_icu.h create mode 100644 ra/fsp/src/bsp/mcu/ra2e3/bsp_mcu_info.h create mode 100644 ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h create mode 100644 ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h create mode 100644 ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h create mode 100644 ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h delete mode 100644 ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 delete mode 100644 ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2.yml delete mode 100644 ra/fsp/src/r_canfd/.module_descriptions/bit_timing.js.j2 delete mode 100644 ra/fsp/src/r_canfd/.module_descriptions/ram_usage_constraint.js.j2 delete mode 100644 ra/fsp/src/r_canfd/.module_descriptions/ram_usage_export.js.j2 create mode 100644 ra/fsp/src/r_ceu/r_ceu.c create mode 100644 ra/fsp/src/r_ospi_b/r_ospi_b.c create mode 100644 ra/fsp/src/r_rsip_key_injection/r_rsip_key_injection.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/DomainParams.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func012.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func013.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func016.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func017.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func052.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func053.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func054.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func055.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func302.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func303.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func304.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func305.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func401.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func402.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func403.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func404.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func405.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func406.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p18.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p19.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p1b.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p2b.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p2c.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p2d.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p2e.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p31.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p74.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p75.c create mode 100644 ra/fsp/src/r_sdadc_b/r_sdadc_b.c create mode 100644 ra/fsp/src/r_usb_hcdc/r_usb_hcdc.c rename ra/fsp/src/r_usb_hcdc/src/inc/{r_usb_hcdc.h => r_usb_hcdc_driver.h} (93%) create mode 100644 ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c rename ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16xxx/{sockets_wrapper.c => tcp_sockets_wrapper.c} (75%) rename ra/fsp/src/{rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.h => rm_aws_sockets_wrapper_wifi_da16xxx/tcp_sockets_wrapper.h} (66%) rename ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/{sockets_wrapper.c => tcp_sockets_wrapper.c} (85%) rename ra/fsp/src/{rm_aws_sockets_wrapper_wifi_da16xxx/sockets_wrapper.h => rm_aws_sockets_wrapper_wifi_silex/tcp_sockets_wrapper.h} (66%) delete mode 100644 ra/fsp/src/rm_usbx_port/fx_port.h rename ra/fsp/src/{rm_wifi_onchip_da16xxx => rm_wifi_da16xxx}/rm_wifi_api_da16xxx.c (90%) create mode 100644 ra/fsp/src/rm_wifi_da16xxx/rm_wifi_da16xxx.c delete mode 100644 ra/fsp/src/rm_wifi_onchip_da16xxx/rm_wifi_onchip_da16xxx.c diff --git a/README.md b/README.md index fcc2a0803..58d3af45a 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v4.6.0](https://github.com/renesas/fsp/releases/tag/v4.6.0) +[FSP v5.0.0](https://github.com/renesas/fsp/releases/tag/v5.0.0) ### Supported RA MCU Kits @@ -42,6 +42,9 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe - EK-RA6E2 - MCK-RA4T1 - MCK-RA6T3 +- EK-RA8M1 +- FPB-RA2E3 +- CK-RA6M5 V2 ### Supported Software Packaged with FSP @@ -74,6 +77,7 @@ For a list of software modules packaged with FSP, see [Supported Software](SUPPO - FSP versions of 4.3.0 and later require a minimum e² studio version of 2023-01. - FSP versions of 4.4.0 and later require a minimum e² studio version of 2023-04. - FSP versions of 4.6.0 and later require a minimum e² studio version of 2023-07. +- FSP versions of 5.0.0 and later require a minimum e² studio version of 2023-10. If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\.exe, that will work on Windows. @@ -81,7 +85,7 @@ When using the zipped version of the packs the zip file should be extracted into #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.6.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.0.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index a46bac744..e2e281b94 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -4,6 +4,7 @@ * Analog * [ADC (r_adc)](https://renesas.github.io/fsp/group___a_d_c.html) * [ADC (r_sdadc)](https://renesas.github.io/fsp/group___s_d_a_d_c.html) + * [ADC (r_sdadc_b)](https://renesas.github.io/fsp/group___s_d_a_d_c___b.html) * [ADC Driver on r_adc_b](https://renesas.github.io/fsp/group___a_d_c___b.html) * [ADC-DMAC Integration (r_adc)](https://renesas.github.io/fsp/group___a_d_c.html) * [Comparator, High-Speed (r_acmphs)](https://renesas.github.io/fsp/group___a_c_m_p_h_s.html) @@ -42,12 +43,12 @@ * [CAN FD Lite (r_canfdlite)](https://renesas.github.io/fsp/group___c_a_n_f_d.html) * [CEC (r_cec)](https://renesas.github.io/fsp/group___c_e_c.html) * [I2C Communication Device (rm_comms_i2c)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___i2_c.html) - * [I2C Master (r_iic_b_master)](https://renesas.github.io/fsp/group___i_i_c___m_a_s_t_e_r.html) + * [I2C Master (r_iic_b_master)](https://renesas.github.io/fsp/group___i_i_c___b___m_a_s_t_e_r.html) * [I2C Master (r_iic_master)](https://renesas.github.io/fsp/group___i_i_c___m_a_s_t_e_r.html) * [I2C Master (r_sci_b_i2c)](https://renesas.github.io/fsp/group___s_c_i___b___i2_c.html) * [I2C Master (r_sci_i2c)](https://renesas.github.io/fsp/group___s_c_i___i2_c.html) * [I2C Shared Bus (rm_comms_i2c)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___i2_c.html) - * [I2C Slave (r_iic_b_slave)](https://renesas.github.io/fsp/group___i_i_c___s_l_a_v_e.html) + * [I2C Slave (r_iic_b_slave)](https://renesas.github.io/fsp/group___i_i_c___b___s_l_a_v_e.html) * [I2C Slave (r_iic_slave)](https://renesas.github.io/fsp/group___i_i_c___s_l_a_v_e.html) * [I2S (r_ssi)](https://renesas.github.io/fsp/group___s_s_i.html) * [I3C (r_i3c)](https://renesas.github.io/fsp/group___i3_c.html) @@ -74,6 +75,7 @@ * [IIR Filter Accelerator (r_iirfa)](https://renesas.github.io/fsp/group___i_i_r_f_a.html) * Graphics * [Azure RTOS GUIX](https://docs.microsoft.com/en-us/azure/rtos/guix/) + * [Capture Engine Unit (r_ceu)](https://renesas.github.io/fsp/group___c_e_u.html) * [D/AVE 2D (r_drw)](https://www.tes-dst.com/technology-products/gpus/d/ave-2d/) * [D/AVE 2D Port Interface (r_drw)](https://renesas.github.io/fsp/group___d_r_w.html) * [Graphics LCD (r_glcdc)](https://renesas.github.io/fsp/group___g_l_c_d_c.html) @@ -89,7 +91,7 @@ * [Clock Accuracy Circuit (r_cac)](https://renesas.github.io/fsp/group___c_a_c.html) * [Data Operation Circuit (r_doc)](https://renesas.github.io/fsp/group___d_o_c.html) * [Independent Watchdog (r_iwdt)](https://renesas.github.io/fsp/group___i_w_d_t.html) - * [Low Voltage Detection (r_lvd)](https://renesas.github.io/fsp/group___l_v_d.html) + * [Low/Programmable Voltage Detection (r_lvd)](https://renesas.github.io/fsp/group___l_v_d.html) * [Watchdog (r_wdt)](https://renesas.github.io/fsp/group___w_d_t.html) * Motor * [120-degree conduction control sensorless (rm_motor_120_control_sensorless)](https://renesas.github.io/fsp/group___m_o_t_o_r__120___c_o_n_t_r_o_l___s_e_n_s_o_r_l_e_s_s.html) @@ -251,6 +253,7 @@ * [FreeRTOS+FAT](https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT/index.html) * [LittleFS](https://github.com/ARMmbed/littlefs) * [OSPI Flash (r_ospi)](https://renesas.github.io/fsp/group___o_s_p_i.html) + * [OSPI Flash (r_ospi_b)](https://renesas.github.io/fsp/group___o_s_p_i___b.html) * [OSPI RAM (r_ospi)](https://renesas.github.io/fsp/group___o_s_p_i.html) * [QSPI (r_qspi)](https://renesas.github.io/fsp/group___q_s_p_i.html) * [SD/MMC (r_sdhi)](https://renesas.github.io/fsp/group___s_d_h_i.html) @@ -266,6 +269,7 @@ * [Three-Phase PWM (r_gpt_three_phase)](https://renesas.github.io/fsp/group___g_p_t___t_h_r_e_e___p_h_a_s_e.html) * [Timer, General PWM (r_gpt)](https://renesas.github.io/fsp/group___g_p_t.html) * [Timer, Low-Power (r_agt)](https://renesas.github.io/fsp/group___a_g_t.html) + * [Timer, Ultra-Low-Power (r_ulpt)](https://renesas.github.io/fsp/group___u_l_p_t.html) * Transfer * [Transfer (r_dmac)](https://renesas.github.io/fsp/group___d_m_a_c.html) * [Transfer (r_dtc)](https://renesas.github.io/fsp/group___d_t_c.html) @@ -307,28 +311,17 @@ * [AWS Cellular Interface Common](https://www.freertos.org/Documentation/api-ref/cellular/index.html) * [AWS Cellular Platform (rm_cellular_platform_aws)](https://www.freertos.org/Documentation/api-ref/cellular/cellular_porting.html) * [AWS Cellular Sockets Wrapper](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [AWS Cellular/WiFi MbedTLS Bio](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [AWS Client Credentials](https://renesas.github.io/fsp/group___a_w_s___m_q_t_t.html) * [AWS Core HTTP](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS Core JSON](https://github.com/FreeRTOS/coreJSON/) * [AWS Core MQTT](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS DA16xxx WiFi Sockets Wrapper (rm_aws_sockets_wrapper_da16xxx)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [AWS Demo dev_mode_key_provisioning](https://docs.aws.amazon.com/freertos/latest/userguide/dev-mode-key-provisioning.html) - * [AWS Demo dev_mode_key_provisioning (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS FreeRTOS+TCP MbedTLS Bio](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [AWS HTTPS Wrapper (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) - * [AWS IoT Common (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS Logging](https://renesas.github.io/fsp/) - * [AWS MQTT Wrapper (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS PKCS11 PAL on LittleFS (rm_aws_pkcs11_pal_littlefs)](https://renesas.github.io/fsp/group___a_w_s___p_k_c_s11___p_a_l___l_i_t_t_l_e_f_s.html) * [AWS PKCS11 to MbedTLS](https://docs.aws.amazon.com/freertos/latest/userguide/security-pkcs.html) - * [AWS Secure Sockets Common (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) - * [AWS Secure Sockets TLS Support (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) - * [AWS Secure Sockets on FreeRTOS Plus TCP (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) - * [AWS Secure Sockets on WiFi (No Longer Supported)](https://renesas.github.io/fsp/) * [AWS Silex WiFi Sockets Wrapper (rm_aws_sockets_wrapper_silex)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [AWS TCP Sockets Wrapper](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) - * [AWS Transport Interface on Secure Sockets (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [Azure EWF Heap Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF Interface on r_uart](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF Memory Pool Allocator](https://azure.github.io/embedded-wireless-framework/html/index.html) @@ -353,14 +346,14 @@ * [BLE Mesh Timer on FreeRTOS (rm_mesh_timer_freertos)](https://renesas.github.io/fsp/group___m_e_s_h___t_i_m_e_r___f_r_e_e_r_t_o_s.html) * [Cellular Comm Interface on UART (rm_cellular_comm_uart_aws)](https://www.freertos.org/Documentation/api-ref/cellular/cellular__comm__interface_8h.html) * [DA14531 GTL Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___g_t_l.html) + * [DA16XXX Transport on UART (rm_at_transport_da16xxx_uart)](https://renesas.github.io/fsp/group___a_t__t_r_a_n_s_p_o_r_t__d_a16_x_x_x.html) * [FreeRTOS+TCP Wrapper to r_ether (rm_freertos_plus_tcp)](https://renesas.github.io/fsp/group___f_r_e_e_r_t_o_s___p_l_u_s___t_c_p.html) - * [FreeRTOS+TLS (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [NetX Duo Ethernet Driver (rm_netxduo_ether)](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter5) - * [NetX Duo WiFi Driver (rm_netxduo_wifi)](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter5) + * [NetX Duo WiFi Driver (rm_netxduo_wifi)](https://renesas.github.io/fsp/group___r_m___n_e_t_x_d_u_o___w_i_f_i.html) * [RYZ012 SPP Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___s_p_p.html) * [TinyCBOR](https://github.com/intel/tinycbor/) * [WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html) - * [WiFi Onchip DA16xxx Driver using r_sci_uart (rm_wifi_onchip_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___d_a16_x_x_x.html) + * [WiFi DA16XXX Framework Driver (rm_wifi_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___d_a16_x_x_x.html) * [WiFi Onchip Silex Driver using r_sci_uart (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) * Security * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) diff --git a/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c b/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c deleted file mode 100644 index 7fc83eed5..000000000 --- a/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * FreeRTOS V202112.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * https://www.FreeRTOS.org - * https://github.com/FreeRTOS - * - */ - -/** - * @file mbedtls_bio_freertos_cellular.c - * @brief Implements mbed TLS platform send/receive functions for cellular. - */ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" - -/* Sockets wrapper includes. */ -#include "sockets_wrapper.h" - -/* mbed TLS includes. */ -#include "threading_alt.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ssl.h" - -/*-----------------------------------------------------------*/ - -/** - * @brief Sends data over cellular sockets. - * - * @param[in] ctx The network context containing the socket handle. - * @param[in] buf Buffer containing the bytes to send. - * @param[in] len Number of bytes to send from the buffer. - * - * @return Number of bytes sent on success; else a negative value. - */ -int mbedtls_platform_send( void * ctx, - const unsigned char * buf, - size_t len ) -{ - configASSERT( ctx != NULL ); - configASSERT( buf != NULL ); - - return Sockets_Send( ( Socket_t ) ctx, buf, len ); -} - -/*-----------------------------------------------------------*/ - -/** - * @brief Receives data from cellular socket. - * - * @param[in] ctx The network context containing the socket handle. - * @param[out] buf Buffer to receive bytes into. - * @param[in] len Number of bytes to receive from the network. - * - * @return Number of bytes received if successful; Negative value on error. - */ -int mbedtls_platform_recv( void * ctx, - unsigned char * buf, - size_t len ) -{ - int recvStatus = 0; - int returnStatus = -1; - - configASSERT( ctx != NULL ); - configASSERT( buf != NULL ); - - recvStatus = Sockets_Recv( ( Socket_t ) ctx, buf, len ); - - if( recvStatus < 0 ) - { - returnStatus = MBEDTLS_ERR_SSL_INTERNAL_ERROR; - } - else - { - returnStatus = recvStatus; - } - - return returnStatus; -} diff --git a/ra/board/ra2e3_fpb/board.h b/ra/board/ra2e3_fpb/board.h new file mode 100644 index 000000000..2d499dff5 --- /dev/null +++ b/ra/board/ra2e3_fpb/board.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA2E3_FPB for the FPB-RA2E3 board + * @brief BSP for the FPB-RA2E3 Board + * + * The FPB-RA2E3 is a development kit for the Renesas R7FA2E3073CFL microcontroller in a LQFP48 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA2E3_FPB + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA2E3_FPB) */ + +#endif diff --git a/ra/board/ra2e3_fpb/board_init.c b/ra/board/ra2e3_fpb/board_init.c new file mode 100644 index 000000000..ea00ef2b0 --- /dev/null +++ b/ra/board/ra2e3_fpb/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2E3_FPB + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA2E3_FPB) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA2E3_FPB) */ diff --git a/ra/board/ra2e3_fpb/board_init.h b/ra/board/ra2e3_fpb/board_init.h new file mode 100644 index 000000000..353181b34 --- /dev/null +++ b/ra/board/ra2e3_fpb/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2E3_FPB + * @brief Board specific code for the FPB-RA2E3 Board + * + * This include file is specific to the FPB-RA2E3 board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA2E3_FPB) */ diff --git a/ra/board/ra2e3_fpb/board_leds.c b/ra/board/ra2e3_fpb/board_leds.c new file mode 100644 index 000000000..9877087fe --- /dev/null +++ b/ra/board/ra2e3_fpb/board_leds.c @@ -0,0 +1,70 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA2E3_FPB_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA2E3_FPB) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_02_PIN_13, ///< LED1 + (uint16_t) BSP_IO_PORT_09_PIN_14, ///< LED2 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA2E3_FPB_LEDS) */ diff --git a/ra/board/ra2e3_fpb/board_leds.h b/ra/board/ra2e3_fpb/board_leds.h new file mode 100644 index 000000000..c971e693b --- /dev/null +++ b/ra/board/ra2e3_fpb/board_leds.h @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA2E3_FPB + * @defgroup BOARD_RA2E3_FPB_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the FPB board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA2E3_FPB_LEDS) */ diff --git a/ra/board/ra6m2_ek/board_ethernet_phy.h b/ra/board/ra6m2_ek/board_ethernet_phy.h index 08e0149a1..ce8e1152c 100644 --- a/ra/board/ra6m2_ek/board_ethernet_phy.h +++ b/ra/board/ra6m2_ek/board_ethernet_phy.h @@ -37,7 +37,6 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (0) // DEPRECATED #define BOARD_PHY_REF_CLK (1) /*********************************************************************************************************************** diff --git a/ra/board/ra6m3_ek/board_ethernet_phy.h b/ra/board/ra6m3_ek/board_ethernet_phy.h index 9f8400f73..03d5c0ef8 100644 --- a/ra/board/ra6m3_ek/board_ethernet_phy.h +++ b/ra/board/ra6m3_ek/board_ethernet_phy.h @@ -37,8 +37,8 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (1) // DEPRECATED #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_KSZ8091RNB #define BOARD_PHY_REF_CLK (1) /*********************************************************************************************************************** diff --git a/ra/board/ra6m3g_ek/board_ethernet_phy.h b/ra/board/ra6m3g_ek/board_ethernet_phy.h index 2be879029..0d8da24e4 100644 --- a/ra/board/ra6m3g_ek/board_ethernet_phy.h +++ b/ra/board/ra6m3g_ek/board_ethernet_phy.h @@ -37,7 +37,6 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (1) // DEPRECATED #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (1) #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_KSZ8091RNB #define BOARD_PHY_REF_CLK (1) diff --git a/ra/board/ra6m4_ek/board_ethernet_phy.h b/ra/board/ra6m4_ek/board_ethernet_phy.h index df4cac6c8..a93121071 100644 --- a/ra/board/ra6m4_ek/board_ethernet_phy.h +++ b/ra/board/ra6m4_ek/board_ethernet_phy.h @@ -37,7 +37,6 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (1) // DEPRECATED #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (1) #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_KSZ8091RNB #define BOARD_PHY_REF_CLK (1) diff --git a/ra/board/ra6m5_ck/board_ethernet_phy.h b/ra/board/ra6m5_ck/board_ethernet_phy.h index 9538e28b3..9dfe61855 100644 --- a/ra/board/ra6m5_ck/board_ethernet_phy.h +++ b/ra/board/ra6m5_ck/board_ethernet_phy.h @@ -37,7 +37,6 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (4) // DEPRECATED #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1) #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_ICS1894 #define BOARD_PHY_REF_CLK (1) diff --git a/ra/board/ra6m5_ck_v2/board.h b/ra/board/ra6m5_ck_v2/board.h new file mode 100644 index 000000000..506bc2b95 --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA6M5_2_CK for the RA6M5_2 CK board + * @brief BSP for the RA6M5_2 CK Board + * + * The RA6M5_2 CK is a development kit for the Renesas R7FA6M5BH3CFC microcontroller in a LQFP176 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA6M5_2_CK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA6M5_2_CK) */ + +#endif diff --git a/ra/board/ra6m5_ck_v2/board_ethernet_phy.h b/ra/board/ra6m5_ck_v2/board_ethernet_phy.h new file mode 100644 index 000000000..eb1d4f1a7 --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board_ethernet_phy.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6M5_2_CK + * @defgroup BOARD_RA6M5_2_CK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RA6M5_2 CK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_ICS1894 +#define BOARD_PHY_REF_CLK (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M5_2_CK_ETHERNET_PHY) */ diff --git a/ra/board/ra6m5_ck_v2/board_init.c b/ra/board/ra6m5_ck_v2/board_init.c new file mode 100644 index 000000000..d0322f92c --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_2_CK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA6M5_2_CK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA6M5_2_CK) */ diff --git a/ra/board/ra6m5_ck_v2/board_init.h b/ra/board/ra6m5_ck_v2/board_init.h new file mode 100644 index 000000000..3ae9d2659 --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_2_CK + * @brief Board specific code for the RA6M5-EK Board + * + * This include file is specific to the RA6M5-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA6M5_2_CK) */ diff --git a/ra/board/ra6m5_ck_v2/board_leds.c b/ra/board/ra6m5_ck_v2/board_leds.c new file mode 100644 index 000000000..c4b5c3b41 --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board_leds.c @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M5_2_CK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA6M5_2_CK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_06_PIN_01, ///< LED1 BLUE + (uint16_t) BSP_IO_PORT_06_PIN_09, ///< LED2 GREEN + (uint16_t) BSP_IO_PORT_06_PIN_10, ///< LED3 RED + (uint16_t) BSP_IO_PORT_06_PIN_02, ///< LED6_TRI_COLOUR_RED + (uint16_t) BSP_IO_PORT_06_PIN_03, ///< LED6_TRI_COLOUR_GREEN + (uint16_t) BSP_IO_PORT_06_PIN_05, ///< LED6_TRI_COLOUR_BLUE +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA6M5_2_CK_LEDS) */ diff --git a/ra/board/ra6m5_ck_v2/board_leds.h b/ra/board/ra6m5_ck_v2/board_leds.h new file mode 100644 index 000000000..df82e0d93 --- /dev/null +++ b/ra/board/ra6m5_ck_v2/board_leds.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6M5_2_CK + * @defgroup BOARD_RA6M5_2_CK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the CK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 RED + BSP_LED_LED2, ///< LED2 GREEN + BSP_LED_LED3, ///< LED3 BLUE + BSP_LED_LED6_RED, ///< LED6_TRI_COLOUR_RED + BSP_LED_LED6_GREEN, ///< LED6_TRI_COLOUR_GREEN + BSP_LED_LED6_BLUE, ///< LED6_TRI_COLOUR_BLUE +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M5_2_CK_LEDS) */ diff --git a/ra/board/ra6m5_ek/board_ethernet_phy.h b/ra/board/ra6m5_ek/board_ethernet_phy.h index 0dc0983ef..594a5a9a7 100644 --- a/ra/board/ra6m5_ek/board_ethernet_phy.h +++ b/ra/board/ra6m5_ek/board_ethernet_phy.h @@ -37,7 +37,6 @@ FSP_HEADER /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BOARD_PHY_TYPE (1) // DEPRECATED #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (1) #define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_KSZ8091RNB #define BOARD_PHY_REF_CLK (1) diff --git a/ra/board/ra8m1_ek/board.h b/ra/board/ra8m1_ek/board.h new file mode 100644 index 000000000..b5759fc6b --- /dev/null +++ b/ra/board/ra8m1_ek/board.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA8M1_EK for the RA8M1-EK board + * @brief BSP for the RA8M1-EK Board + * + * The RA8M1_EK is a development kit for the Renesas R7FA8M1AHDCBD microcontroller in a BGA224 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA8M1_EK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA8M1_EK) */ + +#endif diff --git a/ra/board/ra8m1_ek/board_ethernet_phy.h b/ra/board/ra8m1_ek/board_ethernet_phy.h new file mode 100644 index 000000000..7e9eec59d --- /dev/null +++ b/ra/board/ra8m1_ek/board_ethernet_phy.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA8M1_EK + * @defgroup BOARD_RA8M1_EK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RA8M1_EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_ICS1894 +#define BOARD_PHY_REF_CLK (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA8M1_EK_ETHERNET_PHY) */ diff --git a/ra/board/ra8m1_ek/board_init.c b/ra/board/ra8m1_ek/board_init.c new file mode 100644 index 000000000..addecb06b --- /dev/null +++ b/ra/board/ra8m1_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_EK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA8M1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA8M1_EK) */ diff --git a/ra/board/ra8m1_ek/board_init.h b/ra/board/ra8m1_ek/board_init.h new file mode 100644 index 000000000..0e8f647e4 --- /dev/null +++ b/ra/board/ra8m1_ek/board_init.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_EK + * @brief Board specific code for the RA8M1-EK Board + * + * This include file is specific to the RA8M1-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA8M1_EK) */ diff --git a/ra/board/ra8m1_ek/board_leds.c b/ra/board/ra8m1_ek/board_leds.c new file mode 100644 index 000000000..e312f74eb --- /dev/null +++ b/ra/board/ra8m1_ek/board_leds.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8M1_EK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA8M1_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_06_PIN_00, ///< LED1 + (uint16_t) BSP_IO_PORT_04_PIN_14, ///< LED2 + (uint16_t) BSP_IO_PORT_01_PIN_07, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA8M1_EK_LEDS) */ diff --git a/ra/board/ra8m1_ek/board_leds.h b/ra/board/ra8m1_ek/board_leds.h new file mode 100644 index 000000000..7f108308a --- /dev/null +++ b/ra/board/ra8m1_ek/board_leds.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA8M1_EK + * @defgroup BOARD_RA8M1_EK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA8M1_EK_LEDS) */ diff --git a/ra/fsp/inc/api/bsp_api.h b/ra/fsp/inc/api/bsp_api.h index 9148440c8..1b3472a35 100644 --- a/ra/fsp/inc/api/bsp_api.h +++ b/ra/fsp/inc/api/bsp_api.h @@ -33,6 +33,9 @@ #if defined(__GNUC__) && !defined(__ARMCC_VERSION) +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + /* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. * We are not modifying these files so we will ignore these warnings temporarily. */ #pragma GCC diagnostic ignored "-Wconversion" @@ -40,7 +43,7 @@ #endif /* Vector information for this project. This is generated by the tooling. */ -#include "../../src/bsp/mcu/all/bsp_arm_exceptions.h" +#include "../../src/bsp/mcu/all/bsp_exceptions.h" #include "vector_data.h" /* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ @@ -53,28 +56,29 @@ #pragma GCC diagnostic pop #endif +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + /* BSP Common Includes. */ -#include "../../src/bsp/mcu/all/bsp_common.h" + #include "../../src/bsp/mcu/all/bsp_common.h" /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/all/bsp_register_protection.h" -#include "../../src/bsp/mcu/all/bsp_irq.h" -#include "../../src/bsp/mcu/all/bsp_io.h" -#include "../../src/bsp/mcu/all/bsp_group_irq.h" -#include "../../src/bsp/mcu/all/bsp_clocks.h" -#include "../../src/bsp/mcu/all/bsp_module_stop.h" -#include "../../src/bsp/mcu/all/bsp_security.h" + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" /* Factory MCU information. */ -#include "../../inc/fsp_features.h" + #include "../../inc/fsp_features.h" /* BSP Common Includes (Other than bsp_common.h) */ -#include "../../src/bsp/mcu/all/bsp_delay.h" -#include "../../src/bsp/mcu/all/bsp_mcu_api.h" + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" -/* BSP TFU Includes. */ -#if BSP_FEATURE_TFU_SUPPORTED - #include "../../src/bsp/mcu/all/bsp_tfu.h" #endif /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ diff --git a/ra/fsp/inc/api/r_adc_api.h b/ra/fsp/inc/api/r_adc_api.h index cd3c6ac68..bbc2aefeb 100644 --- a/ra/fsp/inc/api/r_adc_api.h +++ b/ra/fsp/inc/api/r_adc_api.h @@ -32,8 +32,6 @@ * an interrupt can be triggered, and if a callback function is provided, the call back is invoked with the * appropriate event information. * - * Implemented by: - * @ref ADC * * @{ **********************************************************************************************************************/ @@ -44,7 +42,9 @@ /* Includes board and MCU related header files. */ #include "bsp_api.h" -#include "r_elc_api.h" +#ifndef BSP_OVERRIDE_ADC_INCLUDE + #include "r_elc_api.h" +#endif #include "r_transfer_api.h" /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ @@ -57,6 +57,7 @@ FSP_HEADER /***************************************************************************** * Typedef definitions ******************************************************************************/ +#ifndef BSP_OVERRIDE_ADC_MODE_T /** ADC operation mode definitions */ typedef enum e_adc_mode @@ -66,6 +67,8 @@ typedef enum e_adc_mode ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels } adc_mode_t; +#endif + /** ADC data resolution definitions */ typedef enum e_adc_resolution { @@ -84,6 +87,8 @@ typedef enum e_adc_alignment ADC_ALIGNMENT_LEFT = 1 ///< Data alignment left } adc_alignment_t; +#ifndef BSP_OVERRIDE_ADC_TRIGGER_T + /** ADC trigger mode definitions */ typedef enum e_adc_trigger { @@ -92,11 +97,16 @@ typedef enum e_adc_trigger ADC_TRIGGER_ASYNC_EXTERNAL = 3, ///< External asynchronous trigger; not for group modes } adc_trigger_t; +#endif + +#ifndef BSP_OVERRIDE_ADC_EVENT_T + /** ADC callback event definitions */ typedef enum e_adc_event { ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_C, ///< Group C scan complete ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested @@ -107,8 +117,11 @@ typedef enum e_adc_event ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred ADC_EVENT_WINDOW_COMPARE_A, ///< Window A comparison condition met ADC_EVENT_WINDOW_COMPARE_B, ///< Window B comparison condition met + ADC_EVENT_ZERO_CROSS_DETECTION, ///< Zero-cross detection interrupt } adc_event_t; +#endif + #ifndef BSP_OVERRIDE_ADC_CHANNEL_T /** ADC channels */ @@ -200,11 +213,13 @@ typedef struct st_adc_callback_args uint16_t unit; ///< ADC device in use adc_event_t event; ///< ADC callback event void const * p_context; ///< Placeholder for user data - adc_channel_t channel; ///< Channel of conversion result. Only valid for r_adc ADC_EVENT_CONVERSION_COMPLETE - uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b + adc_channel_t channel; ///< Channel of conversion result + uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b and r_sdadc_b adc_group_mask_t group_mask; ///< Group Mask } adc_callback_args_t; +#ifndef BSP_OVERRIDE_ADC_INFO_T + /** ADC Information Structure for Transfer Interface */ typedef struct st_adc_info { @@ -219,6 +234,8 @@ typedef struct st_adc_info bool calibration_ongoing; ///< Calibration is in progress. } adc_info_t; +#endif + /** ADC general configuration */ typedef struct st_adc_cfg { @@ -229,8 +246,10 @@ typedef struct st_adc_cfg adc_trigger_t trigger; ///< Default and Group A trigger source IRQn_Type scan_end_irq; ///< Scan end IRQ number IRQn_Type scan_end_b_irq; ///< Scan end group B IRQ number + IRQn_Type scan_end_c_irq; ///< Scan end group C IRQ number uint8_t scan_end_ipl; ///< Scan end interrupt priority uint8_t scan_end_b_ipl; ///< Scan end group B interrupt priority + uint8_t scan_end_c_ipl; ///< Scan end group C interrupt priority void (* p_callback)(adc_callback_args_t * p_args); ///< Callback function; set to NULL for none void const * p_context; ///< Placeholder for user data. Passed to the user callback in @ref adc_callback_args_t. void const * p_extend; ///< Extension parameter for hardware specific settings @@ -244,10 +263,6 @@ typedef struct st_adc_api { /** Initialize ADC Unit; apply power, set the operational mode, trigger sources, interrupt priority, * and configurations common to all channels and sensors. - * @par Implemented as - * - @ref R_ADC_Open() - * - @ref R_ADC_B_Open() - * - @ref R_SDADC_Open() * * @pre Configure peripheral clocks, ADC pins and IRQs prior to calling this function. * @param[in] p_ctrl Pointer to control handle structure @@ -258,10 +273,6 @@ typedef struct st_adc_api /** Configure the scan including the channels, groups, and scan triggers to be used for the unit that * was initialized in the open call. Some configurations are not supported for all implementations. * See implementation for details. - * @par Implemented as - * - @ref R_ADC_ScanCfg() - * - @ref R_ADC_B_ScanCfg() - * - @ref R_SDADC_ScanCfg() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] p_extend See implementation for details @@ -269,17 +280,12 @@ typedef struct st_adc_api fsp_err_t (* scanCfg)(adc_ctrl_t * const p_ctrl, void const * const p_extend); /** Start the scan (in case of a software trigger), or enable the hardware trigger. - * @par Implemented as - * - @ref R_ADC_ScanStart() - * - @ref R_SDADC_ScanStart() * * @param[in] p_ctrl Pointer to control handle structure */ fsp_err_t (* scanStart)(adc_ctrl_t * const p_ctrl); /** Start the scan group (in case of a software trigger), or enable the hardware trigger. - * @par Implemented as - * - @ref R_ADC_B_ScanGroupStart() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] group_mask Mask of groups to start @@ -287,19 +293,12 @@ typedef struct st_adc_api fsp_err_t (* scanGroupStart)(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask); /** Stop the ADC scan (in case of a software trigger), or disable the hardware trigger. - * @par Implemented as - * - @ref R_ADC_ScanStop() - * - @ref R_SDADC_ScanStop() * * @param[in] p_ctrl Pointer to control handle structure */ fsp_err_t (* scanStop)(adc_ctrl_t * const p_ctrl); /** Check scan status. - * @par Implemented as - * - @ref R_ADC_StatusGet() - * - @ref R_ADC_B_StatusGet() - * - @ref R_SDADC_StatusGet() * * @param[in] p_ctrl Pointer to control handle structure * @param[out] p_status Pointer to store current status in @@ -307,10 +306,6 @@ typedef struct st_adc_api fsp_err_t (* scanStatusGet)(adc_ctrl_t * const p_ctrl, adc_status_t * p_status); /** Read ADC conversion result. - * @par Implemented as - * - @ref R_ADC_Read() - * - @ref R_ADC_B_Read() - * - @ref R_SDADC_Read() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) @@ -319,10 +314,6 @@ typedef struct st_adc_api fsp_err_t (* read)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); /** Read ADC conversion result into a 32-bit word. - * @par Implemented as - * - @ref R_ADC_Read32() - * - @ref R_ADC_B_Read32() - * - @ref R_SDADC_Read32() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) @@ -332,10 +323,6 @@ typedef struct st_adc_api /** Calibrate ADC or associated PGA (programmable gain amplifier). The driver may require implementation specific * arguments to the p_extend input. Not supported for all implementations. See implementation for details. - * @par Implemented as - * - @ref R_ADC_Calibrate() - * - @ref R_ADC_B_Calibrate() - * - @ref R_SDADC_Calibrate() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] p_extend Pointer to implementation specific arguments @@ -344,8 +331,6 @@ typedef struct st_adc_api /** Set offset for input PGA configured for differential input. Not supported for all implementations. * See implementation for details. - * @par Implemented as - * - @ref R_SDADC_OffsetSet() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) @@ -355,9 +340,6 @@ typedef struct st_adc_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_ADC_CallbackSet() - * - @ref R_ADC_B_CallbackSet() * * @param[in] p_ctrl Pointer to the ADC control block. * @param[in] p_callback Callback function @@ -365,15 +347,11 @@ typedef struct st_adc_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(adc_ctrl_t * const p_api_ctrl, void (* p_callback)(adc_callback_args_t *), + fsp_err_t (* callbackSet)(adc_ctrl_t * const p_ctrl, void (* p_callback)(adc_callback_args_t *), void const * const p_context, adc_callback_args_t * const p_callback_memory); /** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the * specified A/D unit. - * @par Implemented as - * - @ref R_ADC_Close() - * - @ref R_ADC_B_Close() - * - @ref R_SDADC_Close() * * @param[in] p_ctrl Pointer to control handle structure */ @@ -382,10 +360,6 @@ typedef struct st_adc_api /** Return the ADC data register address of the first (lowest number) channel and the total number of bytes * to be read in order for the DTC/DMAC to read the conversion results of all configured channels. * Return the temperature sensor calibration and slope data. - * @par Implemented as - * - @ref R_ADC_InfoGet() - * - @ref R_ADC_B_InfoGet() - * - @ref R_SDADC_InfoGet() * * @param[in] p_ctrl Pointer to control handle structure * @param[out] p_adc_info Pointer to ADC information structure diff --git a/ra/fsp/inc/api/r_ble_api.h b/ra/fsp/inc/api/r_ble_api.h index 721e619d4..bca331a48 100644 --- a/ra/fsp/inc/api/r_ble_api.h +++ b/ra/fsp/inc/api/r_ble_api.h @@ -26,10 +26,6 @@ * @section BLE_API_SUMMARY Summary * The BLE interface for the Bluetooth Low Energy (BLE) peripheral provides Bluetooth Low Energy functionality. * - * The Bluetooth Low Energy interface can be implemented by: - * - @ref BLE_EXTENDED - * - @ref BLE_BALANCE - * - @ref BLE_COMPACT * * @{ **********************************************************************************************************************/ @@ -52,6 +48,9 @@ FSP_HEADER /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_BLE_PACKED_OPTION + #define BLE_PACKED_OPTION +#endif /* =================================================== Main Macro =================================================== */ @@ -108,7 +107,7 @@ enum RBLE_STATUS_enum { BLE_SUCCESS = 0x0000, - /* commom error code */ + /* common error code */ BLE_ERR_INVALID_PTR = 0x0001, BLE_ERR_INVALID_DATA = 0x0002, BLE_ERR_INVALID_ARG = 0x0003, @@ -1229,8 +1228,178 @@ enum RBLE_STATUS_enum */ #define BLE_GAP_SEC_DEL_REM_ALL (0x03) +/* CTE values */ + +/** + * @def BLE_GAP_CTE_DISABLED + * @brief Disable CTE transmission or receive + */ +#define BLE_GAP_CTE_DISABLED (0x00) + +/** + * @def BLE_GAP_CTE_ENABLED + * @brief Enable CTE transmission or receive + */ +#define BLE_GAP_CTE_ENABLED (0x01) + +/** + * @def BLE_GAP_CTE_MAX_ANTENNA + * @brief Max antenna number + */ +#define BLE_GAP_CTE_MAX_ANTENNA (0x4B) + +/** + * @def BLE_GAP_CTE_TYPE_AOA + * @brief CTE type AoA + */ +#define BLE_GAP_CTE_TYPE_AOA (0) + +/** + * @def BLE_GAP_CTE_TYPE_AOD_1US + * @brief CTE type AoD with slot of 1 us + */ +#define BLE_GAP_CTE_TYPE_AOD_1US (1) + +/** + * @def BLE_GAP_CTE_TYPE_AOD_2US + * @brief CTE type AoD with slot of 2 us + */ +#define BLE_GAP_CTE_TYPE_AOD_2US (2) + +/** + * @def BLE_PAST_ALL_PERD + * @brief + */ +#define BLE_PAST_ALL_PERD (0x00) + +/** + * @def BLE_PAST_CTE_TYPE_NO_AOA + */ +#define BLE_PAST_CTE_TYPE_NO_AOA (0x01) + +/** + * @def BLE_PAST_CTE_TYPE_NO_AOD_1US + */ +#define BLE_PAST_CTE_TYPE_NO_AOD_1US (0x02) + +/** + * @def BLE_PAST_CTE_TYPE_NO_AOD_2US + */ +#define BLE_PAST_CTE_TYPE_NO_AOD_2US (0x04) + +/** + * @def BLE_PAST_CTE_TYPE_NO_CTE + */ +#define BLE_PAST_CTE_TYPE_NO_CTE (0x08) + +/** + * @def BBLE_PAST_CTE_TYPE_ONLY_CTE + */ +#define BLE_PAST_CTE_TYPE_ONLY_CTE (0x10) + /**@} (end addtogroup GAP_API)*/ + +/* =================================================== ISO Macro =================================================== */ + +/** @addtogroup ISO_API + * @ingroup BLE_API + * @{ + */ + +/** + * @def BLE_ISO_MAX_GROUP_ISO_COUNT + * @brief + */ +#define BLE_ISO_MAX_GROUP_ISO_COUNT (4) + +/** + * @def BLE_ISO_PACKING_SEQUENTIAL + * @brief sequential method of arranging subevents of multiple ISO stream + */ +#define BLE_ISO_PACKING_SEQUENTIAL (0x00) + +/** + * @def BLE_ISO_PACKING_INTERLEAVED + * @brief interleaved method of arranging subevents of multiple ISO stream + */ +#define BLE_ISO_PACKING_INTERLEAVED (0x01) + +/** + * @def BLE_ISO_FRAMING_UNFRAMED + * @brief Unframed format for sending ISO PDUs + */ +#define BLE_ISO_FRAMING_UNFRAMED (0x00) + +/** + * @def BLE_ISO_FRAMING_FRAMED + * @brief Framed format for sending ISO PDUs + */ +#define BLE_ISO_FRAMING_FRAMED (0x01) + +/** + * @def BLE_ISO_BROADCAST_CODE_SIZE + * @brief Broadcast code size in BIG + */ +#define BLE_ISO_BROADCAST_CODE_SIZE (16) + +/** + * @def BLE_ISO_TIMESTAMP_NONE + * @brief timestamp value when ts_valid is 0 + */ +#define BLE_ISO_TIMESTAMP_NONE (0) + +/** + * @def BLE_ISO_SYNC_MSE_AUTO + * @brief Let controller choose the max subevent + */ +#define BLE_ISO_SYNC_MSE_AUTO (0x00) + +/** + * @def BLE_ISO_CIS_ACCEPT + * @brief Accept a CIS request. + */ +#define BLE_ISO_CIS_ACCEPT (0x00) + +/** + * @def BLE_ISO_CIS_REJECT + * @brief Reject a CIS request. + */ +#define BLE_ISO_CIS_REJECT (0x01) + +/** + * @def BLE_ISO_DATA_PATH_HCI + * @brief Value to set the ISO data path over HCI. + */ +#define BLE_ISO_DATA_PATH_HCI (0x00) + + +/** + * @def BLE_ISO_DATA_PATH_DIR_INPUT + * @brief audio datapath directions: App to BLE + */ +#define BLE_ISO_DATA_PATH_DIR_INPUT (0x00) + +/** + * @def BLE_ISO_DATA_PATH_DIR_OUTPUT + * @brief audio datapath directions: BLE to App + */ +#define BLE_ISO_DATA_PATH_DIR_OUTPUT (0x01) + +/** + * @def BLE_ISO_DATA_MAX_PDU + * @brief maximum number of data octets of ISO Data PDU + */ +#define BLE_ISO_DATA_MAX_PDU (251) + +/** + * @def BLE_ISO_DATA_MAX_SDU + * @brief maximum number of data octets of ISO Data SDU + */ +#define BLE_ISO_DATA_MAX_SDU (4095) + +/**@} (end addtogroup ISO_API)*/ + /* =================================================== GATT Macro =================================================== */ /** @addtogroup GATT_SERVER_API @@ -2886,7 +3055,7 @@ typedef void (* ble_rf_notify_cb_t)(uint32_t); * @struct st_ble_rf_notify_t * @brief This structure is RF event notify management. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Set enable/disable of each RF event notification @@ -2934,7 +3103,7 @@ typedef struct * @struct st_ble_evt_data_t * @brief st_ble_evt_data_t is the type of the data notified in a GAP Event. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The size of GAP Event parameters. @@ -2953,7 +3122,7 @@ typedef struct * @note The BD address setting format is little endian. \n * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief BD_ADDR. @@ -2992,13 +3161,14 @@ typedef void (* ble_gap_app_cb_t)(uint16_t event_type, ble_status_t event_result **********************************************************************************************************************/ typedef void (* ble_gap_del_bond_cb_t)(st_ble_dev_addr_t * p_addr); + /* =========================================== GAP API Params Definitions =========================================== */ /******************************************************************************************************************//** * @struct st_ble_gap_ext_adv_param_t * @brief Advertising parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Advertising handle identifying the advertising set to be set the advertising parameters. @@ -3305,7 +3475,7 @@ typedef st_ble_gap_ext_adv_param_t st_ble_gap_adv_param_t; * @struct st_ble_gap_adv_data_t * @brief Advertising data/scan response data/periodic advertising data. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Advertising handle identifying the advertising set to be @@ -3381,7 +3551,7 @@ typedef struct * @struct st_ble_gap_perd_adv_param_t * @brief Periodic advertising parameter. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Advertising handle identifying the advertising set to be set periodic advertising parameter. @@ -3426,7 +3596,7 @@ typedef struct * ``` p_phy_param_1M->scan_window / p_phy_param_1M->scan_intv + * p_phy_param_coded->scan_window / p_phy_param_coded->scan_intv <= 1 ``` **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Scan type. @@ -3459,7 +3629,7 @@ typedef struct * @struct st_ble_gap_ext_scan_param_t * @brief Scan parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Own BD Address Type. @@ -3575,7 +3745,7 @@ typedef st_ble_gap_ext_scan_param_t st_ble_gap_scan_param_t; * @struct st_ble_gap_scan_on_t * @brief Parameters configured when scanning starts. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Procedure type. @@ -3666,7 +3836,7 @@ typedef struct * conn_intv_max_Time(ms) = conn_intv_max * 1.25 * Supervision_timeout(ms) = sup_to * 10 **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Minimum connection interval. @@ -3718,7 +3888,7 @@ typedef struct * @struct st_ble_gap_conn_phy_param_t * @brief Connection parameters per PHY. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Scan interval. @@ -3746,7 +3916,7 @@ typedef struct * @struct st_ble_gap_create_conn_param_t * @brief Connection parameters used in R_BLE_GAP_CreateConn(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief This field specifies whether the White List is used or not, when connecting with a remote device. @@ -3861,7 +4031,7 @@ typedef struct * @struct st_ble_gap_rslv_list_key_set_t * @brief IRK of a remote device and IRK type of local device used in R_BLE_GAP_ConfRslvList(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief IRK of a remote device to be registered in the Resolving List. @@ -3883,7 +4053,7 @@ typedef struct * @struct st_ble_gap_set_phy_param_t * @brief PHY configuration parameters used in R_BLE_GAP_SetPhy(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Transmitter PHY preference. @@ -3923,7 +4093,7 @@ typedef struct * @struct st_ble_gap_set_def_phy_param_t * @brief PHY preferences which allows a remote device to set used in R_BLE_GAP_SetDefPhy(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Transmitter PHY preferences which a remote device may change. @@ -3955,7 +4125,7 @@ typedef struct * @brief Pairing parameters required from a remote device or * information about keys distributed from a remote device. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Security level. @@ -3997,7 +4167,7 @@ typedef struct * @struct st_ble_gap_key_dist_t * @brief Keys distributed from a remote device. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief LTK. @@ -4030,7 +4200,7 @@ typedef struct * @struct st_ble_gap_key_ex_param_t * @brief This structure includes the distributed keys and negotiated LTK size. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Key information. @@ -4075,7 +4245,7 @@ typedef struct * @struct st_ble_gap_pairing_param_t * @brief Pairing parameters used in R_BLE_GAP_SetPairingParams(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief IO capabilities of local device. @@ -4232,7 +4402,7 @@ typedef struct * @struct st_ble_gap_oob_data_t * @brief Oob data received from the remote device. This is used in R_BLE_GAP_SetRemOobData(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief OOB data used in Legacy Pairing. @@ -4250,1584 +4420,3412 @@ typedef struct uint8_t sc_rand[BLE_GAP_OOB_RANDOM_VAL_SIZE]; } st_ble_gap_oob_data_t; -/* ============================================== GAP Event Parameters ============================================== */ +/******************************************************************************************************************//** + * @struct st_ble_gap_past_param_t + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Working mode + * + * The action to be taken when periodic advertising + * synchronization information is received. + */ + uint8_t mode; + + /** + * @brief Maximum event skip + * + * The number of periodic advertising packets that can be skipped + * after a successful receive. + */ + uint16_t skip; -/* Event Code : BLE_GAP_EVENT_STACK_ON : none */ + /** + * @brief Synchronization timeout (N * 10 ms) + * + * Synchronization timeout for the periodic advertising sync. + * Range 0x000A to 0x4000 (100 ms to 163840 ms) + */ + uint16_t timeout; -/* Event Code : BLE_GAP_EVENT_STACK_OFF : none */ + /** Periodic Advertising Sync Transfer options */ + uint8_t cte_type; +} st_ble_gap_past_param_t; -/* Event Code : BLE_GAP_EVENT_LOC_VER_INFO : st_ble_gap_loc_dev_info_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_ver_num_t - * @brief Version number of host stack. + * @struct st_ble_gap_cte_antenna_info_t + * @brief This is the parameters used in R_BLE_GAP_GetAntennaInfo(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /* Bitfield holding optional switching and sampling rates + * bit should be one or compose of: + * BLE_GAP_CTE_TYPE_AOA (bit 0) + * BLE_GAP_CTE_TYPE_AOD_1US (bit 1) + * BLE_GAP_CTE_TYPE_AOD_2US (bit 2) + * */ + uint8_t switch_sr; + + /* Available antennae number */ + uint8_t num_ant; + + /* Maximum supported antenna switching pattern length */ + uint8_t max_pattern_len; + + /* Maximum length of CTE in 8[us] units */ + uint8_t max_cte_len; +} st_ble_gap_cte_antenna_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_recv_test_param_t + * @brief This is the parameters used in R_BLE_GAP_ReceiverTest() **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Major version number. + * @brief RF channel. */ - uint8_t major; + uint8_t rx_ch; /** - * @brief Minor version number. + * @brief The transmitter PHY of packets. */ - uint8_t minor; + uint8_t phy; /** - * @brief Subminor version number. + * @brief Whether or not the Controller should assume the receiver has a stable modulation index. */ - uint8_t subminor; -} st_ble_gap_ver_num_t; + uint8_t mod_idx; -/******************************************************************************************************************//** - * @struct st_ble_gap_loc_ver_info_t - * @brief Version number of Controller. - * @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers). - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Bluetooth HCI version. + * @brief Expected length of the Constant Tone Extensions in received test reference packets. */ - uint8_t hci_ver; + uint8_t expect_cte_len; /** - * @brief Bluetooth HCI revision. + * @brief Expected type of the Constant Tone Extensions in received test reference packets. */ - uint16_t hci_rev; + uint8_t expect_cte_type; /** - * @brief Link Layer revision. + * @brief Switching and sampling slots durations. */ - uint8_t lmp_ver; + uint8_t slot_duration; /** - * @brief Manufacturer ID. + * @brief The number of Antenna IDs in the pattern. */ - uint16_t mnf_name; + uint8_t switch_pattern_len; /** - * @brief Link Layer subversion. + * @brief Antenna ID in the pattern. */ - uint16_t lmp_sub_ver; -} st_ble_gap_loc_ver_info_t; + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; +} st_ble_gap_recv_test_param_t; /******************************************************************************************************************//** - * @struct st_ble_gap_loc_dev_info_evt_t - * @brief Version information of local device. + * @struct st_ble_gap_trans_test_param_t + * @brief This is the parameters used in R_BLE_GAP_TransmitterTest(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Bluetooth Device Address. + * @brief RF channel. */ - st_ble_dev_addr_t l_dev_addr; + uint8_t tx_ch; /** - * @brief Version number of host stack in local device. + * @brief Length of the Payload of the test reference packets. */ - st_ble_gap_ver_num_t l_ver_num; + uint8_t test_data_len; /** - * @brief Version number of Controller in local device. + * @brief Contents of the Payload of the test reference packets. */ - st_ble_gap_loc_ver_info_t l_bt_info; -} st_ble_gap_loc_dev_info_evt_t; + uint8_t packet_payload; -/* Event Code : BLE_GAP_EVENT_HW_ERR : st_ble_gap_hw_err_evt_t */ + /** + * @brief The transmitter PHY of packets. + */ + uint8_t phy; -/******************************************************************************************************************//** - * @struct st_ble_gap_hw_err_evt_t - * @brief Hardware error that is notified from Controller. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief The hw_code field indicates the cause of the hardware error. + * @brief Length of the Constant Tone Extension in the test reference packets. */ - uint8_t hw_code; -} st_ble_gap_hw_err_evt_t; + uint8_t cte_len; -/* Event Code : BLE_GAP_EVENT_CMD_ERR: st_ble_gap_cmd_err_evt_t */ + /** + * @brief Type of the Constant Tone Extension in the test reference packets. + */ + uint8_t cte_type; -/******************************************************************************************************************//** - * @struct st_ble_gap_cmd_err_evt_t - * @brief HCI Command error. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief The opcode of HCI Command which caused the error. + * @brief The number of Antenna IDs in the pattern. */ - uint16_t op_code; + uint8_t switch_pattern_len; /** - * @brief Module ID which caused the error. + * @brief Antenna ID in the pattern. */ - uint32_t module_id; -} st_ble_gap_cmd_err_evt_t; + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; -/* Event Code : BLE_GAP_EVENT_ADV_REPT_IND: st_ble_gap_adv_rept_evt_t */ -/* ADV report related Event defines */ -/* Legacy ADV Report related structure */ + /** + * @brief Transmit power level to be used by the transmitter. + */ + int8_t tx_power_level; +} st_ble_gap_trans_test_param_t; /******************************************************************************************************************//** - * @struct st_ble_gap_adv_rept_t - * @brief Advertising Report. + * @struct st_ble_gap_set_path_loss_rpt_param_t + * @brief This is the parameters used in R_BLE_GAP_SetPathLossReportingParam(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief The number of Advertising Reports received. + * @brief Connection handle. */ - uint8_t num; + uint16_t conn_hdl; /** - * @brief Type of Advertising Packet. - * @details - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
valuerdescription
0x00Connectable and scannable undirected advertising(ADV_IND).
0x01Connectable directed advertising(ADV_DIRECT_IND).
0x02Scannable undirected advertising(ADV_SCAN_IND).
0x03Non-connectable undirected advertising(ADV_NONCONN_IND).
0x04Scan response(SCAN_RSP).
+ * @brief High threshold for the path loss. */ - uint8_t adv_type; + uint8_t high_thr; /** - * @brief Address type of the advertiser. - * @details - * | value | description | - * |:--------- |:--------------------------------------------------------------- | - * | 0x00 | Public Address. | - * | 0x01 | Random Address. | - * | 0x02 | Public Identity Address which could be resolved in Controller. | - * | 0x03 | Random Identity Address which could be resolved in Controller. | + * @brief Hysteresis value for the high threshold. */ - uint8_t addr_type; + uint8_t high_hys; /** - * @brief Address of the advertiser. - * @note The BD address setting format is little endian. + * @brief Low threshold for the path loss. */ - uint8_t * p_addr; + uint8_t low_thr; /** - * @brief Length of Advertising data(in bytes). - * @details Valid range is 0 - 31. + * @brief Hysteresis value for the low threshold. */ - uint8_t len; + uint8_t low_hys; /** - * @brief RSSI(in dBm). - * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n - * If the tx_pwr is 127, it means that RSSI could not be retrieved. + * @brief Minimum time in number of connection events to be observed once the path loss crosses the threshold before an event is generated. */ - int8_t rssi; + uint16_t min_time_spent; +} st_ble_gap_set_path_loss_rpt_param_t; +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_connless_t + * @brief connectionless CTE param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Advertising data/Scan Response Data. + * @brief For connectionless CTE handle is the Sync handle identifying the + * Periodic Sync that has been established. */ - uint8_t * p_data; -} st_ble_gap_adv_rept_t; + uint16_t adv_hdl; + + /** Length of CTE in 8us units. Range: 0x02 to 0x14 */ + uint8_t cte_len; + + /** + * @brief CTE type. + * + * Allowed values are: + * BLE_GAP_CTE_TYPE_AOA + * BLE_GAP_CTE_TYPE_AOD_1US + * BLE_GAP_CTE_TYPE_AOD_2US + */ + uint8_t cte_type; + + /** Number of CTE to transmit in each periodic adv interval. Range: 0x01 to 0x10 */ + uint8_t cte_count; + + /** Number of Antenna IDs in the switch pattern. */ + uint8_t pattern_len; + + /** List of antenna IDs in the pattern. */ + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; +} st_ble_gap_cte_connless_t; /******************************************************************************************************************//** - * @struct st_ble_gap_ext_adv_rept_t - * @brief Extended Advertising Report. + * @struct st_ble_gap_cte_conn_t + * @brief connection CTE param **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief The number of Advertising Reports received. + * @brief The ACL connection handle. */ - uint8_t num; + uint16_t conn_hdl; /** - * @brief Type of Advertising Packet. - * @details - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Bit Numberdescription
0Connectable advertising.
1Scannable advertising.
2Directed advertising.
3Scan response.
4Legacy advertising PDU.
5-6The status of Advertising Data/Scan Response Data.
- * Data Status:
- * 00b = Complete
- * 01b = Incomplete, more data come
- * 10b = Incomplete, data truncated, no more to come
- *
All other bitsReserved for future use
+ * @brief bitfield of CTE types that are allowed + * + * bit should be one or compose of: + * BLE_GAP_CTE_TYPE_AOA (bit 0) + * BLE_GAP_CTE_TYPE_AOD_1US (bit 1) + * BLE_GAP_CTE_TYPE_AOD_2US (bit 2) */ - uint16_t adv_type; + uint8_t allow_cte_types; + + /** Number of Antenna IDs in the switch pattern. */ + uint8_t pattern_len; + /** List of antenna IDs in the pattern. */ + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; +} st_ble_gap_cte_conn_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_connless_recv_t + * @brief connectionless CTE receive param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Address type of the advertiser. - * @details - * | value | description | - * |:--------- |:--------------------------------------------------------------- | - * | 0x00 | Public Address. | - * | 0x01 | Random Address. | - * | 0x02 | Public Identity Address which could be resolved in Controller. | - * | 0x03 | Random Identity Address which could be resolved in Controller. | - * | 0xFF | Anonymous advertisement. | + * @brief Periodic Sync that has been established for CTE. */ - uint8_t addr_type; + uint16_t sync_hdl; /** - * @brief Address of the advertiser. - * @note The BD address setting format is little endian. + * @brief CTE type + * @details CTE type should be get from st_ble_gap_perd_adv_rept_t of BLE_GAP_EVENT_ADV_REPT_IND event + * in connectionless CTE, or get from ACL connection in connection CTE. + * The slot_durations, pattern_len, and ant_ids parameters are only used when receiving + * an AoA Constant Tone Extension and do not affect the reception of an AoD Constant Tone + * Extension. */ - uint8_t * p_addr; + uint8_t cte_type; /** - * @brief The primary PHY configuration of the advertiser. - * @details - * The primary PHY configuration of the advertiser. - * | value | description | - * |:--------- |:------------------------ | - * | 0x01 | 1M PHY | - * | 0x03 | Coded PHY | + * @brief Max number of CTEs to receive. + * Min is 1, max is 10, 0 means receive continuously. */ - uint8_t adv_phy; + uint8_t max_cte_count; /** - * @brief The secondary PHY configuration of the advertiser. - * @details - * | value | description | - * |:--------- |:---------------------------------------------------------------- | - * | 0x00 | Nothing has been received with Secondary Advertising Channel. | - * | 0x01 | The Secondary Advertising PHY configuration was 1M PHY. | - * | 0x02 | The Secondary Advertising PHY configuration was 2M PHY. | - * | 0x03 | The Secondary Advertising PHY configuration was Coded PHY. | + * Antenna switching slots. 1 for 1us or 2 for 2us */ - uint8_t sec_adv_phy; + uint8_t slot_durations; /** - * @brief Advertising SID included in the received Advertising Report. - * @details Valid range is 0 <= adv_sid <= 0x0F and 0xFF.\n - * If the adv_sid is 0xFF, there is no field which includes SID. + * @brief Length of antenna switch pattern. */ - uint8_t adv_sid; + uint8_t pattern_len; /** - * @brief TX power(in dBm). - * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n - * If the tx_pwr is 127, it means that Tx power could not be retrieved. + * @brief Antenna switch pattern. */ - int8_t tx_pwr; + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; +} st_ble_gap_cte_connless_recv_t; +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_conn_rx_param_t + * @brief connection CTE receive param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief RSSI(in dBm). - * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n - * If the tx_pwr is 127, it means that RSSI could not be retrieved. + * @brief For connection CTE handle is the ACL connection handle. */ - int8_t rssi; + uint16_t conn_hdl; /** - * @brief Periodic Advertising interval. - * @details If the perd_adv_intv is 0x0000, it means that this advertising is not periodic advertising.\n - * If the perd_adv_intv is 0x0006 - 0xFFFF, - * it means that this field is the Periodic Advertising interval.\n - * Periodic Advertising interval = per_adv_intr * 1.25ms. + * Antenna switching slots. 1 for 1us or 2 for 2us */ - uint16_t perd_adv_intv; + uint8_t slot_durations; /** - * @brief The address type of Direct Advertising PDU. - * @details - * | value | description | - * |:--------- |:--------------------------------------------------------------------- | - * | 0x00 | Public Address. | - * | 0x01 | Random Address. | - * | 0x02 | Public Identity Address which could be resolved in Controller. | - * | 0x03 | Random Identity Address which could be resolved in Controller. | - * | 0xFE | Resolvable Privacy Address which could not be resolved in Controller. | + * @brief Length of antenna switch pattern. */ - uint8_t dir_addr_type; + uint8_t pattern_len; /** - * @brief Address of Direct Advertising PDU. - * @note The BD address setting format is little endian. + * @brief Antenna switch pattern. */ - uint8_t * p_dir_addr; + uint8_t ant_ids[BLE_GAP_CTE_MAX_ANTENNA]; +} st_ble_gap_cte_conn_rx_param_t; +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_conn_req_t + * @brief connection CTE request + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Length of Advertising data(in bytes). - * @details Valid range is 0 - 229. + * @brief For connection CTE handle is the ACL connection handle. */ - uint8_t len; + uint16_t conn_hdl; /** - * @brief Advertising data/Scan Response Data. + * @brief Requested interval for initiating the CTE Request procedure. + * + * Value 0x0 means, run the procedure once. Other values are intervals in number of + * connection events, to run the command periodically. */ - uint8_t * p_data; -} st_ble_gap_ext_adv_rept_t; + uint16_t interval; + + /** Requested length of the CTE in 8 us units. */ + uint8_t cte_length; + + /** + * @brief Requested type of the CTE. + * + * Allowed values are BLE_GAP_CTE_TYPE_AOA, BLE_GAP_CTE_TYPE_AOD_1US and + * BLE_GAP_CTE_TYPE_AOD_2US + */ + uint8_t cte_type; +} st_ble_gap_cte_conn_req_t; /******************************************************************************************************************//** - * @struct st_ble_gap_perd_adv_rept_t - * @brief Periodic Advertising Report. + * @struct st_ble_gap_subrate_param_t + * @brief subrating param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t subrate_min; + uint16_t subrate_max; + uint16_t max_latency; + uint16_t continuation_num; + uint16_t supervision_timeout; +} st_ble_gap_subrate_param_t; + +/* ============================================== GAP Event Parameters ============================================== */ + +/* Event Code : BLE_GAP_EVENT_STACK_ON : none */ + +/* Event Code : BLE_GAP_EVENT_STACK_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_LOC_VER_INFO : st_ble_gap_loc_dev_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ver_num_t + * @brief Version number of host stack. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Sync handle. - * @details Valid range is 0x0000 - 0x0EFF. + * @brief Major version number. */ - uint16_t sync_hdl; + uint8_t major; /** - * @brief TX power(in dBm). - * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n - * If tx_pwr is 127, it means that Tx power could not be retrieved. + * @brief Minor version number. */ - int8_t tx_pwr; + uint8_t minor; /** - * @brief RSSI(in dBm). - * @details Valid range is -127 <= rssi <= 20 and 127.\n - * If rssi is 127, it means that RSSI could not be retrieved. + * @brief Subminor version number. */ - int8_t rssi; + uint8_t subminor; +} st_ble_gap_ver_num_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_loc_ver_info_t + * @brief Version number of Controller. + * @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Bluetooth HCI version. + */ + uint8_t hci_ver; /** - * @brief Reserved for future use. + * @brief Bluetooth HCI revision. */ - uint8_t rfu; + uint16_t hci_rev; /** - * @brief Reserved for future use. - * @details - * | value | description | - * |:--------- |:------------------------------------------------------- | - * | 0x00 | Data Complete. | - * | 0x01 | Data incomplete, more data to come. | - * | 0x02 | Data incomplete, data truncated, no more to come. | + * @brief Link Layer revision. */ - uint8_t data_status; + uint8_t lmp_ver; /** - * @brief Length of Periodic Advertising data(in bytes). - * @details Valid range is 0 - 247. + * @brief Manufacturer ID. */ - uint8_t len; + uint16_t mnf_name; /** - * @brief Periodic Advertising data. + * @brief Link Layer subversion. */ - uint8_t * p_data; -} st_ble_gap_perd_adv_rept_t; + uint16_t lmp_sub_ver; +} st_ble_gap_loc_ver_info_t; /******************************************************************************************************************//** - * @struct st_ble_gap_adv_rept_evt_t - * @brief Advertising report. + * @struct st_ble_gap_loc_dev_info_evt_t + * @brief Version information of local device. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Data type. - * @details - * | value | description | - * |:-------------------- |:---------------------------------- | - * | 0x00 | Advertising Report. | - * | 0x01 | Extended Advertising Report. | - * | 0x02 | Periodic Advertising Report. | - * - * If the BLE Protocol Stack library type is "extended", - * the adv_rpt_type field in a Legacy Advertising Report event is 0x01. + * @brief Bluetooth Device Address. */ - uint8_t adv_rpt_type; + st_ble_dev_addr_t l_dev_addr; /** - * @brief Advertising Report. + * @brief Version number of host stack in local device. */ - union - { - /** - * @brief Advertising Report. - */ - st_ble_gap_adv_rept_t * p_adv_rpt; - - /** - * @brief Extended Advertising Report. - */ - st_ble_gap_ext_adv_rept_t * p_ext_adv_rpt; + st_ble_gap_ver_num_t l_ver_num; - /** - * @brief Periodic Advertising Report. - */ - st_ble_gap_perd_adv_rept_t * p_per_adv_rpt; - } param; -} st_ble_gap_adv_rept_evt_t; + /** + * @brief Version number of Controller in local device. + */ + st_ble_gap_loc_ver_info_t l_bt_info; +} st_ble_gap_loc_dev_info_evt_t; -/* Event Code : BLE_GAP_EVENT_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ -/* Event Code : BLE_GAP_EVENT_ADV_ON : st_ble_gap_adv_set_evt_t */ -/* Event Code : BLE_GAP_EVENT_PERD_ADV_ON : st_ble_gap_adv_set_evt_t */ -/* Event Code : BLE_GAP_EVENT_PERD_ADV_OFF : st_ble_gap_adv_set_evt_t */ -/* Event Code : BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_HW_ERR : st_ble_gap_hw_err_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_adv_set_evt_t - * @brief Advertising handle. + * @struct st_ble_gap_hw_err_evt_t + * @brief Hardware error that is notified from Controller. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Advertising handle specifying the advertising set configured advertising parameters. + * @brief The hw_code field indicates the cause of the hardware error. */ - uint8_t adv_hdl; -} st_ble_gap_adv_set_evt_t; + uint8_t hw_code; +} st_ble_gap_hw_err_evt_t; -/* Event Code : BLE_GAP_EVENT_ADV_OFF : st_ble_gap_adv_off_evt_t */ +/* Event Code : BLE_GAP_EVENT_CMD_ERR: st_ble_gap_cmd_err_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_adv_off_evt_t - * @brief Information about the advertising set which stops advertising. + * @struct st_ble_gap_cmd_err_evt_t + * @brief HCI Command error. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Advertising handle identifying the advertising set which has stopped advertising. - * @details Valid range is 0x00 - 0x03. + * @brief The opcode of HCI Command which caused the error. */ - uint8_t adv_hdl; - - /** - * @brief The reason for stopping advertising. - * @details - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
valuedescription
0x01 - * Advertising has been stopped by R_BLE_GAP_StopAdv(). - *
0x02 - * Because the duration specified by R_BLE_GAP_StartAdv() was expired, - * advertising has terminated. - *
0x03 - * Because the max_extd_adv_evts parameter specified by R_BLE_GAP_StartAdv() was reached, - * advertising has terminated. - *
0x04 - * Because the connection was established with the remote device, advertising has terminated. - *
- */ - uint8_t reason; - - /** - * @brief Connection handle. - * @details If the reason field is 0x04, this field indicates connection handle identifying - * the remote device connected with local device. - * If other reasons, ignore this field. - */ - uint16_t conn_hdl; + uint16_t op_code; /** - * @brief The number of the advertising event that has been received until advertising has terminated. - * @details If max_extd_adv_evts by R_BLE_GAP_StartAdv() is not 0, this parameter is valid. + * @brief Module ID which caused the error. */ - uint8_t num_comp_ext_adv_evts; -} st_ble_gap_adv_off_evt_t; + uint32_t module_id; +} st_ble_gap_cmd_err_evt_t; -/* Event Code : BLE_GAP_EVENT_ADV_DATA_UPD_COMP : st_ble_gap_adv_data_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_REPT_IND: st_ble_gap_adv_rept_evt_t */ +/* ADV report related Event defines */ +/* Legacy ADV Report related structure */ /******************************************************************************************************************//** - * @struct st_ble_gap_adv_data_evt_t - * @brief This structure notifies that advertising data has been set to Controller by R_BLE_GAP_SetAdvSresData(). + * @struct st_ble_gap_adv_rept_t + * @brief Advertising Report. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Advertising handle identifying the advertising set to - * which advertising data/scan response data/periodic advertising data is set. + * @brief The number of Advertising Reports received. */ - uint8_t adv_hdl; + uint8_t num; /** - * @brief Type of the data set to the advertising set. + * @brief Type of Advertising Packet. * @details - * | value | description | - * |:------------------------------------ |:--------------------------- | - * | BLE_GAP_ADV_DATA_MODE(0x00) | Advertising data | - * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data | - * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data | + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuerdescription
0x00Connectable and scannable undirected advertising(ADV_IND).
0x01Connectable directed advertising(ADV_DIRECT_IND).
0x02Scannable undirected advertising(ADV_SCAN_IND).
0x03Non-connectable undirected advertising(ADV_NONCONN_IND).
0x04Scan response(SCAN_RSP).
*/ - uint8_t data_type; -} st_ble_gap_adv_data_evt_t; - -/* Event Code : BLE_GAP_EVENT_ADV_SET_REMOVE_COMP : st_ble_gap_rem_adv_set_evt_t */ + uint8_t adv_type; -/******************************************************************************************************************//** - * @struct st_ble_gap_rem_adv_set_evt_t - * @brief This structure notifies that an advertising set has been removed. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief This field indicates that the advertising set has been removed or cleared. + * @brief Address type of the advertiser. * @details - * | value | description | - * |:-------- |:--------------------------------------- | - * | 0x01 | The advertising set has been removed. | - * | 0x02 | The advertising set has been cleared. | + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | */ - uint8_t remove_op; + uint8_t addr_type; /** - * @brief Advertising handle identifying the advertising set which has been removed. - * @details If the advertising set has been cleared, this field is ignored. + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. */ - uint8_t adv_hdl; -} st_ble_gap_rem_adv_set_evt_t; + uint8_t * p_addr; -/* Event Code : BLE_GAP_EVENT_SCAN_ON : none */ -/* Event Code : BLE_GAP_EVENT_SCAN_OFF : none */ + /** + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 31. + */ + uint8_t len; -/* Event Code : BLE_GAP_EVENT_CONN_IND : st_ble_gap_conn_evt_t */ + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; -/******************************************************************************************************************//** - * @struct st_ble_gap_conn_evt_t - * @brief This structure notifies that a link has been established. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the created link. + * @brief Advertising data/Scan Response Data. */ - uint16_t conn_hdl; + uint8_t * p_data; +} st_ble_gap_adv_rept_t; +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_adv_rept_t + * @brief Extended Advertising Report. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief The role of the link. - * @details - * | value | description | - * |:-------- |:-------------- | - * | 0x00 | Master | - * | 0x01 | Slave | + * @brief The number of Advertising Reports received. */ - uint8_t role; + uint8_t num; /** - * @brief Address type of the remote device. + * @brief Type of Advertising Packet. * @details * * - * + * * * * - * - * + * + * * * - * - * + * + * * * - * - * + * + * + * + * + * + * + * + * + * + * + * + * + * * * - * - * + * * *
valueBit Numberdescription
0x00Public Address0Connectable advertising.
0x01Random Address1Scannable advertising.
0x02Public Identity Address.
- * It indicates that the Controller could resolve the resolvable private address of the remote device. + * 		2Directed advertising.
3Scan response.
4Legacy advertising PDU.
5-6The status of Advertising Data/Scan Response Data.
+ * Data Status:
+ * 00b = Complete
+ * 01b = Incomplete, more data come
+ * 10b = Incomplete, data truncated, no more to come
*
0x03Random Identity Address.
- * It indicates that the Controller could resolve the resolvable private address of the remote device. - * 		+ * All other bitsReserved for future use
*/ - uint8_t remote_addr_type; - - /** - * @brief Address of the remote device. - * @note The BD address setting format is little endian. - */ - uint8_t remote_addr[BLE_BD_ADDR_LEN]; + uint16_t adv_type; /** - * @brief Resolvable private address that local device used in connection procedure. + * @brief Address type of the advertiser. * @details - * The local device address used in creating the link when the address type was set to - * BLE_GAP_ADDR_RPA_ID_PUBLIC or BLE_GAP_ADDR_RPA_ID_RANDOM by R_BLE_GAP_SetAdvParam() or - * R_BLE_GAP_CreateConn(). - * If the address type was set to other than BLE_GAP_ADDR_RPA_ID_PUBLIC and - * BLE_GAP_ADDR_RPA_ID_RANDOM, this field is set to all-zero. - * @note The BD address setting format is little endian. + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFF | Anonymous advertisement. | */ - uint8_t local_rpa[BLE_BD_ADDR_LEN]; + uint8_t addr_type; /** - * @brief Resolvable private address that the remote device used in connection procedure. - * @details - * This field indicates the remote resolvable private address when remote_addr_type is 0x02 or 0x03. - * If remote_addr_type is other than 0x02 and 0x03, this field is set to all-zero. - * @note The BD address setting format is little endian. + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. */ - uint8_t remote_rpa[BLE_BD_ADDR_LEN]; + uint8_t * p_addr; /** - * @brief Connection interval. + * @brief The primary PHY configuration of the advertiser. * @details - * Valid range is 0x0006 - 0x0C80.\n - * Time(ms) = conn_intv * 1.25. + * The primary PHY configuration of the advertiser. + * | value | description | + * |:--------- |:------------------------ | + * | 0x01 | 1M PHY | + * | 0x03 | Coded PHY | */ - uint16_t conn_intv; + uint8_t adv_phy; /** - * @brief Slave latency. + * @brief The secondary PHY configuration of the advertiser. * @details - * Valid range is 0x0000 - 0x01F3. - */ - uint16_t conn_latency; + * | value | description | + * |:--------- |:---------------------------------------------------------------- | + * | 0x00 | Nothing has been received with Secondary Advertising Channel. | + * | 0x01 | The Secondary Advertising PHY configuration was 1M PHY. | + * | 0x02 | The Secondary Advertising PHY configuration was 2M PHY. | + * | 0x03 | The Secondary Advertising PHY configuration was Coded PHY. | + */ + uint8_t sec_adv_phy; /** - * @brief Supervision timeout. - * @details - * Valid range is 0x000A - 0x0C80.Time(ms) = sup_to * 10. + * @brief Advertising SID included in the received Advertising Report. + * @details Valid range is 0 <= adv_sid <= 0x0F and 0xFF.\n + * If the adv_sid is 0xFF, there is no field which includes SID. */ - uint16_t sup_to; + uint8_t adv_sid; /** - * @brief Master_Clock_Accuracy. - * @details - * | value | description | - * |:---------|:--------------------------- | - * | 0x00 | 500ppm | - * | 0x01 | 250ppm | - * | 0x02 | 150ppm | - * | 0x03 | 100ppm | - * | 0x04 | 75ppm | - * | 0x05 | 50ppm | - * | 0x06 | 30ppm | - * | 0x07 | 20ppm | + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that Tx power could not be retrieved. */ - uint8_t clk_acc; -} st_ble_gap_conn_evt_t; - -/* Event Code : BLE_GAP_EVENT_DISCONN_IND : st_ble_gap_disconn_evt_t */ + int8_t tx_pwr; -/******************************************************************************************************************//** - * @struct st_ble_gap_disconn_evt_t - * @brief This structure notifies that a link has been disconnected. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the link disconnected. + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. */ - uint16_t conn_hdl; + int8_t rssi; /** - * @brief The reason for disconnection. - * @details - * Refer Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + * @brief Periodic Advertising interval. + * @details If the perd_adv_intv is 0x0000, it means that this advertising is not periodic advertising.\n + * If the perd_adv_intv is 0x0006 - 0xFFFF, + * it means that this field is the Periodic Advertising interval.\n + * Periodic Advertising interval = per_adv_intr * 1.25ms. */ - uint8_t reason; -} st_ble_gap_disconn_evt_t; - -/* Event Code : BLE_GAP_EVENT_CONN_CANCEL_COMP : none */ - -/* Event Code : BLE_GAP_EVENT_WHITE_LIST_CONF_COMP : st_ble_gap_white_list_conf_evt_t */ - -/* Event Code : BLE_GAP_EVENT_RAND_ADDR_SET_COMP : none */ - -/* Event Code : BLE_GAP_EVENT_CH_MAP_RD_COMP : st_ble_gap_rd_ch_map_evt_t */ -/* Read Channel MAP */ + uint16_t perd_adv_intv; -/******************************************************************************************************************//** - * @struct st_ble_gap_rd_ch_map_evt_t - * @brief This structure notifies that Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the link whose Channel Map was retrieved. + * @brief The address type of Direct Advertising PDU. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFE | Resolvable Privacy Address which could not be resolved in Controller. | */ - uint16_t conn_hdl; + uint8_t dir_addr_type; /** - * @brief Channel Map. + * @brief Address of Direct Advertising PDU. + * @note The BD address setting format is little endian. */ - uint8_t ch_map[BLE_GAP_CH_MAP_SIZE]; -} st_ble_gap_rd_ch_map_evt_t; - -/* Event Code : BLE_GAP_EVENT_CH_MAP_SET_COMP : none */ - -/* Event Code : BLE_GAP_EVENT_RSSI_RD_COMP : st_ble_gap_rd_rssi_evt_t */ + uint8_t * p_dir_addr; -/******************************************************************************************************************//** - * @struct st_ble_gap_rd_rssi_evt_t - * @brief This structure notifies that RSSI has been retrieved by R_BLE_GAP_ReadRssi(). - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the link whose RSSI was retrieved. + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 229. */ - uint16_t conn_hdl; + uint8_t len; /** - * @brief RSSI(in dBm). - * @details - * Valid range is -127 < rssi < 20 and 127.\n - * If this field is 127, it indicates that RSSI could not be retrieved. + * @brief Advertising data/Scan Response Data. */ - int8_t rssi; -} st_ble_gap_rd_rssi_evt_t; - -/* Event Code : BLE_GAP_EVENT_GET_REM_DEV_INFO : st_ble_gap_dev_info_evt_t */ + uint8_t * p_data; +} st_ble_gap_ext_adv_rept_t; /******************************************************************************************************************//** - * @struct st_ble_gap_dev_info_evt_t - * @brief This structure notifies that information about remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + * @struct st_ble_gap_perd_adv_rept_t + * @brief Periodic Advertising Report. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device whose information has been retrieved. + * @brief Sync handle. + * @details Valid range is 0x0000 - 0x0EFF. */ - uint16_t conn_hdl; + uint16_t sync_hdl; /** - * @brief Information about the remote device. This field is a bitwise OR of the following values. - * @details - * | Bit Number | description | - * |:-------------------|:------------------------------- | - * | bit0 | Address | - * | bit1 | Version, company_id, subversion | - * | bit2 | Feature | - * | All other bits | Reserved for future use | + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If tx_pwr is 127, it means that Tx power could not be retrieved. */ - uint8_t get_status; + int8_t tx_pwr; /** - * @brief Address of the remote device. + * @brief RSSI(in dBm). + * @details Valid range is -127 <= rssi <= 20 and 127.\n + * If rssi is 127, it means that RSSI could not be retrieved. */ - st_ble_dev_addr_t addr; + int8_t rssi; /** - * @brief The version of Link Layer of the remote device. + * @brief Type of Constant Tone Extension in the periodic advertising packets. * @details - * Refer to Bluetooth SIG Assigned Number - * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + * | value | description | + * |:--------- |:------------------------------------------------------- | + * | 0x00 | AoA Constant Tone Extension. | + * | 0x01 | AoD Constant Tone Extension with 1 μs slots. | + * | 0x02 | AoD Constant Tone Extension with 2 μs slots. | + * | 0xFF | No Constant Tone Extension. | */ - uint8_t version; + uint8_t cte_type; /** - * @brief The manufacturer ID of the remote device. + * @brief Reserved for future use. * @details - * Refer to Bluetooth SIG Assigned Number - * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + * | value | description | + * |:--------- |:------------------------------------------------------- | + * | 0x00 | Data Complete. | + * | 0x01 | Data incomplete, more data to come. | + * | 0x02 | Data incomplete, data truncated, no more to come. | */ - uint16_t company_id; + uint8_t data_status; /** - * @brief The subversion of Link Layer. + * @brief Length of Periodic Advertising data(in bytes). + * @details Valid range is 0 - 247. */ - uint16_t subversion; + uint8_t len; /** - * @brief LE feature supported in the remote device. - * @details - * Refer to Core Spec Vol 6, Part B 4.6 FEATURE SUPPORT. + * @brief Periodic Advertising data. */ - uint8_t features[BLE_GAP_REM_FEATURE_SIZE]; -} st_ble_gap_dev_info_evt_t; - -/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_COMP : st_ble_gap_conn_upd_evt_t */ + uint8_t * p_data; +} st_ble_gap_perd_adv_rept_t; /******************************************************************************************************************//** - * @struct st_ble_gap_conn_upd_evt_t - * @brief This structure notifies that connection parameters has been updated. + * @struct st_ble_gap_adv_rept_evt_t + * @brief Advertising report. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the connection whose parameters has been updated. - */ - uint16_t conn_hdl; - - /** - * @brief Updated Connection Interval. + * @brief Data type. * @details - * Valid range is 0x0006 - 0x0C80.\n - * Time(ms) = conn_intv * 1.25. + * | value | description | + * |:-------------------- |:---------------------------------- | + * | 0x00 | Advertising Report. | + * | 0x01 | Extended Advertising Report. | + * | 0x02 | Periodic Advertising Report. | + * + * If the BLE Protocol Stack library type is "extended", + * the adv_rpt_type field in a Legacy Advertising Report event is 0x01. */ - uint16_t conn_intv; + uint8_t adv_rpt_type; /** - * @brief Updated slave latency. - * @details - * Valid range is 0x0000 - 0x01F3. + * @brief Advertising Report. */ - uint16_t conn_latency; + union + { + /** + * @brief Advertising Report. + */ + st_ble_gap_adv_rept_t * p_adv_rpt; + + /** + * @brief Extended Advertising Report. + */ + st_ble_gap_ext_adv_rept_t * p_ext_adv_rpt; + + /** + * @brief Periodic Advertising Report. + */ + st_ble_gap_perd_adv_rept_t * p_per_adv_rpt; + } param; +} st_ble_gap_adv_rept_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_OFF : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_set_evt_t + * @brief Advertising handle. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Updated supervision timeout. - * @details - * Valid range is 0x000A - 0x0C80.\n - * Time(ms) = sup_to * 10. + * @brief Advertising handle specifying the advertising set configured advertising parameters. */ - uint16_t sup_to; -} st_ble_gap_conn_upd_evt_t; + uint8_t adv_hdl; +} st_ble_gap_adv_set_evt_t; -/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_REQ : st_ble_gap_conn_upd_req_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_OFF : st_ble_gap_adv_off_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_conn_upd_req_evt_t - * @brief This structure notifies that a request for connection parameters update has been received. + * @struct st_ble_gap_adv_off_evt_t + * @brief Information about the advertising set which stops advertising. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the link that was requested to update connection parameters. + * @brief Advertising handle identifying the advertising set which has stopped advertising. + * @details Valid range is 0x00 - 0x03. */ - uint16_t conn_hdl; + uint8_t adv_hdl; /** - * @brief Minimum connection interval. + * @brief The reason for stopping advertising. * @details - * Valid range is 0x0006 - 0x0C80.\n - * Time(ms) = conn_intv_min * 1.25. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x01 + * Advertising has been stopped by R_BLE_GAP_StopAdv(). + *
0x02 + * Because the duration specified by R_BLE_GAP_StartAdv() was expired, + * advertising has terminated. + *
0x03 + * Because the max_extd_adv_evts parameter specified by R_BLE_GAP_StartAdv() was reached, + * advertising has terminated. + *
0x04 + * Because the connection was established with the remote device, advertising has terminated. + *
*/ - uint16_t conn_intv_min; + uint8_t reason; /** - * @brief Maximum connection interval. - * @details - * Valid range is 0x0006 - 0x0C80.\n - * Time(ms) = conn_intv_max * 1.25. + * @brief Connection handle. + * @details If the reason field is 0x04, this field indicates connection handle identifying + * the remote device connected with local device. + * If other reasons, ignore this field. */ - uint16_t conn_intv_max; + uint16_t conn_hdl; /** - * @brief Slave latency. - * @details - * Valid range is 0x0000 - 0x01F3. + * @brief The number of the advertising event that has been received until advertising has terminated. + * @details If max_extd_adv_evts by R_BLE_GAP_StartAdv() is not 0, this parameter is valid. */ - uint16_t conn_latency; + uint8_t num_comp_ext_adv_evts; +} st_ble_gap_adv_off_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_DATA_UPD_COMP : st_ble_gap_adv_data_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_data_evt_t + * @brief This structure notifies that advertising data has been set to Controller by R_BLE_GAP_SetAdvSresData(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Supervision timeout. + * @brief Advertising handle identifying the advertising set to + * which advertising data/scan response data/periodic advertising data is set. + */ + uint8_t adv_hdl; + + /** + * @brief Type of the data set to the advertising set. * @details - * Valid range is 0x000A - 0x0C80.\n - * Time(ms) = sup_to * 10 + * | value | description | + * |:------------------------------------ |:--------------------------- | + * | BLE_GAP_ADV_DATA_MODE(0x00) | Advertising data | + * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data | + * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data | */ - uint16_t sup_to; -} st_ble_gap_conn_upd_req_evt_t; + uint8_t data_type; +} st_ble_gap_adv_data_evt_t; -/* Event Code : RBLE_GAP_EVENT_CONN_PARAM_UPD_RSP : st_ble_gap_conn_hdl_evt_t */ -/* Event Code : BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_SET_REMOVE_COMP : st_ble_gap_rem_adv_set_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_conn_hdl_evt_t - * @brief This structure notifies that a GAP Event that includes only connection handle has occurred. + * @struct st_ble_gap_rem_adv_set_evt_t + * @brief This structure notifies that an advertising set has been removed. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle. + * @brief This field indicates that the advertising set has been removed or cleared. + * @details + * | value | description | + * |:-------- |:--------------------------------------- | + * | 0x01 | The advertising set has been removed. | + * | 0x02 | The advertising set has been cleared. | */ - uint16_t conn_hdl; -} st_ble_gap_conn_hdl_evt_t; + uint8_t remove_op; -/* Event Code : BLE_GAP_EVENT_DATA_LEN_CHG : st_ble_gap_data_len_chg_evt_t */ + /** + * @brief Advertising handle identifying the advertising set which has been removed. + * @details If the advertising set has been cleared, this field is ignored. + */ + uint8_t adv_hdl; +} st_ble_gap_rem_adv_set_evt_t; + +/* Event Code : BLE_GAP_EVENT_SCAN_ON : none */ +/* Event Code : BLE_GAP_EVENT_SCAN_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_CONN_IND : st_ble_gap_conn_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_data_len_chg_evt_t - * @brief This structure notifies that the packet data length has been updated. + * @struct st_ble_gap_conn_evt_t + * @brief This structure notifies that a link has been established. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the link that updated Data Length. + * @brief Connection handle identifying the created link. */ uint16_t conn_hdl; /** - * @brief Updated transmission packet size(in bytes). + * @brief The role of the link. * @details - * Valid range is 0x001B - 0x00FB. + * | value | description | + * |:-------- |:-------------- | + * | 0x00 | Master | + * | 0x01 | Slave | */ - uint16_t tx_octets; + uint8_t role; /** - * @brief Updated transmission time(us). + * @brief Address type of the remote device. * @details - * Valid range is 0x0148 - 0x4290. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x00Public Address
0x01Random Address
0x02Public Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + *
0x03Random Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + * 		+ *
*/ - uint16_t tx_time; + uint8_t remote_addr_type; /** - * @brief Updated receive packet size(in bytes). - * @details - * Valid range is 0x001B - 0x00FB. + * @brief Address of the remote device. + * @note The BD address setting format is little endian. */ - uint16_t rx_octets; + uint8_t remote_addr[BLE_BD_ADDR_LEN]; /** - * @brief Updated receive time(us). + * @brief Resolvable private address that local device used in connection procedure. * @details - * Valid range is 0x0148 - 0x4290. + * The local device address used in creating the link when the address type was set to + * BLE_GAP_ADDR_RPA_ID_PUBLIC or BLE_GAP_ADDR_RPA_ID_RANDOM by R_BLE_GAP_SetAdvParam() or + * R_BLE_GAP_CreateConn(). + * If the address type was set to other than BLE_GAP_ADDR_RPA_ID_PUBLIC and + * BLE_GAP_ADDR_RPA_ID_RANDOM, this field is set to all-zero. + * @note The BD address setting format is little endian. */ - uint16_t rx_time; -} st_ble_gap_data_len_chg_evt_t; - -/* Event Code : BLE_GAP_EVENT_RSLV_LIST_CONF_COMP : st_ble_gap_rslv_list_conf_evt_t */ - -/* Event Code : BLE_GAP_EVENT_RPA_EN_COMP : none */ -/* Event Code : BLE_GAP_EVENT_SET_RPA_TO_COMP : none */ -/* Event Code : BLE_GAP_EVENT_RD_RPA_COMP : st_ble_gap_rd_rpa_evt_t */ + uint8_t local_rpa[BLE_BD_ADDR_LEN]; -/******************************************************************************************************************//** - * @struct st_ble_gap_rd_rpa_evt_t - * @brief This structure notifies that the local resolvable private address has been retrieved by R_BLE_GAP_ReadRpa(). - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief The resolvable private address of local device. + * @brief Resolvable private address that the remote device used in connection procedure. + * @details + * This field indicates the remote resolvable private address when remote_addr_type is 0x02 or 0x03. + * If remote_addr_type is other than 0x02 and 0x03, this field is set to all-zero. + * @note The BD address setting format is little endian. */ - st_ble_dev_addr_t addr; -} st_ble_gap_rd_rpa_evt_t; + uint8_t remote_rpa[BLE_BD_ADDR_LEN]; -/* Event Code : BLE_GAP_EVENT_PHY_UPD : st_ble_gap_phy_upd_evt_t */ + /** + * @brief Connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; -/******************************************************************************************************************//** - * @struct st_ble_gap_phy_upd_evt_t - * @brief This structure notifies that PHY for a connection has been updated. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the link that has been updated. + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. */ - uint16_t conn_hdl; + uint16_t conn_latency; /** - * @brief Transmitter PHY. + * @brief Supervision timeout. * @details - * | value | description | - * |:-----------|:------------------------------------------------------------ | - * | 0x01 | The transmitter PHY has been updated to 1M PHY. | - * | 0x02 | The transmitter PHY has been updated to 2M PHY. | - * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + * Valid range is 0x000A - 0x0C80.Time(ms) = sup_to * 10. */ - uint8_t tx_phy; + uint16_t sup_to; /** - * @brief Receiver PHY. + * @brief Master_Clock_Accuracy. * @details - * | value | description | - * |:-----------|:------------------------------------------------------------ | - * | 0x01 | The receiver PHY has been updated to 1M PHY. | - * | 0x02 | The receiver PHY has been updated to 2M PHY. | - * | 0x03 | The receiver PHY has been updated to Coded PHY. | + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | */ - uint8_t rx_phy; -} st_ble_gap_phy_upd_evt_t; + uint8_t clk_acc; +} st_ble_gap_conn_evt_t; -/* Event Code : BLE_GAP_EVENT_PHY_RD_COMP : st_ble_gap_phy_rd_evt_t */ +/* Event Code : BLE_GAP_EVENT_DISCONN_IND : st_ble_gap_disconn_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_phy_rd_evt_t - * @brief This structure notifies that the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(). + * @struct st_ble_gap_disconn_evt_t + * @brief This structure notifies that a link has been disconnected. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the link that has been retrieved the PHY settings. + * @brief Connection handle identifying the link disconnected. */ uint16_t conn_hdl; /** - * @brief Transmitter PHY. + * @brief The reason for disconnection. * @details - * | value | description | - * |:-----------|:------------------------------------------------------------ | - * | 0x01 | The transmitter PHY has been updated to 1M PHY. | - * | 0x02 | The transmitter PHY has been updated to 2M PHY. | - * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + * Refer Core Specification Vol.2 Part D ,"2 Error Code Descriptions". */ - uint8_t tx_phy; + uint8_t reason; +} st_ble_gap_disconn_evt_t; - /** - * @brief Receiver PHY. - * @details - * | value | description | - * |:-----------|:------------------------------------------------------------ | - * | 0x01 | The receiver PHY has been updated to 1M PHY. | - * | 0x02 | The receiver PHY has been updated to 2M PHY. | - * | 0x03 | The receiver PHY has been updated to Coded PHY. | - */ - uint8_t rx_phy; -} st_ble_gap_phy_rd_evt_t; +/* Event Code : BLE_GAP_EVENT_CONN_CANCEL_COMP : none */ -/* Event Code : BLE_GAP_EVENT_PHY_SET_COMP : st_ble_gap_conn_hdl_evt_t */ -/* Event Code : BLE_GAP_EVENT_SCAN_REQ_RECV : st_ble_gap_scan_req_recv_evt_t */ +/* Event Code : BLE_GAP_EVENT_WHITE_LIST_CONF_COMP : st_ble_gap_white_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RAND_ADDR_SET_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_CH_MAP_RD_COMP : st_ble_gap_rd_ch_map_evt_t */ +/* Read Channel MAP */ /******************************************************************************************************************//** - * @struct st_ble_gap_scan_req_recv_evt_t - * @brief This structure notifies that a Scan Request packet has been received from a Scanner. + * @struct st_ble_gap_rd_ch_map_evt_t + * @brief This structure notifies that Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Advertising handle identifying the advertising set that has received the Scan Request. + * @brief Connection handle identifying the link whose Channel Map was retrieved. */ - uint8_t adv_hdl; + uint16_t conn_hdl; /** - * @brief Address type of the Scanner. - * @details - * | value | description | - * |:-----------|:-------------------------------------------------------------- | - * | 0x00 | Public Address. | - * | 0x01 | Random Address. | - * | 0x02 | Public Identity Address which could be resolved in Controller. | - * | 0x03 | Random Identity Address which could be resolved in Controller. | + * @brief Channel Map. */ - uint8_t scanner_addr_type; + uint8_t ch_map[BLE_GAP_CH_MAP_SIZE]; +} st_ble_gap_rd_ch_map_evt_t; - /** - * @brief Address of the Scanner. - * @note The BD address setting format is little endian. - */ - uint8_t scanner_addr[BLE_BD_ADDR_LEN]; -} st_ble_gap_scan_req_recv_evt_t; +/* Event Code : BLE_GAP_EVENT_CH_MAP_SET_COMP : none */ -/* Event Code : BLE_GAP_EVENT_SYNC_EST : st_ble_gap_sync_est_evt_t */ +/* Event Code : BLE_GAP_EVENT_RSSI_RD_COMP : st_ble_gap_rd_rssi_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_sync_est_evt_t - * @brief This structure notifies that a Periodic sync has been established. + * @struct st_ble_gap_rd_rssi_evt_t + * @brief This structure notifies that RSSI has been retrieved by R_BLE_GAP_ReadRssi(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Sync handle identifying the Periodic Sync that has been established. + * @brief Connection handle identifying the link whose RSSI was retrieved. */ - uint16_t sync_hdl; + uint16_t conn_hdl; /** - * @brief Advertising SID identifying the advertising set that has established the Periodic Sync. + * @brief RSSI(in dBm). + * @details + * Valid range is -127 < rssi < 20 and 127.\n + * If this field is 127, it indicates that RSSI could not be retrieved. */ - uint8_t adv_sid; + int8_t rssi; +} st_ble_gap_rd_rssi_evt_t; + +/* Event Code : BLE_GAP_EVENT_GET_REM_DEV_INFO : st_ble_gap_dev_info_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_dev_info_evt_t + * @brief This structure notifies that information about remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Address type of the advertiser. + * @brief Connection handle identifying the remote device whose information has been retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Information about the remote device. This field is a bitwise OR of the following values. * @details - * | value | description | - * |:-----------|:-------------------------------------------------------------- | - * | 0x00 | Public Address. | - * | 0x01 | Random Address. | - * | 0x02 | Public Identity Address which could be resolved in Controller. | - * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | Bit Number | description | + * |:-------------------|:------------------------------- | + * | bit0 | Address | + * | bit1 | Version, company_id, subversion | + * | bit2 | Feature | + * | All other bits | Reserved for future use | */ - uint8_t adv_addr_type; + uint8_t get_status; /** - * @brief Address of the advertiser. - * @note The BD address setting format is little endian. + * @brief Address of the remote device. */ - uint8_t * p_adv_addr; + st_ble_dev_addr_t addr; /** - * @brief Advertising PHY. + * @brief The version of Link Layer of the remote device. * @details - * | value | description | - * |:-----------|:---------------------------- | - * | 0x01 | Advertiser PHY is 1M PHY. | - * | 0x02 | Advertiser PHY is 2M PHY. | - * | 0x03 | Advertiser PHY is Coded PHY. | + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. */ - uint8_t adv_phy; + uint8_t version; /** - * @brief Periodic Advertising Interval. + * @brief The manufacturer ID of the remote device. * @details - * Valid range is 0x0006 - 0xFFFF.\n - * Time(ms) = perd_adv_intv * 1.25. + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. */ - uint16_t perd_adv_intv; + uint16_t company_id; /** - * @brief Advertiser Clock Accuracy. + * @brief The subversion of Link Layer. + */ + uint16_t subversion; + + /** + * @brief LE feature supported in the remote device. * @details - * | value | description | - * |:---------|:--------------------------- | - * | 0x00 | 500ppm | - * | 0x01 | 250ppm | - * | 0x02 | 150ppm | - * | 0x03 | 100ppm | - * | 0x04 | 75ppm | - * | 0x05 | 50ppm | - * | 0x06 | 30ppm | - * | 0x07 | 20ppm | + * Refer to Core Spec Vol 6, Part B 4.6 FEATURE SUPPORT. */ - uint8_t adv_clk_acc; -} st_ble_gap_sync_est_evt_t; + uint8_t features[BLE_GAP_REM_FEATURE_SIZE]; +} st_ble_gap_dev_info_evt_t; -/* Event Code : BLE_GAP_EVENT_SYNC_TERM : st_ble_gap_sync_hdl_evt_t */ -/* Event Code : BLE_GAP_EVENT_SYNC_LOST : st_ble_gap_sync_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_COMP : st_ble_gap_conn_upd_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_sync_hdl_evt_t - * @brief This structure notifies that a GAP Event that includes only sync handle has occurred. + * @struct st_ble_gap_conn_upd_evt_t + * @brief This structure notifies that connection parameters has been updated. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Sync handle. + * @brief Connection handle identifying the connection whose parameters has been updated. */ - uint16_t sync_hdl; -} st_ble_gap_sync_hdl_evt_t; + uint16_t conn_hdl; -/* Event Code : BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP : none */ -/* Event Code : BLE_GAP_EVENT_PERD_LIST_CONF_COMP : st_ble_gap_perd_list_conf_evt_t */ + /** + * @brief Updated Connection Interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; -/******************************************************************************************************************//** - * @struct st_ble_gap_white_list_conf_evt_t - * @brief This structure notifies that White List has been configured. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief The operation for White List. + * @brief Updated slave latency. * @details - * | value | description | - * |:---------|:---------------------------------------- | - * | 0x01 | A device was added to White List. | - * | 0x02 | A device was deleted from White List. | - * | 0x03 | White List was cleared. | + * Valid range is 0x0000 - 0x01F3. */ - uint8_t op_code; + uint16_t conn_latency; /** - * @brief The number or devices which have been added to or deleted from White List. + * @brief Updated supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10. */ - uint8_t num; -} st_ble_gap_white_list_conf_evt_t; + uint16_t sup_to; +} st_ble_gap_conn_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_REQ : st_ble_gap_conn_upd_req_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_rslv_list_conf_evt_t - * @brief This structure notifies that Resolving List has been configured. + * @struct st_ble_gap_conn_upd_req_evt_t + * @brief This structure notifies that a request for connection parameters update has been received. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief The operation for Resolving List. + * @brief Connection handle identifying the link that was requested to update connection parameters. + */ + uint16_t conn_hdl; + + /** + * @brief Minimum connection interval. * @details - * | value | description | - * |:---------|:-------------------------------------------- | - * | 0x01 | A device was added to Resolving List. | - * | 0x02 | A device was deleted from Resolving List. | - * | 0x03 | Resolving List was cleared. | + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_min * 1.25. */ - uint8_t op_code; + uint16_t conn_intv_min; /** - * @brief The number or devices which have been added to or deleted from Resolving List. + * @brief Maximum connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_max * 1.25. */ - uint8_t num; -} st_ble_gap_rslv_list_conf_evt_t; + uint16_t conn_intv_max; -/******************************************************************************************************************//** - * @struct st_ble_gap_perd_list_conf_evt_t - * @brief This structure notifies that Periodic Advertiser List has been configured. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief The operation for Periodic Advertiser List. + * @brief Slave latency. * @details - * | value | description | - * |:---------|:------------------------------------------------------ | - * | 0x01 | A device was added to Periodic Advertiser List. | - * | 0x02 | A device was deleted from Periodic Advertiser List. | - * | 0x03 | Periodic Advertiser List was cleared. | + * Valid range is 0x0000 - 0x01F3. */ - uint8_t op_code; + uint16_t conn_latency; /** - * @brief The number or devices which have been added to or deleted from Periodic Advertiser List. + * @brief Supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10 */ - uint8_t num; -} st_ble_gap_perd_list_conf_evt_t; + uint16_t sup_to; +} st_ble_gap_conn_upd_req_evt_t; -/* Event Code : BLE_GAP_EVENT_PRIV_MODE_SET_COMP : st_ble_gap_set_priv_mode_evt_t */ +/* Event Code : RBLE_GAP_EVENT_CONN_PARAM_UPD_RSP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED : st_ble_gap_conn_hdl_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_set_priv_mode_evt_t - * @brief This structure notifies that Privacy Mode has been configured. + * @struct st_ble_gap_conn_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only connection handle has occurred. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief The number or devices which have been set privacy mode. + * @brief Connection handle. */ - uint8_t num; -} st_ble_gap_set_priv_mode_evt_t; + uint16_t conn_hdl; +} st_ble_gap_conn_hdl_evt_t; -/* Event Code : BLE_GAP_EVENT_PAIRING_REQ : st_ble_gap_pairing_req_evt_t */ +/* Event Code : BLE_GAP_EVENT_DATA_LEN_CHG : st_ble_gap_data_len_chg_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_pairing_req_evt_t - * @brief This structure notifies that a pairing request from a remote device has been received. + * @struct st_ble_gap_data_len_chg_evt_t + * @brief This structure notifies that the packet data length has been updated. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device that sent the pairing request. + * @brief Connection handle identifying the link that updated Data Length. */ uint16_t conn_hdl; /** - * @brief The address of the remote device. + * @brief Updated transmission packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. */ - st_ble_dev_addr_t bd_addr; + uint16_t tx_octets; /** - * @brief The Pairing parameters of the remote device. + * @brief Updated transmission time(us). + * @details + * Valid range is 0x0148 - 0x4290. */ - st_ble_gap_auth_info_t auth_info; -} st_ble_gap_pairing_req_evt_t; - -/* Event Code : BLE_GAP_EVENT_PASSKEY_ENTRY_REQ : st_ble_gap_conn_hdl_evt_t */ - -/* Event Code : BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ : st_ble_gap_passkey_display_evt_t */ + uint16_t tx_time; -/******************************************************************************************************************//** - * @struct st_ble_gap_passkey_display_evt_t - * @brief This structure notifies that a request for Passkey display in pairing has been received. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the remote device that requested Passkey display. + * @brief Updated receive packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. */ - uint16_t conn_hdl; + uint16_t rx_octets; /** - * @brief Passkey. - * @details This field is a 6 digit decimal number(000000-999999). + * @brief Updated receive time(us). + * @details + * Valid range is 0x0148 - 0x4290. */ - uint32_t passkey; -} st_ble_gap_passkey_display_evt_t; + uint16_t rx_time; +} st_ble_gap_data_len_chg_evt_t; -/* Event Code : BLE_GAP_EVENT_NUM_COMP_REQ : st_ble_gap_num_comp_evt_t */ +/* Event Code : BLE_GAP_EVENT_RSLV_LIST_CONF_COMP : st_ble_gap_rslv_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RPA_EN_COMP : none */ +/* Event Code : BLE_GAP_EVENT_SET_RPA_TO_COMP : none */ +/* Event Code : BLE_GAP_EVENT_RD_RPA_COMP : st_ble_gap_rd_rpa_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_num_comp_evt_t - * @brief This structure notifies that a request for Numeric Comparison in pairing has been received. + * @struct st_ble_gap_rd_rpa_evt_t + * @brief This structure notifies that the local resolvable private address has been retrieved by R_BLE_GAP_ReadRpa(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device that requested Numeric Comparison. - */ - uint16_t conn_hdl; - - /** - * @brief The number to be confirmed in Numeric Comparison. - * @details This field is a 6 digit decimal number(000000-999999). + * @brief The resolvable private address of local device. */ - uint32_t numeric; -} st_ble_gap_num_comp_evt_t; + st_ble_dev_addr_t addr; +} st_ble_gap_rd_rpa_evt_t; -/* Event Code : BLE_GAP_EVENT_KEY_PRESS_NTF : st_ble_gap_key_press_ntf_evt_t */ +/* Event Code : BLE_GAP_EVENT_PHY_UPD : st_ble_gap_phy_upd_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_key_press_ntf_evt_t - * @brief This structure notifies that the remote device has input a key in Passkey Entry + * @struct st_ble_gap_phy_upd_evt_t + * @brief This structure notifies that PHY for a connection has been updated. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device that input a key. + * @brief Connection handle identifying the link that has been updated. */ uint16_t conn_hdl; /** - * @brief Type of the key that the remote device input. + * @brief Transmitter PHY. * @details - * | value | description | - * |:---------|:----------------------------- | - * | 0x00 | Passkey entry started. | - * | 0x01 | Passkey digit entered. | - * | 0x02 | Passkey digit erased. | - * | 0x03 | Passkey cleared. | - * | 0x04 | Passkey entry completed. | + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | */ - uint8_t key_type; -} st_ble_gap_key_press_ntf_evt_t; + uint8_t tx_phy; -/* Event Code : BLE_GAP_EVENT_PAIRING_COMP : st_ble_gap_pairing_info_evt_t */ + /** + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | + */ + uint8_t rx_phy; +} st_ble_gap_phy_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_RD_COMP : st_ble_gap_phy_rd_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_pairing_info_evt_t - * @brief This structure notifies that the pairing has completed. + * @struct st_ble_gap_phy_rd_evt_t + * @brief This structure notifies that the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device that the pairing has been done with. + * @brief Connection handle identifying the link that has been retrieved the PHY settings. */ uint16_t conn_hdl; /** - * @brief Address of the remote device. + * @brief Transmitter PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | */ - st_ble_dev_addr_t bd_addr; + uint8_t tx_phy; /** - * @brief Key information exchanged in pairing. - * @details If local device supports bonding, store the information in non-volatile memory - * in order to set it to host stack after power re-supply. + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | */ - st_ble_gap_auth_info_t auth_info; -} st_ble_gap_pairing_info_evt_t; + uint8_t rx_phy; +} st_ble_gap_phy_rd_evt_t; -/* Event Code : BLE_GAP_EVENT_ENC_CHG : st_ble_gap_enc_chg_evt_t */ +/* Event Code : BLE_GAP_EVENT_PHY_SET_COMP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SCAN_REQ_RECV : st_ble_gap_scan_req_recv_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_enc_chg_evt_t - * @brief This structure notifies that the encryption status of a link has been changed. + * @struct st_ble_gap_scan_req_recv_evt_t + * @brief This structure notifies that a Scan Request packet has been received from a Scanner. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the link that has been changed. + * @brief Advertising handle identifying the advertising set that has received the Scan Request. */ - uint16_t conn_hdl; + uint8_t adv_hdl; /** - * @brief Encryption Status. + * @brief Address type of the Scanner. * @details - * | value | description | - * |:---------|:-------------------------------------------------------- | - * | 0x00 | Encryption OFF. | - * | 0x01 | Encryption ON. | - * | 0x03 | Encryption updated by Encryption Key Refresh Completed. | + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | */ - uint8_t enc_status; -} st_ble_gap_enc_chg_evt_t; + uint8_t scanner_addr_type; -/* Event Code : BLE_GAP_EVENT_PEER_KEY_INFO : st_ble_gap_peer_key_info_evt_t */ + /** + * @brief Address of the Scanner. + * @note The BD address setting format is little endian. + */ + uint8_t scanner_addr[BLE_BD_ADDR_LEN]; +} st_ble_gap_scan_req_recv_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_EST : st_ble_gap_sync_est_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_peer_key_info_evt_t - * @brief This structure notifies that the remote device has distributed the keys. + * @struct st_ble_gap_sync_est_evt_t + * @brief This structure notifies that a Periodic sync has been established. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device that has distributed the keys. + * @brief Sync handle identifying the Periodic Sync that has been established. */ - uint16_t conn_hdl; + uint16_t sync_hdl; /** - * @brief Address of the remote device. + * @brief Advertising SID identifying the advertising set that has established the Periodic Sync. */ - st_ble_dev_addr_t bd_addr; + uint8_t adv_sid; /** - * @brief Distributed keys. + * @brief Address type of the advertiser. * @details - * If local device supports bonding, store the keys in non-volatile memory and - * at power re-supply set to the host stack by R_BLE_GAP_SetBondInfo(). + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | */ - st_ble_gap_key_ex_param_t key_ex_param; -} st_ble_gap_peer_key_info_evt_t; - -/* Event Code : BLE_GAP_EVENT_EX_KEY_REQ : st_ble_gap_conn_hdl_evt_t */ + uint8_t adv_addr_type; -/* Event Code : BLE_GAP_EVENT_LTK_REQ : st_ble_gap_ltk_req_evt_t */ + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_adv_addr; -/******************************************************************************************************************//** - * @struct st_ble_gap_ltk_req_evt_t - * @brief This structure notifies that a LTK request from a remote device has been received. - **********************************************************************************************************************/ -typedef struct -{ /** - * @brief Connection handle identifying the remote device which requests for the LTK. + * @brief Advertising PHY. + * @details + * | value | description | + * |:-----------|:---------------------------- | + * | 0x01 | Advertiser PHY is 1M PHY. | + * | 0x02 | Advertiser PHY is 2M PHY. | + * | 0x03 | Advertiser PHY is Coded PHY. | */ - uint16_t conn_hdl; + uint8_t adv_phy; /** - * @brief Ediv. + * @brief Periodic Advertising Interval. + * @details + * Valid range is 0x0006 - 0xFFFF.\n + * Time(ms) = perd_adv_intv * 1.25. */ - uint16_t ediv; + uint16_t perd_adv_intv; /** - * @brief Rand. + * @brief Advertiser Clock Accuracy. + * @details + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | */ - uint8_t * p_peer_rand; -} st_ble_gap_ltk_req_evt_t; + uint8_t adv_clk_acc; +} st_ble_gap_sync_est_evt_t; -/* Event Code : BLE_GAP_EVENT_LTK_RSP_COMP : st_ble_gap_ltk_req_evt_t */ +/* Event Code : BLE_GAP_EVENT_SYNC_TERM : st_ble_gap_sync_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SYNC_LOST : st_ble_gap_sync_hdl_evt_t */ /******************************************************************************************************************//** - * @struct st_ble_gap_ltk_rsp_evt_t - * @brief This structure notifies that local device has replied to the LTK request from the remote device. + * @struct st_ble_gap_sync_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only sync handle has occurred. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Connection handle identifying the remote device to be sent the response to the LTK request. + * @brief Sync handle. */ - uint16_t conn_hdl; + uint16_t sync_hdl; +} st_ble_gap_sync_hdl_evt_t; - /** - * @brief The response to the LTK request. - * @details - * | value | description | - * |:---------|:----------------------------------------------------------------------- | - * | 0x00 | Local device replied with the stored LTK. | - * | 0x01 | Local device rejected the LTK request, because the LTK was not found. | +/* Event Code : BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP : none */ +/* Event Code : BLE_GAP_EVENT_PERD_LIST_CONF_COMP : st_ble_gap_perd_list_conf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_white_list_conf_evt_t + * @brief This structure notifies that White List has been configured. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief The operation for White List. + * @details + * | value | description | + * |:---------|:---------------------------------------- | + * | 0x01 | A device was added to White List. | + * | 0x02 | A device was deleted from White List. | + * | 0x03 | White List was cleared. | */ - uint8_t response; -} st_ble_gap_ltk_rsp_evt_t; + uint8_t op_code; -/* Event Code : BLE_GAP_EVENT_SC_OOB_CREATE_COMP : st_ble_gap_sc_oob_data_evt_t */ + /** + * @brief The number or devices which have been added to or deleted from White List. + */ + uint8_t num; +} st_ble_gap_white_list_conf_evt_t; /******************************************************************************************************************//** - * @struct st_ble_gap_sc_oob_data_evt_t - * @brief This structure notifies that OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + * @struct st_ble_gap_rslv_list_conf_evt_t + * @brief This structure notifies that Resolving List has been configured. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Confirmation value(16 bytes) of OOB Data. + * @brief The operation for Resolving List. + * @details + * | value | description | + * |:---------|:-------------------------------------------- | + * | 0x01 | A device was added to Resolving List. | + * | 0x02 | A device was deleted from Resolving List. | + * | 0x03 | Resolving List was cleared. | */ - uint8_t * p_sc_oob_conf; + uint8_t op_code; /** - * @brief Rand(16bytes) of OOB Data. + * @brief The number or devices which have been added to or deleted from Resolving List. */ - uint8_t * p_sc_oob_rand; -} st_ble_gap_sc_oob_data_evt_t; + uint8_t num; +} st_ble_gap_rslv_list_conf_evt_t; /******************************************************************************************************************//** - * @struct st_ble_gap_bond_info_t - * @brief Bonding information used in R_BLE_GAP_SetBondInfo(). + * @struct st_ble_gap_perd_list_conf_evt_t + * @brief This structure notifies that Periodic Advertiser List has been configured. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** - * @brief Address of the device which exchanged the keys. + * @brief The operation for Periodic Advertiser List. + * @details + * | value | description | + * |:---------|:------------------------------------------------------ | + * | 0x01 | A device was added to Periodic Advertiser List. | + * | 0x02 | A device was deleted from Periodic Advertiser List. | + * | 0x03 | Periodic Advertiser List was cleared. | */ - st_ble_dev_addr_t * p_addr; + uint8_t op_code; /** - * @brief Information about the keys. + * @brief The number or devices which have been added to or deleted from Periodic Advertiser List. */ - st_ble_gap_auth_info_t * p_auth_info; + uint8_t num; +} st_ble_gap_perd_list_conf_evt_t; +/* Event Code : BLE_GAP_EVENT_PRIV_MODE_SET_COMP : st_ble_gap_set_priv_mode_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_priv_mode_evt_t + * @brief This structure notifies that Privacy Mode has been configured. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ /** - * @brief Keys distributed from the remote device in paring. + * @brief The number or devices which have been set privacy mode. + */ + uint8_t num; +} st_ble_gap_set_priv_mode_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_REQ : st_ble_gap_pairing_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_req_evt_t + * @brief This structure notifies that a pairing request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that sent the pairing request. + */ + uint16_t conn_hdl; + + /** + * @brief The address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief The Pairing parameters of the remote device. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_PASSKEY_ENTRY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ : st_ble_gap_passkey_display_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_passkey_display_evt_t + * @brief This structure notifies that a request for Passkey display in pairing has been received. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that requested Passkey display. + */ + uint16_t conn_hdl; + + /** + * @brief Passkey. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t passkey; +} st_ble_gap_passkey_display_evt_t; + +/* Event Code : BLE_GAP_EVENT_NUM_COMP_REQ : st_ble_gap_num_comp_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_num_comp_evt_t + * @brief This structure notifies that a request for Numeric Comparison in pairing has been received. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that requested Numeric Comparison. + */ + uint16_t conn_hdl; + + /** + * @brief The number to be confirmed in Numeric Comparison. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t numeric; +} st_ble_gap_num_comp_evt_t; + +/* Event Code : BLE_GAP_EVENT_KEY_PRESS_NTF : st_ble_gap_key_press_ntf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_press_ntf_evt_t + * @brief This structure notifies that the remote device has input a key in Passkey Entry + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that input a key. + */ + uint16_t conn_hdl; + + /** + * @brief Type of the key that the remote device input. + * @details + * | value | description | + * |:---------|:----------------------------- | + * | 0x00 | Passkey entry started. | + * | 0x01 | Passkey digit entered. | + * | 0x02 | Passkey digit erased. | + * | 0x03 | Passkey cleared. | + * | 0x04 | Passkey entry completed. | + */ + uint8_t key_type; +} st_ble_gap_key_press_ntf_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_COMP : st_ble_gap_pairing_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_info_evt_t + * @brief This structure notifies that the pairing has completed. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that the pairing has been done with. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Key information exchanged in pairing. + * @details If local device supports bonding, store the information in non-volatile memory + * in order to set it to host stack after power re-supply. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_ENC_CHG : st_ble_gap_enc_chg_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_enc_chg_evt_t + * @brief This structure notifies that the encryption status of a link has been changed. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the link that has been changed. + */ + uint16_t conn_hdl; + + /** + * @brief Encryption Status. + * @details + * | value | description | + * |:---------|:-------------------------------------------------------- | + * | 0x00 | Encryption OFF. | + * | 0x01 | Encryption ON. | + * | 0x03 | Encryption updated by Encryption Key Refresh Completed. | + */ + uint8_t enc_status; +} st_ble_gap_enc_chg_evt_t; + +/* Event Code : BLE_GAP_EVENT_PEER_KEY_INFO : st_ble_gap_peer_key_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_peer_key_info_evt_t + * @brief This structure notifies that the remote device has distributed the keys. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device that has distributed the keys. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Distributed keys. + * @details + * If local device supports bonding, store the keys in non-volatile memory and + * at power re-supply set to the host stack by R_BLE_GAP_SetBondInfo(). + */ + st_ble_gap_key_ex_param_t key_ex_param; +} st_ble_gap_peer_key_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_EX_KEY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_LTK_REQ : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_req_evt_t + * @brief This structure notifies that a LTK request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device which requests for the LTK. + */ + uint16_t conn_hdl; + + /** + * @brief Ediv. + */ + uint16_t ediv; + + /** + * @brief Rand. + */ + uint8_t * p_peer_rand; +} st_ble_gap_ltk_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_LTK_RSP_COMP : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_rsp_evt_t + * @brief This structure notifies that local device has replied to the LTK request from the remote device. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Connection handle identifying the remote device to be sent the response to the LTK request. + */ + uint16_t conn_hdl; + + /** + * @brief The response to the LTK request. + * @details + * | value | description | + * |:---------|:----------------------------------------------------------------------- | + * | 0x00 | Local device replied with the stored LTK. | + * | 0x01 | Local device rejected the LTK request, because the LTK was not found. | + */ + uint8_t response; +} st_ble_gap_ltk_rsp_evt_t; + +/* Event Code : BLE_GAP_EVENT_SC_OOB_CREATE_COMP : st_ble_gap_sc_oob_data_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sc_oob_data_evt_t + * @brief This structure notifies that OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Confirmation value(16 bytes) of OOB Data. + */ + uint8_t * p_sc_oob_conf; + + /** + * @brief Rand(16bytes) of OOB Data. + */ + uint8_t * p_sc_oob_rand; +} st_ble_gap_sc_oob_data_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_bond_info_t + * @brief Bonding information used in R_BLE_GAP_SetBondInfo(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Address of the device which exchanged the keys. + */ + st_ble_dev_addr_t * p_addr; + + /** + * @brief Information about the keys. + */ + st_ble_gap_auth_info_t * p_auth_info; + + /** + * @brief Keys distributed from the remote device in paring. + */ + st_ble_gap_key_ex_param_t * p_keys; +} st_ble_gap_bond_info_t; + + +/******************************************************************************************************************//** + * @struct st_cte_iq_sample_t + * @brief CTE IQ sample data + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint8_t chan_idx; + int16_t rssi; + uint8_t rssi_ant_id; + uint8_t cte_type; + uint8_t slot_durations; + uint8_t packet_status; + uint8_t sample_count; + struct + { + int8_t i; + int8_t q; + } * iq; +} st_cte_iq_sample_t; + +/* Event Code : BLE_GAP_EVENT_CTE_CONNLESS_REPT */ +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_connless_rept_t + * @brief connectionless CTE data report + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t sync_hdl; + uint16_t evt_counter; + st_cte_iq_sample_t sample; +} st_ble_gap_cte_connless_rept_t; + +/* Event Code : BLE_GAP_EVENT_CTE_CONN_REPT */ +/******************************************************************************************************************//** + * @struct st_ble_gap_cte_conn_rept_t + * @brief connection CTE data report + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t conn_hdl; + uint8_t rx_phy; + uint16_t evt_counter; + st_cte_iq_sample_t sample; +} st_ble_gap_cte_conn_rept_t; + +/* Event Code : BLE_GAP_EVENT_SUBRATE_CHANGE */ +/******************************************************************************************************************//** + * @struct st_ble_subrate_upd_t + * @brief subrating update event + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t conn_hdl; + uint16_t subrate_factor; + uint16_t peripheral_latency; + uint16_t continuation_number; + uint16_t supervision_timeout; +} st_ble_subrate_upd_t; + +/* Event Code : BLE_GAP_EVENT_PAST_RECV : st_ble_gap_past_est_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_past_est_evt_t + * @brief This structure notifies that + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** Periodic Advertising Sync Transfer options */ + uint16_t conn_hdl; + uint16_t service_data; + st_ble_gap_sync_est_evt_t sync; +} st_ble_gap_past_est_evt_t; + +/* Event Code : BLE_GAP_EVENT_TX_POWER_REPT: st_ble_gap_tx_power_reporting_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_tx_power_reporting_evt_t + * @brief This structure notifies that + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t conn_hdl; + uint8_t reason; + uint8_t phy; + uint8_t tx_power_level; + uint8_t tx_power_level_flag; + uint8_t delta; +} st_ble_gap_tx_power_reporting_evt_t; + +/* Event Code : BLE_GAP_EVENT_PATH_LOSS_THR: st_ble_gap_pass_loss_thr_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_pass_loss_thr_evt_t + * @brief This structure notifies that a path loss report has been received. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t conn_hdl; + uint8_t current_path_loss; + uint8_t zone_entered; +} st_ble_gap_pass_loss_thr_evt_t; + +/* Event Code : BLE_GAP_EVENT_REQ_PEER_SCA_COMP: st_ble_gap_req_peer_sca_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_req_peer_sca_evt_t + * @brief This structure notifies that a SCA request to a remote device has been completed. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + uint16_t conn_hdl; + uint8_t sca; +} st_ble_gap_req_peer_sca_evt_t; + +/* Event Code : BLE_GAP_EVENT_DTM_TEST_END_COMP: st_ble_gap_dtm_test_end_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_dtm_test_end_evt_t + * @brief report of dtm transmit/receive test end + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief the number of received packets + */ + uint16_t recv_cnt; +} st_ble_gap_dtm_test_end_evt_t; + +/* Event Code : BLE_GAP_EVENT_ENHANCED_READ_TX_POWER_LEVEL_COMP: st_ble_gap_enhanced_read_tx_power_level_evt_t */ +/******************************************************************************************************************//** + * @struct st_ble_gap_enhanced_read_tx_power_level_evt_t + * @brief Power level report of remove device. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Indicate an ACL connection + */ + uint16_t handle; + + /** + * @brief PHY + */ + uint8_t phy; + + /** + * @brief Current transmit power level + */ + int8_t crt_tx_power_level; + + /** + * @brief Maximum transmit power level + */ + int8_t max_tx_power_level; +} st_ble_gap_enhanced_read_tx_power_level_evt_t; + +/*@}*/ + +/* ============================================== ISO Type Definitions ============================================== */ + +/** @addtogroup ISO_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @struct st_ble_iso_big_param_t + * @brief big param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** @brief Number channels + * + * Maximum number of channels in a single group is + * BLE_ISO_MAX_GROUP_ISO_COUNT + */ + uint8_t num_bis; + + /** @brief Channel interval in us. + * + * Value range BT_ISO_SDU_INTERVAL_MIN - BT_ISO_SDU_INTERVAL_MAX. + */ + uint32_t sdu_intv; + + /** @brief Maximum size of an SDU + * + * Value range 0x0001 to 0x0FFF + */ + uint16_t max_sdu; + + /** @brief Channel Latency in ms. + * + * Value range 0x0005 to 0x0FA0 + */ + uint16_t max_latency; + + /** @brief The number of times that every BIS Data PDU should be retransmitted. + * + * Value range 0x00 to 0x1E + */ + uint8_t rtn; + + /** + * @brief Advertising PHY. + * @details + * | value | description | + * |:-----------|:---------------------------- | + * | 0x01 | Advertiser PHY is 1M PHY. | + * | 0x02 | Advertiser PHY is 2M PHY. | + * | 0x03 | Advertiser PHY is Coded PHY. | + */ + uint8_t phy; + + /** @brief Channel packing mode. + * + * the preferred method of arranging subevents of multiple BISes. + * BLE_ISO_PACKING_SEQUENTIAL for Sequential or + * BLE_ISO_PACKING_INTERLEAVED for Interleaved + */ + uint8_t packing; + + /** @brief Channel framing mode. + * + * the format of the BIS Data PDUs. + * BLE_ISO_FRAMING_UNFRAMED for unframed or + * BLE_ISO_FRAMING_FRAMED for framed. + */ + uint8_t framing; + + /** Whether or not to encrypt the streams. */ + uint8_t encryption; + + /** @brief Broadcast code + * + * The code used to derive the session key that is used to encrypt and + * decrypt BIS payloads. + */ + uint8_t bcode[BLE_ISO_BROADCAST_CODE_SIZE]; +} st_ble_iso_big_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_big_sync_param_t + * @brief big sync param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** @brief Number channels in @p bis_bitfield + * + * Maximum number of channels in a single group is + * BLE_ISO_MAX_GROUP_ISO_COUNT + */ + uint8_t num_bis; + + /** Bitfield of the BISes to sync to + * + * The BIS indexes start from 0x01, so the lowest allowed bit is + * bit0 that represents index 0x01. To synchronize to e.g. BIS + * indexes bit1 and bit2, the bitfield value should be bit0 | bit1. + */ + uint32_t bis_bitfield; + + /** maximum number of subevents that a Controller should use to + * receive data payloads in each interval for a BIS. + * @ref BLE_ISO_SYNC_MSE_AUTO to let controller choose. + */ + uint8_t max_subevents; + + /* Value range is 0x000A to 0x4000. + */ + uint16_t sync_timeout; + + /** Whether or not to encrypt the streams. */ + uint8_t encryption; + + /** @brief Broadcast code + * + * The code used to derive the session key that is used to encrypt and + * decrypt BIS payloads. + */ + uint8_t bcode[BLE_ISO_BROADCAST_CODE_SIZE]; +} st_ble_iso_big_sync_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_cis_qos + * @brief CIS channel QoS + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief max sdu size of input and output + */ + uint16_t max_sdu_c2p; + uint16_t max_sdu_p2c; + + /** + * @brief number of times that a CIS Data PDU should be retransmitted. + */ + uint8_t rtn_c2p; + uint8_t rtn_p2c; + + /** + * @brief Transmitter PHY preference. + * @details The phy_c2p and phy_p2c field is set to a bitwise OR of the following values. + * All other values are ignored. + * | macro | description | + * |:------------------------------------- |:---------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Use 1M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Use 2M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Use Coded PHY for Transmitter PHY. | + */ + uint8_t phy_c2p; + uint8_t phy_p2c; +} st_ble_cis_qos; + +/******************************************************************************************************************//** + * @struct st_ble_iso_cig_param_t + * @brief CIG group param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** @brief Number channels of CIG. + * @details Maximum number of channels in a single group is + * BLE_ISO_MAX_GROUP_ISO_COUNT + */ + uint8_t num_cis; + + /** @brief Center to Peripheral Channel interval in us. + */ + uint32_t sdu_intv_c2p; + + /** @brief Peripheral to Center Channel interval in us. + */ + uint32_t sdu_intv_p2c; + + /** @brief Center to Peripheral Channel Latency in ms. + * @details Value range 0x0005 - 0x0FA0 + */ + uint16_t max_latency_c2p; + + /** @brief Peripheral to CenterCenter to Peripheral Channel Latency in ms. + * @details Value range 0x0005 - 0x0FA0 + */ + uint16_t max_latency_p2c; + + /** @brief Channel packing mode. + * @details The preferred method of arranging subevents of multiple CISes. + * @ref BLE_ISO_PACKING_SEQUENTIAL for Sequential or + * @ref BLE_ISO_PACKING_INTERLEAVED for Interleaved + */ + uint8_t packing; + + /** @brief Channel framing mode. + * @details The format of the CIS Data PDUs. + * @ref BLE_ISO_FRAMING_UNFRAMED for unframed or + * @ref BLE_ISO_FRAMING_FRAMED for framed. + */ + uint8_t framing; + + /** @brief qos param. */ + st_ble_cis_qos cis_qos[BLE_ISO_MAX_GROUP_ISO_COUNT]; +} st_ble_iso_cig_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_cis_conn_t + * @brief CIS stream param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** @brief CIG id of this group */ + uint8_t cig_id; + + /** @brief Number channels of CIG. + * @details Maximum number of channels in a single group is + * BLE_ISO_MAX_GROUP_ISO_COUNT + */ + uint8_t num_cis; + + /** @brief handles for every CIS. + * @details CIS handles are got from event BLE_ISO_EVENT_CIG_PARAM_SET_COMP. + */ + uint16_t cis_hdl[BLE_ISO_MAX_GROUP_ISO_COUNT]; + + /** @brief handles of ACL for every CIS. + */ + uint16_t acl_hdl[BLE_ISO_MAX_GROUP_ISO_COUNT]; +} st_ble_iso_cis_conn_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_chan_path + * @brief ISO channel path param + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief path direction. + * @details Select value from BLE_ISO_DATAPATH_DIR_INPUT or BLE_ISO_DATAPATH_DIR_OUTPUT + */ + uint8_t path_dir; + + /** + * @brief path ID + * @details Only @ref BLE_ISO_DATA_PATH_HCI is accepted. + */ + uint8_t path_id; + + /** + * @brief Coding Format + * @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers). + */ + uint8_t coding_format; + + /** + * @brief Company ID + */ + uint16_t company_id; + + /** + * @brief Vendor-defined Codec ID + * @details Shall be ignored if coding_format is not 0xFF + */ + uint16_t vcodec_id; + + /** + * @brief Controller Delay + */ + uint32_t delay; + + /** + * @brief Codec Configuration length. Reserved for future use. + */ + uint8_t codec_conf_len; + + /** + * @brief Pointer to an array containing the Codec Configuration. Reserved for future use. + */ + uint8_t * codec_conf; +} st_ble_iso_chan_path; + +/** + * @brief SDU data structure in SDU input/output flow. + * @details Event Code : BLE_ISO_EVENT_ISO_RX_DATA_IND. + * Also the param of R_BLE_ISO_SendData and R_BLE_ISO_SendDataNoCopy. + */ +/******************************************************************************************************************//** + * @struct st_ble_iso_sdu_t + * @brief ISO SDU structure + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Identifier of the logical channel. + * Should use BIS or CIS handle for this field. + */ + uint16_t conn_hdl; + + /** + * @brief if 0 then timestamp value is invalid. + */ + uint16_t ts_valid; + + /** + * @brief timestamp of SDU. Valid when ts_valid is not 0. + */ + uint32_t timestamp; + + /** + * @brief sequence number + */ + uint16_t seq_num; + + /** + * @brief Length of SDU. + */ + uint16_t sdu_len; + + /** + * @brief SDU data. + */ + uint8_t * sdu_data; +} st_ble_iso_sdu_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_bis_qos_t + * @brief BIS channel QoS data. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Maximum number of subevents in each isochronous event + */ + uint8_t nse; + + /** + * @brief The number of new payloads in each BIS event + */ + uint8_t bn; + + /** + * @brief Offset used for pre-transmissions + */ + uint8_t pto; + + /** + * @brief The number of times a payload is transmitted in a BIS event + **/ + uint8_t irc; + + /** + * @brief Maximum size, in octets, of the payload + */ + uint16_t max_pdu; + + /** + * @brief The interval, in microseconds, of periodic SDUs + */ + uint16_t iso_interval; +} st_ble_iso_bis_qos_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_create_big_test_param_t + * @brief This is the parameters used in R_BLE_ISO_CreateBigTest(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Total number of BISes in the BIG. + */ + uint8_t num_bis; + + /** + * @brief The interval, in microseconds, of periodic SDUs. + */ + uint8_t sdu_interval[3]; + + /** + * @brief The time between consecutive BIG anchor points. + */ + uint16_t iso_interval; + + /** + * @brief The total number of subevents in each interval of each BIS in the BIG. + */ + uint8_t nse; + + /** + * @brief Maximum size, in octets, of an SDU. + */ + uint16_t max_sdu; + + /** + * @brief Maximum size, in octets, of payload. + */ + uint16_t max_pdu; + + /** + * @brief The transmitter PHY of packets. + */ + uint8_t phy; + + /** + * @brief The preferred method of arranging subevents of multiple BISes. + */ + uint8_t packing; + + /** + * @brief The format for sending BIS Data PDUs. + */ + uint8_t framing; + + /** + * @brief Number of new payloads for each BIS in a BIS event. + */ + uint8_t bn; + + /** + * @brief Number of times the scheduled data packet is transmitted. + */ + uint8_t irc; + + /** + * @brief Offset in number of ISO_Intervals for pre transmissions of data packets. + */ + uint8_t pto; + + /** + * @brief Encryption mode of the BISes in the BIG. + */ + uint8_t encryption; + + /** + * @brief Used to generate the session key to encrypt payloads of all BISes in the BIG. + */ + uint8_t bcode[BLE_ISO_BROADCAST_CODE_SIZE]; +} st_ble_iso_create_big_test_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_cis_qos_test_t + * @brief CIS channel QoS. This is the member variables of st_ble_iso_set_cig_param_test_param_t. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Used to identify the CIS. + */ + uint8_t cis_id; + + /** + * @brief Maximum number of subevents for each CIS in a CIG event. + */ + uint8_t nse; + + /** + * @brief Maximum size, in octets, of the payload from the Central’s Host. + */ + uint16_t c_sdu; + + /** + * @brief Maximum size, in octets, of the payload from the Peripheral’s Host. + */ + uint16_t p_sdu; + + /** + * @brief Maximum size, in octets, of the payload from the Central’s Link Layer to the Peripheral’s Link Layer. + */ + uint16_t c_pdu; + + /** + * @brief Maximum size, in octets, of the payload from the Peripheral’s Link Layer to the Central’s Link Layer. + */ + uint16_t p_pdu; + + /** + * @brief The transmitter PHY of packets from the Central. + */ + uint8_t c_phy; + + /** + * @brief The transmitter PHY of packets from the Peripheral. + */ + uint8_t p_phy; + + /** + * @brief Burst number for Central to Peripheral. + */ + uint8_t c_bn; + + /** + * @brief Burst number for Peripheral to Central. + */ + uint8_t p_bn; +} st_ble_cis_qos_test_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_set_cig_param_test_param_t + * @brief Parameters used in R_BLE_ISO_SetCigParamTest(). + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Time interval of periodic SDUs from the Central’s Host. + */ + uint8_t c_interval[3]; + + /** + * @brief Time interval of periodic SDUs from the Peripheral’s Host. + */ + uint8_t p_interval[3]; + + /** + * @brief Maximum time for a payload from the Central to Peripheral to be transmitted and re-transmitted, after which it is flushed. + */ + uint8_t c_ft; + + /** + * @brief Maximum time for a payload from the Peripheral to Central to be transmitted and re-transmitted, after which it is flushed. + */ + uint8_t p_ft; + + /** + * @brief Time between two consecutive CIS anchor points. + */ + uint16_t iso_interval; + + /** + * @brief Worst-case sleep clock accuracy of all the Peripherals that will participate in the CIG. + */ + uint8_t sca; + + /** + * @brief Preferred method of arranging subevents of multiple CISes. + */ + uint8_t packing; + + /** + * @brief Format of the CIS Data PDUs of all the CISes. + */ + uint8_t framing; + + /** + * @brief Total number of CIS configurations in the CIG being added or modified. + */ + uint8_t num_cis; + + /** + * @brief CIS QoS configurations. + */ + st_ble_cis_qos_test_t cis[BLE_ISO_MAX_GROUP_ISO_COUNT]; +} st_ble_iso_set_cig_param_test_param_t; + +/* ============================================== ISO Event Parameters ============================================== */ + +/** Event Code : BLE_ISO_EVENT_CREATE_BIG_COMP + * BLE_ISO_EVENT_CREATE_BIG_SYNC_COMP: st_ble_iso_big_comp_evt_t + */ +/******************************************************************************************************************//** + * @struct st_ble_iso_big_comp_evt_t + * @brief BIG info of a created BIG. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief status of BIG creation + */ + uint8_t status; + + /** + * @brief BIG handle + */ + uint8_t big_hdl; + + /** + * @brief BIG sync delay + */ + uint32_t sync_delay; + + /** + * @brief Actual latency returned by controller + */ + uint32_t latency; + + /** + * @brief PHY + */ + uint8_t phy; + + /** + * @brief qos parameters + */ + st_ble_iso_bis_qos_t bis_qos; + + /** + * @brief number of streams in the group + */ + uint8_t num_bis; + + /** + * @brief handles of all streams + */ + uint16_t bis_hdl[BLE_ISO_MAX_GROUP_ISO_COUNT]; +} st_ble_iso_big_comp_evt_t; + +/* Event Code : BLE_ISO_EVENT_BIGINFO_REPT */ +/******************************************************************************************************************//** + * @struct st_ble_iso_biginfo_rept_evt_t + * @brief BIG info report in a periodic adv. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Advertiser SID + */ + uint8_t sid; + + /** + * @brief Number of BISes in the BIG + */ + uint8_t num_bis; + + /** + * @brief Maximum number of subevents in each isochronous event + */ + uint8_t sub_evt_count; + + /** + * @brief Interval between two BIG anchor point (N * 1.25 ms) + */ + uint16_t iso_interval; + + /** + * @brief The number of new payloads in each BIS event + */ + uint8_t burst_number; + + /** + * @brief Offset used for pre-transmissions + */ + uint8_t pto; + + /** + * @brief The number of times a payload is transmitted in a BIS event + */ + uint8_t rep_count; + + /** + * @brief Maximum size, in octets, of the payload + * */ + uint16_t max_pdu; + + /** + * @brief The interval, in microseconds, of periodic SDUs. + */ + uint32_t sdu_interval; + + /** + * @brief Maximum size of an SDU, in octets. + */ + uint16_t max_sdu; + + /** + * @brief Channel PHY + */ + uint8_t phy; + + /** + * @brief Channel framing mode + */ + uint8_t framing; + + /** + * @brief Whether or not the BIG is encrypted + */ + uint8_t encryption; +} st_ble_iso_biginfo_rept_evt_t; + +/* Event Code : BLE_ISO_EVENT_CIG_PARAM_SET_COMP */ +/******************************************************************************************************************//** + * @struct st_ble_iso_cig_set_evt_t + * @brief CIS + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief number of CIG streams + */ + uint8_t cig_id; + + /** + * @brief number of CIS streams + */ + uint8_t num_cis; + + /** + * @brief cis_id over peers. Application should store cis_id for profile's usage + */ + uint8_t cis_id[BLE_ISO_MAX_GROUP_ISO_COUNT]; + + /** + * @brief CIS conn handle + */ + uint16_t cis_hdl[BLE_ISO_MAX_GROUP_ISO_COUNT]; +} st_ble_iso_cig_set_evt_t; + +/* Event Code : BLE_ISO_EVENT_CIS_REQ */ +/******************************************************************************************************************//** + * @struct st_ble_iso_cis_req_evt_t + * @brief CIS reqest from remote device. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief cig_id over peers. Application should check the request by cig_id and cis_id + */ + uint8_t cig_id; + + /** + * @brief cis_id over peers. Application should check the request by cig_id and cis_id + */ + uint8_t cis_id; + + /** + * @brief The ACL handle over which this cis is created. + */ + uint16_t acl_hdl; +} st_ble_iso_cis_req_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_cis_qos_t + * @brief CIS channel QoS data. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Maximum number of subevents in each isochronous event + */ + uint8_t nse; + + /** + * @brief The number of new payloads in each CIS event + */ + uint8_t bn_c2p; + uint8_t bn_p2c; + + /** + * @brief The flush timeout, in multiples of the ISO_Interval for the CIS + */ + uint8_t flush_to_c2p; + uint8_t flush_to_p2c; + + /** + * @brief Maximum size, in octets, of the payload + */ + uint16_t max_pdu_c2p; + uint16_t max_pdu_p2c; + + /** + * @brief The time between two consecutive CIS anchor points + */ + uint16_t iso_interval; +} st_ble_iso_cis_qos_t; + +/* Event Code : BLE_ISO_EVENT_CIS_EST */ +/******************************************************************************************************************//** + * @struct st_ble_iso_cis_est_evt_t + * @brief Information of CIS that was estabilished. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief CIS handler + */ + uint16_t cis_hdl; + + /** + * @brief CIG sync delay + */ + uint32_t cig_sync_delay; + + /** + * @brief CIS sync delay + */ + uint32_t cis_sync_delay; + + /** + * @brief latency of each direction + */ + uint32_t latency_c2p; + uint32_t latency_p2c; + + /** + * @brief PHY of each direction + */ + uint8_t phy_c2p; + uint8_t phy_p2c; + + /** + * @brief qos parameters + */ + st_ble_iso_cis_qos_t cis_qos; +} st_ble_iso_cis_est_evt_t; + +/* Event Code : BLE_ISO_EVENT_ISO_TX_COMP */ +/******************************************************************************************************************//** + * @struct st_ble_iso_tx_comp_evt_t + * @brief Information of ISO SDU that was sent. + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** connection handle of the ISO packet that was sent */ + uint16_t conn_hdl; + + /** sequence number of ISO packet that was sent */ + uint32_t seq_num; +} st_ble_iso_tx_comp_evt_t; + +/* Event Code : BLE_ISO_EVENT_READ_TEST_CNT_COMP: st_ble_iso_test_cnt_info_t */ +/******************************************************************************************************************//** + * @struct st_ble_iso_test_cnt_info_t + * @brief ISO test count + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Indicate an BIS or CIS. + */ + uint16_t conn_hdl; + + /** + * @brief Number in the Received_SDU_Count. + */ + uint32_t received_cnt; + + /** + * @brief Number in the Missed_SDU_Count. + */ + uint32_t missed_cnt; + + /** + * @brief Number in the Failed_SDU_Count. + */ + uint32_t failed_cnt; +} st_ble_iso_test_cnt_info_t; + +/* Event Code : BLE_ISO_EVENT_TEST_ENDED: st_ble_iso_test_end_rept_t */ +/******************************************************************************************************************//** + * @struct st_ble_iso_test_end_rept_t + * @brief ISO test report + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Indicate an BIS or CIS. + */ + uint16_t conn_hdl; + + /** + * @brief Number in the Received_SDU_Count. + */ + uint32_t received_cnt; + + /** + * @brief Number in the Missed_SDU_Count. + */ + uint32_t missed_cnt; + + /** + * @brief Number in the Failed_SDU_Count. + */ + uint32_t failed_cnt; +} st_ble_iso_test_end_rept_t; + +/* Event Code : BLE_ISO_EVENT_READ_LINK_QUALITY_COMP: st_ble_iso_link_quality_info_t */ +/******************************************************************************************************************//** + * @struct st_ble_iso_link_quality_info_t + * @brief ISO link qulity information + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief Indicate an BIS or CIS. + */ + uint16_t conn_hdl; + + /** + * @brief Value of the Tx_UnACKed_Packets counter. + */ + uint32_t tx_unacked_packets; + + /** + * @brief Value of the Tx_Flushed_Packets counter. + */ + uint32_t tx_flushed_packets; + + /** + * @brief Value of the Tx_Last_Subevent_Packets counter. + */ + uint32_t tx_last_subevent_packets; + + /** + * @brief Value of the Retransmitted_Packets counter. + */ + uint32_t retransmitted_packets; + + /** + * @brief Value of the CRC_Error_Packets counter. + */ + uint32_t crc_error_packets; + + /** + * @brief Value of the Rx_Unreceived_Packets counter. + */ + uint32_t rx_unreceived_packets; + + /** + * @brief Value of the Duplicate_Packets counter. + */ + uint32_t duplicate_packets; +} st_ble_iso_link_quality_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_iso_tx_sync_info_t + * @brief iso TX sync information + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** Indicate an BIS or CIS. */ + uint16_t conn_hdl; + + /** CIG reference point or BIG anchor point of a transmitted SDU, in microseconds. */ + uint32_t ts; + + /** Time offset, in microseconds */ + uint32_t offset; + + /** Packet sequence number */ + uint16_t seq_num; +} st_ble_iso_tx_sync_info_t; + +/* Event Code : BLE_ISO_EVENT_SYNC_TERM */ +/* Event Code : BLE_ISO_EVENT_SYNC_LOST */ +/******************************************************************************************************************//** + * @struct st_ble_iso_group_hdl_evt_t + * @brief ISO gourp handle + **********************************************************************************************************************/ +typedef struct BLE_PACKED_OPTION +{ + /** + * @brief BIG handle or CIG id + */ + uint8_t group_hdl; +} st_ble_iso_group_hdl_evt_t; + +/*@}*/ + +/* ================================================= GAP Event Code ================================================= */ + +/** @addtogroup GAP_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @enum e_ble_gap_evt_t + * @brief GAP Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief Invalid GAP Event. + * + * ## Event Code: 0x1001 + * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_INVALID = 0x1001, + + /* Range for Generic events - 0x01 to 0x0F */ + + /** + * @brief Host Stack has been initialized. + * @details + * When initializing host stack by R_BLE_GAP_Init() has been completed, + * BLE_GAP_EVENT_STACK_ON event is notified. + * + * ## Event Code: 0x1002 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_ON, + + /** + * @brief Host Stack has been terminated. + * @details + * When terminating host stack by R_BLE_GAP_Terminate() has been completed, + * BLE_GAP_EVENT_STACK_OFF event is notified. + * + * ## Event Code: 0x1003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008)When function was called, host stack has not yet been initialized.
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_OFF, + + /** + * @brief Version information of local device. + * @details + * When version information of local device has been retrieved by R_BLE_GAP_GetVerInfo(), + * BLE_GAP_EVENT_LOC_VER_INFO event is notified. + * + * ## Event Code: 0x1004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_loc_dev_info_evt_t + */ + BLE_GAP_EVENT_LOC_VER_INFO, + + /** + * @brief Hardware Error. + * @details + * When hardware error has been received from Controller, BLE_GAP_EVENT_HW_ERR event is notified. + * + * ## Event Code: 0x1005 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_hw_err_evt_t + */ + BLE_GAP_EVENT_HW_ERR, + + /** + * @brief Command Status Error. + * @details + * When the error of HCI Command has occurred after a R_BLE GAP API call, BLE_GAP_EVENT_CMD_ERR event is notified. + * + * ## Event Code: 0x1101 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_cmd_err_evt_t + */ + BLE_GAP_EVENT_CMD_ERR = 0x1101, + + /** + * @brief Advertising Report. + * @details + * When advertising PDUs has been received after scanning was started by R_BLE_GAP_StartScan(). + * + * ## Event Code: 0x1102 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_rept_evt_t + */ + BLE_GAP_EVENT_ADV_REPT_IND, + + /** + * @brief Advertising parameters have been set. + * @details + * Advertising parameters have been configured by R_BLE_GAP_SetAdvParam(). + * + * ## Event Code: 0x1103 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising type that doesn't support advertising data/scan response data was + * specified to the advertising set which has already set + * advertising data/scan response data. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - Advertising parameters were configured to the advertising set in advertising.
+ * - The sec_adv_phy field in adv_paran was not specified + * when Periodic Advertising was started. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_PARAM_SET_COMP, + + /** + * @brief Advertising data has been set. + * @details + * This event notifies that Advertising Data/Scan Response Data/Periodic Advertising Data has been + * set to the advertising set by R_BLE_GAP_SetAdvSresData(). + * + * ## Event Code: 0x1104 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - The advertising set that doesn't support advertising data/scan response data + * was set to the data.
+ * - The advertising set that supports legacy advertising was set to + * advertising data/scan response data larger than 31 bytes.
+ * - The advertising set that has advertising data/scan response data greater + * than or equal to 252 bytes was set the data in advertising.
+ * - The advertising set that has periodic advertising data greater than or equal to + * 253 bytes was set the data in advertising. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Length exceeded the length that the advertising set could be set. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetAdvSresData() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_data_evt_t + */ + BLE_GAP_EVENT_ADV_DATA_UPD_COMP, + + /** + * @brief Advertising has started. + * @details + * When advertising has been started by R_BLE_GAP_StartAdv(), this event is notified to the application layer. + * + * ## Event Code: 0x1105 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows.
+ * - The advertising data length set to the advertising set + * for connectable extended advertising was invalid.
+ * - If o_addr_type field in adv_param used in R_BLE_GAP_SetAdvParam() is 0x03, + * the address which is set in o_addr field of adv_param + * has not been registered in Resolving List. + *
BLE_ERR_INVALID_OPERATION(0x0009)Setting of advertising data/scan response data has not been completed.
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StartAdv() has not been created. + *
BLE_ERR_LIMIT_EXCEEDED(0x0010)When the maximum connections are established, a new connectable advertising tried starting.
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_ON, + + /** + * @brief Advertising has stopped. + * @details + * This event notifies the application layer that advertising has stopped. + * + * ## Event Code: 0x1106 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StopAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_off_evt_t */ - st_ble_gap_key_ex_param_t * p_keys; -} st_ble_gap_bond_info_t; - -/*@}*/ - -/* ================================================= GAP Event Code ================================================= */ - -/** @addtogroup GAP_API - * @ingroup BLE_API - * @{ - */ + BLE_GAP_EVENT_ADV_OFF, -/******************************************************************************************************************//** - * @enum e_ble_gap_evt_t - * @brief GAP Event Identifier - **********************************************************************************************************************/ -typedef enum -{ /** - * @brief Invalid GAP Event. + * @brief Periodic advertising parameters have been set. + * @details + * This event notifies the application layer that Periodic Advertising Parameters + * has been configured by R_BLE_GAP_SetPerdAdvParam(). * - * ## Event Code: 0x1001 + * ## Event Code: 0x1107 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising set was the setting for anonymous advertising. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The advertising set was configured to the parameters in periodic advertising. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetPerdAdvParam() has not been created. + *
+ *
* * ## Event Data: - * none + * st_ble_gap_adv_set_evt_t */ - BLE_GAP_EVENT_INVALID = 0x1001, - - /* Range for Generic events - 0x01 to 0x0F */ + BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP, /** - * @brief Host Stack has been initialized. + * @brief Periodic advertising has started. * @details - * When initializing host stack by R_BLE_GAP_Init() has been completed, - * BLE_GAP_EVENT_STACK_ON event is notified. + * When Periodic Advertising has been started by R_BLE_GAP_StartPerdAdv(), + * this event is notified to the application layer. * - * ## Event Code: 0x1002 + * ## Event Code: 0x1108 * * ## result: *
@@ -5836,21 +7834,33 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * The periodic advertising data set in the advertising set has not been completed. + * + * + * + * BLE_ERR_INVALID_HDL(0x000E) + * + * The advertising set specified by R_BLE_GAP_StartPerdAdv() has not been created. + * + * * *
* * ## Event Data: - * none + * st_ble_gap_adv_set_evt_t */ - BLE_GAP_EVENT_STACK_ON, + BLE_GAP_EVENT_PERD_ADV_ON, /** - * @brief Host Stack has been terminated. + * @brief Periodic advertising has stopped. * @details - * When terminating host stack by R_BLE_GAP_Terminate() has been completed, - * BLE_GAP_EVENT_STACK_OFF event is notified. + * When Periodic Advertising has terminated by R_BLE_GAP_StopPerdAdv(), + * this event is notified to the application layer. * - * ## Event Code: 0x1003 + * ## Event Code: 0x1109 * * ## result: *
@@ -5860,24 +7870,26 @@ typedef enum * Success * * - * BLE_ERR_INVALID_STATE(0x0008) - * When function was called, host stack has not yet been initialized. + * BLE_ERR_INVALID_HDL(0x000E) + * + * The advertising set specified by R_BLE_GAP_StopPerdAdv() has not been created. + * * * *
* * ## Event Data: - * none + * st_ble_gap_adv_set_evt_t */ - BLE_GAP_EVENT_STACK_OFF, + BLE_GAP_EVENT_PERD_ADV_OFF, /** - * @brief Version information of local device. + * @brief Advertising set has been deleted. * @details - * When version information of local device has been retrieved by R_BLE_GAP_GetVerInfo(), - * BLE_GAP_EVENT_LOC_VER_INFO event is notified. + * When the advertising set has been removed by R_BLE_GAP_RemoveAdvSet(), + * this event is notified to the application layer. * - * ## Event Code: 0x1004 + * ## Event Code: 0x110A * * ## result: *
@@ -5886,20 +7898,33 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * When the advertising set was in advertising, R_BLE_GAP_RemoveAdvSet() was called. + * + * + * + * BLE_ERR_INVALID_HDL(0x000E) + * + * The advertising set specified by R_BLE_GAP_RemoveAdvSet() has not been created. + * + * * *
* * ## Event Data: - * st_ble_gap_loc_dev_info_evt_t + * st_ble_gap_rem_adv_set_evt_t */ - BLE_GAP_EVENT_LOC_VER_INFO, + BLE_GAP_EVENT_ADV_SET_REMOVE_COMP, /** - * @brief Hardware Error. + * @brief Scanning has started. * @details - * When hardware error has been received from Controller, BLE_GAP_EVENT_HW_ERR event is notified. + * When scanning has started by R_BLE_GAP_StartScan(), + * this event is notified to the application layer. * - * ## Event Code: 0x1005 + * ## Event Code: 0x110B * * ## result: *
@@ -5908,20 +7933,36 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * + * + * BLE_ERR_INVALID_ARG(0x0003) + * + * The reason for this error is as follows:
+ * - Scan interval or scan window was invalid. + * - When filter_dup field in scan_enable was BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02), + * period field in scan_enable was 0. + * - duration field in scan_enable was larger than period in scan_enable. + * + * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * In scanning, R_BLE_GAP_StartScan() was called. + * + * * *
* * ## Event Data: - * st_ble_gap_hw_err_evt_t + * none */ - BLE_GAP_EVENT_HW_ERR, + BLE_GAP_EVENT_SCAN_ON, /** - * @brief Command Status Error. + * @brief Scanning has stopped. * @details - * When the error of HCI Command has occurred after a R_BLE GAP API call, BLE_GAP_EVENT_CMD_ERR event is notified. + * When scanning has been stopped by R_BLE_GAP_StopScan(), this event is notified to the application layer. * - * ## Event Code: 0x1101 + * ## Event Code: 0x110C * * ## result: *
@@ -5934,16 +7975,17 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_cmd_err_evt_t + * none */ - BLE_GAP_EVENT_CMD_ERR = 0x1101, + BLE_GAP_EVENT_SCAN_OFF, /** - * @brief Advertising Report. + * @brief Scanning has stopped, because duration specified by API expired. * @details - * When advertising PDUs has been received after scanning was started by R_BLE_GAP_StartScan(). + * When the scan duration specified by R_BLE_GAP_StartScan() has expired, + * this event notifies scanning has stopped. * - * ## Event Code: 0x1102 + * ## Event Code: 0x110D * * ## result: *
@@ -5956,16 +7998,16 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_adv_rept_evt_t + * none */ - BLE_GAP_EVENT_ADV_REPT_IND, + BLE_GAP_EVENT_SCAN_TO, /** - * @brief Advertising parameters have been set. + * @brief Connection Request has been sent to Controller. * @details - * Advertising parameters have been configured by R_BLE_GAP_SetAdvParam(). + * This event notifies a request for a connection has been sent to Controller. * - * ## Event Code: 0x1103 + * ## Event Code: 0x110E * * ## result: *
@@ -5977,35 +8019,89 @@ typedef enum * * BLE_ERR_INVALID_ARG(0x0003) * - * The advertising type that doesn't support advertising data/scan response data was - * specified to the advertising set which has already set - * advertising data/scan response data. + * The reason for this error is as follows:
+ * - Scan interval or scan windows specified by R_BLE_GAP_CreateConn() is invalid. + * - Although the own_addr_type field in p_param was set to 0x03, + * random address had not been registered in Resolving List. * * * * BLE_ERR_INVALID_OPERATION(0x0009) * - * The reason for this error is as follows.
- * - Advertising parameters were configured to the advertising set in advertising.
- * - The sec_adv_phy field in adv_paran was not specified - * when Periodic Advertising was started. + * R_BLE_GAP_CreateConn() was called while creating a link + * by previous R_BLE_GAP_CreateConn() call . + * + * + * + * BLE_ERR_LIMIT_EXCEEDED(0x0010) + * + * When the maximum connections are established, R_BLE_GAP_CreateConn() was called. + * + * + * + *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CREATE_CONN_COMP, + + /** + * @brief Link has been established. + * @details + * This event notifies a link has been established. + * + * ## Event Code: 0x110F + * + * ## result: + *
+ * + * + * + * + * + * + * + * * *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). *
*
* * ## Event Data: - * st_ble_gap_adv_set_evt_t + * st_ble_gap_conn_evt_t + */ + BLE_GAP_EVENT_CONN_IND, + + /** + * @brief Link has been disconnected. + * @details + * This event notifies a link has been disconnected. + * + * ## Event Code: 0x1110 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_disconn_evt_t */ - BLE_GAP_EVENT_ADV_PARAM_SET_COMP, + BLE_GAP_EVENT_DISCONN_IND, /** - * @brief Advertising data has been set. + * @brief Connection Cancel Request has been sent to Controller. * @details - * This event notifies that Advertising Data/Scan Response Data/Periodic Advertising Data has been - * set to the advertising set by R_BLE_GAP_SetAdvSresData(). + * This event notifies the request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). * - * ## Event Code: 0x1104 + * ## Event Code: 0x1111 * * ## result: *
@@ -6017,43 +8113,24 @@ typedef enum * * BLE_ERR_INVALID_OPERATION(0x0009) * - * The reason for this error is as follows.
- * - The advertising set that doesn't support advertising data/scan response data - * was set to the data.
- * - The advertising set that supports legacy advertising was set to - * advertising data/scan response data larger than 31 bytes.
- * - The advertising set that has advertising data/scan response data greater - * than or equal to 252 bytes was set the data in advertising.
- * - The advertising set that has periodic advertising data greater than or equal to - * 253 bytes was set the data in advertising. - * - * - * - * BLE_ERR_MEM_ALLOC_FAILED(0x000C) - * - * Length exceeded the length that the advertising set could be set. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The advertising set specified by R_BLE_GAP_SetAdvSresData() has not been created. + * When a request for a connection has not been sent to Controller, + * R_BLE_GAP_CancelCreateConn() was called. * * * *
* * ## Event Data: - * st_ble_gap_adv_data_evt_t + * none */ - BLE_GAP_EVENT_ADV_DATA_UPD_COMP, + BLE_GAP_EVENT_CONN_CANCEL_COMP, /** - * @brief Advertising has started. + * @brief The White List has been configured. * @details - * When advertising has been started by R_BLE_GAP_StartAdv(), this event is notified to the application layer. + * When White List has been configured, this event is notified to the application layer. * - * ## Event Code: 0x1105 + * ## Event Code: 0x1112 * * ## result: *
@@ -6063,44 +8140,38 @@ typedef enum * Success * * - * BLE_ERR_INVALID_ARG(0x0003) + * BLE_ERR_INVALID_STATE(0x0008) * - * The reason for this error is as follows.
- * - The advertising data length set to the advertising set - * for connectable extended advertising was invalid.
- * - If o_addr_type field in adv_param used in R_BLE_GAP_SetAdvParam() is 0x03, - * the address which is set in o_addr field of adv_param - * has not been registered in Resolving List. + * The add or delete operation was called, before the previous clear operation has been completed. * * * * BLE_ERR_INVALID_OPERATION(0x0009) - * Setting of advertising data/scan response data has not been completed. - * - * - * BLE_ERR_INVALID_HDL(0x000E) * - * The advertising set specified by R_BLE_GAP_StartAdv() has not been created. + * While doing advertising or scanning or creating a link with the White List, + * R_BLE_GAP_ConfWhiteList() was called. * * * - * BLE_ERR_LIMIT_EXCEEDED(0x0010) - * When the maximum connections are established, a new connectable advertising tried starting. + * BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * + * White List has already registered the maximum number of devices. + * * * *
* * ## Event Data: - * st_ble_gap_adv_set_evt_t + * st_ble_gap_white_list_conf_evt_t */ - BLE_GAP_EVENT_ADV_ON, + BLE_GAP_EVENT_WHITE_LIST_CONF_COMP, /** - * @brief Advertising has stopped. + * @brief Random address has been set to Controller. * @details - * This event notifies the application layer that advertising has stopped. + * This event notifies Controller has been set the random address by R_BLE_GAP_SetRandAddr(). * - * ## Event Code: 0x1106 + * ## Event Code: 0x1113 * * ## result: *
@@ -6110,26 +8181,25 @@ typedef enum * Success * * - * BLE_ERR_INVALID_HDL(0x000E) + * BLE_ERR_INVALID_OPERATION(0x0009) * - * The advertising set specified by R_BLE_GAP_StopAdv() has not been created. + * When local device was in legacy advertising, R_BLE_GAP_SetRandAddr() was called. * * * *
* * ## Event Data: - * st_ble_gap_adv_off_evt_t + * none */ - BLE_GAP_EVENT_ADV_OFF, + BLE_GAP_EVENT_RAND_ADDR_SET_COMP, /** - * @brief Periodic advertising parameters have been set. + * @brief Channel Map has been retrieved. * @details - * This event notifies the application layer that Periodic Advertising Parameters - * has been configured by R_BLE_GAP_SetPerdAdvParam(). + * This event notifies Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). * - * ## Event Code: 0x1107 + * ## Event Code: 0x1114 * * ## result: *
@@ -6139,38 +8209,25 @@ typedef enum * Success * * - * BLE_ERR_INVALID_ARG(0x0003) - * - * The advertising set was the setting for anonymous advertising. - * - * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * The advertising set was configured to the parameters in periodic advertising. - * - * - * * BLE_ERR_INVALID_HDL(0x000E) * - * The advertising set specified by R_BLE_GAP_SetPerdAdvParam() has not been created. + * The remote device specified by R_BLE_GAP_ReadChMap() was not found. * * * *
* * ## Event Data: - * st_ble_gap_adv_set_evt_t + * st_ble_gap_rd_ch_map_evt_t */ - BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP, + BLE_GAP_EVENT_CH_MAP_RD_COMP, /** - * @brief Periodic advertising has started. + * @brief Channel Map has set. * @details - * When Periodic Advertising has been started by R_BLE_GAP_StartPerdAdv(), - * this event is notified to the application layer. + * This event notifies Channel Map has been configured by R_BLE_GAP_SetChMap(). * - * ## Event Code: 0x1108 + * ## Event Code: 0x1115 * * ## result: *
@@ -6180,32 +8237,25 @@ typedef enum * Success * * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * The periodic advertising data set in the advertising set has not been completed. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) + * BLE_ERR_INVALID_ARG(0x0003) * - * The advertising set specified by R_BLE_GAP_StartPerdAdv() has not been created. + * The channel map specified by R_BLE_GAP_SetChMap() was all-zero. * * * *
* * ## Event Data: - * st_ble_gap_adv_set_evt_t + * none */ - BLE_GAP_EVENT_PERD_ADV_ON, + BLE_GAP_EVENT_CH_MAP_SET_COMP, /** - * @brief Periodic advertising has stopped. + * @brief RSSl has been retrieved. * @details - * When Periodic Advertising has terminated by R_BLE_GAP_StopPerdAdv(), - * this event is notified to the application layer. + * This event notifies RSSI has been retrieved by R_BLE_GAP_ReadRssi(). * - * ## Event Code: 0x1109 + * ## Event Code: 0x1116 * * ## result: *
@@ -6217,24 +8267,23 @@ typedef enum * * BLE_ERR_INVALID_HDL(0x000E) * - * The advertising set specified by R_BLE_GAP_StopPerdAdv() has not been created. + * The remote device specified by R_BLE_GAP_ReadRssi() was not found. * * * *
* * ## Event Data: - * st_ble_gap_adv_set_evt_t + * st_ble_gap_rd_rssi_evt_t */ - BLE_GAP_EVENT_PERD_ADV_OFF, + BLE_GAP_EVENT_RSSI_RD_COMP, /** - * @brief Advertising set has been deleted. + * @brief Information about the remote device has been retrieved. * @details - * When the advertising set has been removed by R_BLE_GAP_RemoveAdvSet(), - * this event is notified to the application layer. + * This event notifies information about the remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). * - * ## Event Code: 0x110A + * ## Event Code: 0x1117 * * ## result: *
@@ -6243,33 +8292,20 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * When the advertising set was in advertising, R_BLE_GAP_RemoveAdvSet() was called. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The advertising set specified by R_BLE_GAP_RemoveAdvSet() has not been created. - * - * * *
* * ## Event Data: - * st_ble_gap_rem_adv_set_evt_t + * st_ble_gap_dev_info_evt_t */ - BLE_GAP_EVENT_ADV_SET_REMOVE_COMP, + BLE_GAP_EVENT_GET_REM_DEV_INFO, /** - * @brief Scanning has started. + * @brief Connection parameters has been configured. * @details - * When scanning has started by R_BLE_GAP_StartScan(), - * this event is notified to the application layer. + * This event notifies the connection parameters has been updated. * - * ## Event Code: 0x110B + * ## Event Code: 0x1118 * * ## result: *
@@ -6279,35 +8315,37 @@ typedef enum * Success * * + * BLE_ERR_INVALID_DATA(0x0002) + * + * Local device rejected the request for updating connection parameters. + * + * + * * BLE_ERR_INVALID_ARG(0x0003) * - * The reason for this error is as follows:
- * - Scan interval or scan window was invalid. - * - When filter_dup field in scan_enable was BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02), - * period field in scan_enable was 0. - * - duration field in scan_enable was larger than period in scan_enable. + * The remote device rejected the connection parameters suggested from local device. * * * - * BLE_ERR_INVALID_OPERATION(0x0009) + * BLE_ERR_UNSUPPORTED(0x0007) * - * In scanning, R_BLE_GAP_StartScan() was called. + * The remote device doesn't support connection parameters update feature. * * * *
* * ## Event Data: - * none + * st_ble_gap_conn_upd_evt_t */ - BLE_GAP_EVENT_SCAN_ON, + BLE_GAP_EVENT_CONN_PARAM_UPD_COMP, /** - * @brief Scanning has stopped. + * @brief Local device has received the request for configuration of connection parameters. * @details - * When scanning has been stopped by R_BLE_GAP_StopScan(), this event is notified to the application layer. + * This event notifies the request for connection parameters update has been received. * - * ## Event Code: 0x110C + * ## Event Code: 0x1119 * * ## result: *
@@ -6320,17 +8358,16 @@ typedef enum *
* * ## Event Data: - * none + * st_ble_gap_conn_upd_req_evt_t */ - BLE_GAP_EVENT_SCAN_OFF, + BLE_GAP_EVENT_CONN_PARAM_UPD_REQ, /** - * @brief Scanning has stopped, because duration specified by API expired. + * @brief Authenticated Payload Timeout. * @details - * When the scan duration specified by R_BLE_GAP_StartScan() has expired, - * this event notifies scanning has stopped. + * This event notifies Authenticated Payload Timeout has occurred. * - * ## Event Code: 0x110D + * ## Event Code: 0x111A * * ## result: *
@@ -6343,16 +8380,16 @@ typedef enum *
* * ## Event Data: - * none + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_SCAN_TO, + BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED, /** - * @brief Connection Request has been sent to Controller. + * @brief The request for update transmission packet size and transmission time have been sent to Controller. * @details - * This event notifies a request for a connection has been sent to Controller. + * This event notifies a request for updating packet data length and transmission timer has been sent to Controller. * - * ## Event Code: 0x110E + * ## Event Code: 0x111B * * ## result: *
@@ -6364,67 +8401,35 @@ typedef enum * * BLE_ERR_INVALID_ARG(0x0003) * - * The reason for this error is as follows:
- * - Scan interval or scan windows specified by R_BLE_GAP_CreateConn() is invalid. - * - Although the own_addr_type field in p_param was set to 0x03, - * random address had not been registered in Resolving List. - * - * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * R_BLE_GAP_CreateConn() was called while creating a link - * by previous R_BLE_GAP_CreateConn() call . - * - * - * - * BLE_ERR_LIMIT_EXCEEDED(0x0010) - * - * When the maximum connections are established, R_BLE_GAP_CreateConn() was called. + * The tx_octets or tx_time parameter specified by R_BLE_GAP_SetDataLen() is invalid. * * - * - *
- * - * ## Event Data: - * none - */ - BLE_GAP_EVENT_CREATE_CONN_COMP, - - /** - * @brief Link has been established. - * @details - * This event notifies a link has been established. - * - * ## Event Code: 0x110F - * - * ## result: - *
- * * - * - * + * + * * * * * * *
BLE_SUCCESS(0x0000)Success BLE_ERR_UNSUPPORTED(0x0007) + * The remote device does not support updating packet data length and transmission time. + *
BLE_ERR_INVALID_HDL(0x000E) - * The request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + * When R_BLE_GAP_SetDataLen() was called, the connection was not established. *
*
* * ## Event Data: - * st_ble_gap_conn_evt_t + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_CONN_IND, + BLE_GAP_EVENT_SET_DATA_LEN_COMP, /** - * @brief Link has been disconnected. + * @brief Transmission packet size and transmission time have been changed. * @details - * This event notifies a link has been disconnected. + * This event notifies packet data length and transmission time have been updated. * - * ## Event Code: 0x1110 + * ## Event Code: 0x111C * * ## result: *
@@ -6437,16 +8442,17 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_disconn_evt_t + * st_ble_gap_data_len_chg_evt_t */ - BLE_GAP_EVENT_DISCONN_IND, + BLE_GAP_EVENT_DATA_LEN_CHG, /** - * @brief Connection Cancel Request has been sent to Controller. + * @brief The Resolving List has been configured. * @details - * This event notifies the request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + * When Resolving List has been configured by R_BLE_GAP_ConfRslvList(), + * this event is notified to the application layer. * - * ## Event Code: 0x1111 + * ## Event Code: 0x111D * * ## result: *
@@ -6456,26 +8462,46 @@ typedef enum * Success * * + * BLE_ERR_INVALID_STATE(0x0008) + * + * The add or delete operation was called, + * before the previous clear operation has been completed. + * + * + * * BLE_ERR_INVALID_OPERATION(0x0009) * - * When a request for a connection has not been sent to Controller, - * R_BLE_GAP_CancelCreateConn() was called. + * While doing advertising or scanning or creating a link with resolvable private address, + * R_BLE_GAP_ConfRslvList() was called. + * + * + * + * BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * + * Resolving List has already registered the maximum number of devices. + * + * + * + * BLE_ERR_INVALID_HDL(0x000E) + * + * The specified Identity Address was not found in Resolving List. * * * *
* * ## Event Data: - * none + * st_ble_gap_rslv_list_conf_evt_t */ - BLE_GAP_EVENT_CONN_CANCEL_COMP, + BLE_GAP_EVENT_RSLV_LIST_CONF_COMP, /** - * @brief The White List has been configured. + * @brief Resolvable private address function has been enabled or disabled. * @details - * When White List has been configured, this event is notified to the application layer. + * When Resolvable Private Address function in Controller has been enabled by R_BLE_GAP_EnableRpa(), + * this event is notified to the application layer. * - * ## Event Code: 0x1112 + * ## Event Code: 0x111E * * ## result: *
@@ -6485,38 +8511,27 @@ typedef enum * Success * * - * BLE_ERR_INVALID_STATE(0x0008) - * - * The add or delete operation was called, before the previous clear operation has been completed. - * - * - * * BLE_ERR_INVALID_OPERATION(0x0009) * - * While doing advertising or scanning or creating a link with the White List, - * R_BLE_GAP_ConfWhiteList() was called. - * - * - * - * BLE_ERR_MEM_ALLOC_FAILED(0x000C) - * - * White List has already registered the maximum number of devices. + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_EnableRpa() was called. * * * *
* * ## Event Data: - * st_ble_gap_white_list_conf_evt_t + * none */ - BLE_GAP_EVENT_WHITE_LIST_CONF_COMP, + BLE_GAP_EVENT_RPA_EN_COMP, /** - * @brief Random address has been set to Controller. + * @brief The update time of resolvable private address has been changed. * @details - * This event notifies Controller has been set the random address by R_BLE_GAP_SetRandAddr(). + * When Resolvable Private Address Timeout in Controller has been updated by R_BLE_GAP_SetRpaTo(), + * this event is notified to the application layer. * - * ## Event Code: 0x1113 + * ## Event Code: 0x111F * * ## result: *
@@ -6526,9 +8541,9 @@ typedef enum * Success * * - * BLE_ERR_INVALID_OPERATION(0x0009) + * BLE_ERR_INVALID_ARG(0x0003) * - * When local device was in legacy advertising, R_BLE_GAP_SetRandAddr() was called. + * The rpa_timeout parameter specified by R_BLE_GAP_SetRpaTo() is out of range. * * * @@ -6537,14 +8552,15 @@ typedef enum * ## Event Data: * none */ - BLE_GAP_EVENT_RAND_ADDR_SET_COMP, + BLE_GAP_EVENT_SET_RPA_TO_COMP, /** - * @brief Channel Map has been retrieved. + * @brief The resolvable private address of local device has been retrieved. * @details - * This event notifies Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). + * When the resolvable private address of local device has been retrieved by R_BLE_GAP_ReadRpa(), + * this event is notified to the application layer. * - * ## Event Code: 0x1114 + * ## Event Code: 0x1120 * * ## result: *
@@ -6556,23 +8572,23 @@ typedef enum * * BLE_ERR_INVALID_HDL(0x000E) * - * The remote device specified by R_BLE_GAP_ReadChMap() was not found. + * The identity address specified by R_BLE_GAP_ReadRpa() was not registered in Resolving List. * * * *
* * ## Event Data: - * st_ble_gap_rd_ch_map_evt_t + * st_ble_gap_rd_rpa_evt_t */ - BLE_GAP_EVENT_CH_MAP_RD_COMP, + BLE_GAP_EVENT_RD_RPA_COMP, /** - * @brief Channel Map has set. + * @brief PHY for connection has been changed. * @details - * This event notifies Channel Map has been configured by R_BLE_GAP_SetChMap(). + * This event notifies the application layer that PHY for a connection has been updated. * - * ## Event Code: 0x1115 + * ## Event Code: 0x1121 * * ## result: *
@@ -6581,26 +8597,21 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_ARG(0x0003) - * - * The channel map specified by R_BLE_GAP_SetChMap() was all-zero. - * - * * *
* * ## Event Data: - * none + * st_ble_gap_phy_upd_evt_t */ - BLE_GAP_EVENT_CH_MAP_SET_COMP, + BLE_GAP_EVENT_PHY_UPD, /** - * @brief RSSl has been retrieved. + * @brief The request for updating PHY for connection has been sent to Controller. * @details - * This event notifies RSSI has been retrieved by R_BLE_GAP_ReadRssi(). + * When Controller has received a request for updating PHY for a connection by R_BLE_GAP_SetPhy(), + * this event is notified to the application layer. * - * ## Event Code: 0x1116 + * ## Event Code: 0x1122 * * ## result: *
@@ -6612,23 +8623,24 @@ typedef enum * * BLE_ERR_INVALID_HDL(0x000E) * - * The remote device specified by R_BLE_GAP_ReadRssi() was not found. + * The remote device specified by R_BLE_GAP_SetPhy() was not found. * * * *
* * ## Event Data: - * st_ble_gap_rd_rssi_evt_t + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_RSSI_RD_COMP, + BLE_GAP_EVENT_PHY_SET_COMP, /** - * @brief Information about the remote device has been retrieved. + * @brief The request for setting default PHY has been sent to Controller. * @details - * This event notifies information about the remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + * When the PHY preferences which a remote device may change has been configured by R_BLE_GAP_SetDefPhy(), + * this event is notified to the application layer. * - * ## Event Code: 0x1117 + * ## Event Code: 0x1123 * * ## result: *
@@ -6641,16 +8653,17 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_dev_info_evt_t + * none */ - BLE_GAP_EVENT_GET_REM_DEV_INFO, + BLE_GAP_EVENT_DEF_PHY_SET_COMP, /** - * @brief Connection parameters has been configured. + * @brief PHY configuration has been retrieved. * @details - * This event notifies the connection parameters has been updated. + * When the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(), + * this event is notified to the application layer. * - * ## Event Code: 0x1118 + * ## Event Code: 0x1124 * * ## result: *
@@ -6660,37 +8673,25 @@ typedef enum * Success * * - * BLE_ERR_INVALID_DATA(0x0002) - * - * Local device rejected the request for updating connection parameters. - * - * - * - * BLE_ERR_INVALID_ARG(0x0003) - * - * The remote device rejected the connection parameters suggested from local device. - * - * - * - * BLE_ERR_UNSUPPORTED(0x0007) + * BLE_ERR_INVALID_HDL(0x000E) * - * The remote device doesn't support connection parameters update feature. + * The link specified by R_BLE_GAP_ReadPhy() was not found. * * * *
* * ## Event Data: - * st_ble_gap_conn_upd_evt_t + * st_ble_gap_phy_rd_evt_t */ - BLE_GAP_EVENT_CONN_PARAM_UPD_COMP, + BLE_GAP_EVENT_PHY_RD_COMP, /** - * @brief Local device has received the request for configuration of connection parameters. + * @brief Scan Request has been received. * @details - * This event notifies the request for connection parameters update has been received. + * This event notifies the application layer that a Scan Request packet has been received from a Scanner. * - * ## Event Code: 0x1119 + * ## Event Code: 0x1125 * * ## result: *
@@ -6703,16 +8704,17 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_conn_upd_req_evt_t + * st_ble_gap_scan_req_recv_evt_t */ - BLE_GAP_EVENT_CONN_PARAM_UPD_REQ, + BLE_GAP_EVENT_SCAN_REQ_RECV, /** - * @brief Authenticated Payload Timeout. + * @brief The request for establishing a periodic sync has been sent to Controller. * @details - * This event notifies Authenticated Payload Timeout has occurred. + * This event notifies the application layer that Controller has received a request + * for a Periodic Sync establishment. * - * ## Event Code: 0x111A + * ## Event Code: 0x1126 * * ## result: *
@@ -6721,20 +8723,34 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * When R_BLE_GAP_CreateSync() was called, + * this event for previous the API call has not been received. + * + * + * + * BLE_ERR_ALREADY_IN_PROGRESS(0x000A) + * + * The advertising set specified by R_BLE_GAP_CreateSync() has already established + * a periodic sync. + * + * * *
* * ## Event Data: - * st_ble_gap_conn_hdl_evt_t + * none */ - BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED, + BLE_GAP_EVENT_CREATE_SYNC_COMP, /** - * @brief The request for update transmission packet size and transmission time have been sent to Controller. + * @brief The periodic advertising sync has been established. * @details - * This event notifies a request for updating packet data length and transmission timer has been sent to Controller. + * This event notifies the application layer that a Periodic sync has been established. * - * ## Event Code: 0x111B + * ## Event Code: 0x1127 * * ## result: *
@@ -6744,37 +8760,26 @@ typedef enum * Success * * - * BLE_ERR_INVALID_ARG(0x0003) - * - * The tx_octets or tx_time parameter specified by R_BLE_GAP_SetDataLen() is invalid. - * - * - * - * BLE_ERR_UNSUPPORTED(0x0007) - * - * The remote device does not support updating packet data length and transmission time. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) + * BLE_ERR_NOT_YET_READY(0x0012) * - * When R_BLE_GAP_SetDataLen() was called, the connection was not established. + * The request for a Periodic Sync establishment was cancelled by R_BLE_GAP_CancelCreateSync(). * * * *
* * ## Event Data: - * st_ble_gap_conn_hdl_evt_t + * st_ble_gap_sync_est_evt_t */ - BLE_GAP_EVENT_SET_DATA_LEN_COMP, + BLE_GAP_EVENT_SYNC_EST, /** - * @brief Transmission packet size and transmission time have been changed. + * @brief The periodic advertising sync has been terminated. * @details - * This event notifies packet data length and transmission time have been updated. + * This event notifies the application layer that the Periodic Sync has been terminated + * by R_BLE_GAP_TerminateSync(). * - * ## Event Code: 0x111C + * ## Event Code: 0x1128 * * ## result: *
@@ -6783,21 +8788,33 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * While establishing a Periodic Sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_TerminateSync() was called. + * + * + * + * BLE_ERR_INVALID_HDL(0x000E) + * + * The sync handle specified by R_BLE_GAP_TerminateSync() was not found. + * + * * *
* * ## Event Data: - * st_ble_gap_data_len_chg_evt_t + * st_ble_gap_sync_hdl_evt_t */ - BLE_GAP_EVENT_DATA_LEN_CHG, + BLE_GAP_EVENT_SYNC_TERM, /** - * @brief The Resolving List has been configured. + * @brief The periodic advertising sync has been lost. * @details - * When Resolving List has been configured by R_BLE_GAP_ConfRslvList(), - * this event is notified to the application layer. + * This event notifies the application layer that the Periodic Sync has been lost. * - * ## Event Code: 0x111D + * ## Event Code: 0x1129 * * ## result: *
@@ -6806,47 +8823,21 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_STATE(0x0008) - * - * The add or delete operation was called, - * before the previous clear operation has been completed. - * - * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * While doing advertising or scanning or creating a link with resolvable private address, - * R_BLE_GAP_ConfRslvList() was called. - * - * - * - * BLE_ERR_MEM_ALLOC_FAILED(0x000C) - * - * Resolving List has already registered the maximum number of devices. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The specified Identity Address was not found in Resolving List. - * - * * *
* * ## Event Data: - * st_ble_gap_rslv_list_conf_evt_t + * st_ble_gap_sync_hdl_evt_t */ - BLE_GAP_EVENT_RSLV_LIST_CONF_COMP, + BLE_GAP_EVENT_SYNC_LOST, /** - * @brief Resolvable private address function has been enabled or disabled. + * @brief The request for cancel of establishing a periodic advertising sync has been sent to Controller. * @details - * When Resolvable Private Address function in Controller has been enabled by R_BLE_GAP_EnableRpa(), - * this event is notified to the application layer. + * This event notifies the request for a Periodic Sync establishment has been cancelled + * by R_BLE_GAP_CancelCreateSync(). * - * ## Event Code: 0x111E + * ## Event Code: 0x112A * * ## result: *
@@ -6858,8 +8849,9 @@ typedef enum * * BLE_ERR_INVALID_OPERATION(0x0009) * - * While advertising, scanning, or establishing a link with resolvable private address, - * R_BLE_GAP_EnableRpa() was called. + * When R_BLE_GAP_CancelCreateSync() was called, + * a request for a Periodic Sync establishment by R_BLE_GAP_CreateSync() + * has not been sent to Controller. * * * @@ -6868,15 +8860,15 @@ typedef enum * ## Event Data: * none */ - BLE_GAP_EVENT_RPA_EN_COMP, + BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP, /** - * @brief The update time of resolvable private address has been changed. + * @brief The Periodic Advertiser list has been configured. * @details - * When Resolvable Private Address Timeout in Controller has been updated by R_BLE_GAP_SetRpaTo(), + * When Periodic Advertiser List has been configured by R_BLE_GAP_ConfPerdAdvList(), * this event is notified to the application layer. * - * ## Event Code: 0x111F + * ## Event Code: 0x112B * * ## result: *
@@ -6888,24 +8880,48 @@ typedef enum * * BLE_ERR_INVALID_ARG(0x0003) * - * The rpa_timeout parameter specified by R_BLE_GAP_SetRpaTo() is out of range. + * The advertiser has already been registered in Periodic Advertiser List. + * + * + * + * BLE_ERR_INVALID_STATE(0x0008) + * + * The add or delete operation was called, before the previous clear operation has been completed. + * + * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * When establishing a periodic sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_ConfPerdAdvList() was called. + * + * + * + * BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * + * Periodic Advertiser List has already registered the maximum number of devices. + * + * + * + * BLE_ERR_INVALID_HDL(0x000E) + * + * The device specified by R_BLE_GAP_ConfPerdAdvList() was not found. * * * *
* * ## Event Data: - * none + * st_ble_gap_perd_list_conf_evt_t */ - BLE_GAP_EVENT_SET_RPA_TO_COMP, + BLE_GAP_EVENT_PERD_LIST_CONF_COMP, /** - * @brief The resolvable private address of local device has been retrieved. + * @brief Privacy Mode has been configured. * @details - * When the resolvable private address of local device has been retrieved by R_BLE_GAP_ReadRpa(), - * this event is notified to the application layer. + * This event notifies the application layer that the Privacy Mode has been configured by R_BLE_GAP_SetPrivMode(). * - * ## Event Code: 0x1120 + * ## Event Code: 0x112B * * ## result: *
@@ -6915,25 +8931,37 @@ typedef enum * Success * * + * BLE_ERR_INVALID_ARG(0x0003) + * Address type or privacy mode is out of range. + * + * + * BLE_ERR_INVALID_OPERATION(0x0009) + * + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_SetPrivMode() was called. + * + * + * * BLE_ERR_INVALID_HDL(0x000E) * - * The identity address specified by R_BLE_GAP_ReadRpa() was not registered in Resolving List. + * The address specified by R_BLE_GAP_SetPrivMode() has not been registered + * in Resolving List. * * * *
* * ## Event Data: - * st_ble_gap_rd_rpa_evt_t + * none */ - BLE_GAP_EVENT_RD_RPA_COMP, + BLE_GAP_EVENT_PRIV_MODE_SET_COMP, /** - * @brief PHY for connection has been changed. + * @brief The pairing request from a remote device has been received. * @details - * This event notifies the application layer that PHY for a connection has been updated. + * This event notifies the application layer that a pairing request from a remote device has been received. * - * ## Event Code: 0x1121 + * ## Event Code: 0x1401 * * ## result: *
@@ -6946,17 +8974,16 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_phy_upd_evt_t + * st_ble_gap_pairing_info_evt_t */ - BLE_GAP_EVENT_PHY_UPD, + BLE_GAP_EVENT_PAIRING_REQ = 0x1401, /** - * @brief The request for updating PHY for connection has been sent to Controller. + * @brief The request for input passkey has been received. * @details - * When Controller has received a request for updating PHY for a connection by R_BLE_GAP_SetPhy(), - * this event is notified to the application layer. + * This event notifies that a request for Passkey input in pairing has been received. * - * ## Event Code: 0x1122 + * ## Event Code: 0x1402 * * ## result: *
@@ -6965,27 +8992,20 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The remote device specified by R_BLE_GAP_SetPhy() was not found. - * - * * *
* * ## Event Data: * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_PHY_SET_COMP, + BLE_GAP_EVENT_PASSKEY_ENTRY_REQ, /** - * @brief The request for setting default PHY has been sent to Controller. + * @brief The request for displaying a passkey has been received. * @details - * When the PHY preferences which a remote device may change has been configured by R_BLE_GAP_SetDefPhy(), - * this event is notified to the application layer. + * This event notifies that a request for Passkey display in pairing has been received. * - * ## Event Code: 0x1123 + * ## Event Code: 0x1403 * * ## result: *
@@ -6998,17 +9018,16 @@ typedef enum *
* * ## Event Data: - * none + * st_ble_gap_passkey_display_evt_t */ - BLE_GAP_EVENT_DEF_PHY_SET_COMP, + BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ, /** - * @brief PHY configuration has been retrieved. + * @brief The request for confirmation with Numeric Comparison has received. * @details - * When the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(), - * this event is notified to the application layer. + * This event notifies that a request for Numeric Comparison in pairing has been received. * - * ## Event Code: 0x1124 + * ## Event Code: 0x1404 * * ## result: *
@@ -7017,26 +9036,20 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The link specified by R_BLE_GAP_ReadPhy() was not found. - * - * * *
* * ## Event Data: - * st_ble_gap_phy_rd_evt_t + * st_ble_gap_num_comp_evt_t */ - BLE_GAP_EVENT_PHY_RD_COMP, + BLE_GAP_EVENT_NUM_COMP_REQ, /** - * @brief Scan Request has been received. + * @brief Key Notification from a remote device has been received. * @details - * This event notifies the application layer that a Scan Request packet has been received from a Scanner. + * This event notifies the application layer that the remote device has input a key in Passkey Entry. * - * ## Event Code: 0x1125 + * ## Event Code: 0x1405 * * ## result: *
@@ -7049,17 +9062,16 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_scan_req_recv_evt_t + * st_ble_gap_key_press_ntf_evt_t */ - BLE_GAP_EVENT_SCAN_REQ_RECV, + BLE_GAP_EVENT_KEY_PRESS_NTF, /** - * @brief The request for establishing a periodic sync has been sent to Controller. + * @brief Pairing has been completed. * @details - * This event notifies the application layer that Controller has received a request - * for a Periodic Sync establishment. + * This event notifies the application layer that the pairing has completed. * - * ## Event Code: 0x1126 + * ## Event Code: 0x1406 * * ## result: *
@@ -7069,33 +9081,79 @@ typedef enum * Success * * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * When R_BLE_GAP_CreateSync() was called, - * this event for previous the API call has not been received. - * + * BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL(0x2001) + * PassKey Entry is failed. * * - * BLE_ERR_ALREADY_IN_PROGRESS(0x000A) - * - * The advertising set specified by R_BLE_GAP_CreateSync() has already established - * a periodic sync. - * + * BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE(0x2002) + * OOB Data is not available. + * + * + * BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET(0x2003) + * The requested pairing can not be performed because of IO Capability. + * + * + * BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH(0x2004) + * Confirmation value does not match. + * + * + * BLE_ERR_SMP_LE_PAIRING_NOT_SPRT(0x2005) + * Pairing is not supported. + * + * + * BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE(0x2006) + * Encryption Key Size is insufficient. + * + * + * BLE_ERR_SMP_LE_CMD_NOT_SPRT(0x2007) + * The pairing command received is not supported. + * + * + * BLE_ERR_SMP_LE_UNSPECIFIED_REASON(0x2008) + * Pairing failed with an unspecified reason. + * + * + * BLE_ERR_SMP_LE_REPEATED_ATTEMPTS(0x2009) + * The number of repetition exceeded the upper limit. + * + * + * BLE_ERR_SMP_LE_INVALID_PARAM(0x200A) + * Invalid parameter is set. + * + * + * BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL(0x200B) + * DHKey Check error. + * + * + * BLE_ERR_SMP_LE_NUM_COMP_FAIL(0x200C) + * Numeric Comparison failure. + * + * + * BLE_ERR_SMP_LE_DISCONNECTED(0x200F) + * Disconnection in pairing. + * + * + * BLE_ERR_SMP_LE_TO(0x2011) + * Failure due to timeout. + * + * + * BLE_ERR_SMP_LE_LOC_KEY_MISSING(0x2014) + * Pairing/Encryption failure because local device lost the LTK. * * *
* * ## Event Data: - * none + * st_ble_gap_pairing_info_evt_t */ - BLE_GAP_EVENT_CREATE_SYNC_COMP, + BLE_GAP_EVENT_PAIRING_COMP, /** - * @brief The periodic advertising sync has been established. + * @brief Key Notification from a remote device has been received. * @details - * This event notifies the application layer that a Periodic sync has been established. + * This event notifies the application layer that the encryption status of a link has been changed. * - * ## Event Code: 0x1127 + * ## Event Code: 0x1407 * * ## result: *
@@ -7104,27 +9162,20 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_NOT_YET_READY(0x0012) - * - * The request for a Periodic Sync establishment was cancelled by R_BLE_GAP_CancelCreateSync(). - * - * * *
* * ## Event Data: - * st_ble_gap_sync_est_evt_t + * st_ble_gap_enc_chg_evt_t */ - BLE_GAP_EVENT_SYNC_EST, + BLE_GAP_EVENT_ENC_CHG, /** - * @brief The periodic advertising sync has been terminated. + * @brief Keys has been received from a remote device. * @details - * This event notifies the application layer that the Periodic Sync has been terminated - * by R_BLE_GAP_TerminateSync(). + * This event notifies the application layer that the remote device has distributed the keys. * - * ## Event Code: 0x1128 + * ## Event Code: 0x1408 * * ## result: *
@@ -7133,33 +9184,21 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * While establishing a Periodic Sync by R_BLE_GAP_CreateSync(), - * R_BLE_GAP_TerminateSync() was called. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The sync handle specified by R_BLE_GAP_TerminateSync() was not found. - * - * * *
* * ## Event Data: - * st_ble_gap_sync_hdl_evt_t + * st_ble_gap_peer_key_info_evt_t */ - BLE_GAP_EVENT_SYNC_TERM, + BLE_GAP_EVENT_PEER_KEY_INFO, /** - * @brief The periodic advertising sync has been lost. + * @brief The request for key distribution has been received. * @details - * This event notifies the application layer that the Periodic Sync has been lost. + * When local device has been received a request for key distribution to remote device, + * this event is notified to the application layer. * - * ## Event Code: 0x1129 + * ## Event Code: 0x1409 * * ## result: *
@@ -7172,17 +9211,17 @@ typedef enum *
* * ## Event Data: - * st_ble_gap_sync_hdl_evt_t + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_SYNC_LOST, + BLE_GAP_EVENT_EX_KEY_REQ, /** - * @brief The request for cancel of establishing a periodic advertising sync has been sent to Controller. + * @brief LTK has been request from a remote device. * @details - * This event notifies the request for a Periodic Sync establishment has been cancelled - * by R_BLE_GAP_CancelCreateSync(). + * When local device has been received a LTK request from a remote device, + * this event is notified to the application layer. * - * ## Event Code: 0x112A + * ## Event Code: 0x140A * * ## result: *
@@ -7191,29 +9230,21 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * When R_BLE_GAP_CancelCreateSync() was called, - * a request for a Periodic Sync establishment by R_BLE_GAP_CreateSync() - * has not been sent to Controller. - * - * * *
* * ## Event Data: - * none + * st_ble_gap_ltk_req_evt_t */ - BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP, + BLE_GAP_EVENT_LTK_REQ, /** - * @brief The Periodic Advertiser list has been configured. + * @brief LTK reply has been sent to Controller. * @details - * When Periodic Advertiser List has been configured by R_BLE_GAP_ConfPerdAdvList(), + * When local device has replied to the LTK request from the remote device, * this event is notified to the application layer. * - * ## Event Code: 0x112B + * ## Event Code: 0x140B * * ## result: *
@@ -7222,51 +9253,20 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_ARG(0x0003) - * - * The advertiser has already been registered in Periodic Advertiser List. - * - * - * - * BLE_ERR_INVALID_STATE(0x0008) - * - * The add or delete operation was called, before the previous clear operation has been completed. - * - * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * When establishing a periodic sync by R_BLE_GAP_CreateSync(), - * R_BLE_GAP_ConfPerdAdvList() was called. - * - * - * - * BLE_ERR_MEM_ALLOC_FAILED(0x000C) - * - * Periodic Advertiser List has already registered the maximum number of devices. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The device specified by R_BLE_GAP_ConfPerdAdvList() was not found. - * - * * *
* * ## Event Data: - * st_ble_gap_perd_list_conf_evt_t + * st_ble_gap_ltk_rsp_evt_t */ - BLE_GAP_EVENT_PERD_LIST_CONF_COMP, + BLE_GAP_EVENT_LTK_RSP_COMP, /** - * @brief Privacy Mode has been configured. + * @brief The authentication data to be used in Secure Connections OOB has been created. * @details - * This event notifies the application layer that the Privacy Mode has been configured by R_BLE_GAP_SetPrivMode(). + * This event notifies OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). * - * ## Event Code: 0x112B + * ## Event Code: 0x140C * * ## result: *
@@ -7275,359 +9275,547 @@ typedef enum * BLE_SUCCESS(0x0000) * Success * - * - * BLE_ERR_INVALID_ARG(0x0003) - * Address type or privacy mode is out of range. - * - * - * BLE_ERR_INVALID_OPERATION(0x0009) - * - * While advertising, scanning, or establishing a link with resolvable private address, - * R_BLE_GAP_SetPrivMode() was called. - * - * - * - * BLE_ERR_INVALID_HDL(0x000E) - * - * The address specified by R_BLE_GAP_SetPrivMode() has not been registered - * in Resolving List. - * - * * *
* - * ## Event Data: - * none + * ## Event Data: + * st_ble_gap_sc_oob_data_evt_t + */ + BLE_GAP_EVENT_SC_OOB_CREATE_COMP, + + /** + * @brief An connectionless CTE IQ sample is reported. + * + * ## result + * 0x0000 Response without CTE info + * other Rejected by remote peer + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_CTE_CONN_REQ_FAILED, + + /** + * @brief An connectionless CTE IQ sample is reported. + * + * ## Event Data: + * st_ble_gap_cte_connless_rept_t + */ + BLE_GAP_EVENT_CTE_CONNLESS_REPT, + + /** + * @brief An connection CTE IQ sample is reported. + * + * ## Event Data: + * st_ble_gap_cte_conn_rept_t + */ + BLE_GAP_EVENT_CTE_CONN_REPT, + + /** + * @brief a Connection Subrate Update procedure has completed and + * some parameters of the specified connection have changed. + * + * ## Event Data: + * st_ble_subrate_upd_t + */ + BLE_GAP_EVENT_SUBRATE_CHANGE, + + /** + * @brief This event notifies that it has received periodic advertising synchronization + * information from the device referred to by the Connection_Handle parameter + * ## Event Data: + * st_ble_gap_past_est_evt_t + */ + BLE_GAP_EVENT_PAST_RECV, + + /** + * @brief Transmit power level report. + * @details + * This event is a report of the transmit power level on the ACL connection identified by the conn_hdl + * + * ## Event Data: + * st_ble_gap_tx_power_reporting_evt_t + */ + BLE_GAP_EVENT_TX_POWER_REPT, + + /** + * @brief Report a path loss threshold crossing on + * the ACL connection identified by the Connection_Handle parameter. + * + * ## Event Data: + * st_ble_gap_pass_loss_thr_evt_t + */ + BLE_GAP_EVENT_PATH_LOSS_THR, + + /** + * @brief Indicates that the HCI_LE_Request_Peer_SCA command has been completed. + * ## Event Data: + * st_ble_gap_req_peer_sca_evt_t + */ + BLE_GAP_EVENT_REQ_PEER_SCA_COMP, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_CTE_SET_CONNLESS_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_CTE_CONNLESS_TX_ON, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_CTE_CONNLESS_TX_OFF, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_CONNLESS_RX_ON, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_CONNLESS_RX_OFF, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_SET_CONN_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_SET_CONN_RSP_ON, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_SET_CONN_RSP_OFF, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_SET_CONN_RECV_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_CONN_REQ_ON, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_CTE_CONN_REQ_OFF, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_SET_DEF_SUBRATE_COMP, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_REQ_SUBRATE_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PAST_START_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PAST_SET_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PAST_SET_DEF_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_UPD_SCA_COMP, + + /** + * @brief + * + * ## Event Data: + * None + */ + BLE_GAP_EVENT_READ_REMOTE_TX_POWER_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_SET_PATHLOSS_REPT_PARAM_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_PRIV_MODE_SET_COMP, + BLE_GAP_EVENT_PATHLOSS_REPT_ON, /** - * @brief The pairing request from a remote device has been received. - * @details - * This event notifies the application layer that a pairing request from a remote device has been received. + * @brief * - * ## Event Code: 0x1401 + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PATHLOSS_REPT_OFF, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_LOCAL_TX_POWER_REPT_ON, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_pairing_info_evt_t + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_PAIRING_REQ = 0x1401, + BLE_GAP_EVENT_LOCAL_TX_POWER_REPT_OFF, /** - * @brief The request for input passkey has been received. - * @details - * This event notifies that a request for Passkey input in pairing has been received. + * @brief * - * ## Event Code: 0x1402 + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_REMOTE_TX_POWER_REPT_ON, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_REMOTE_TX_POWER_REPT_OFF, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_conn_hdl_evt_t + * ## Event Data: + * None */ - BLE_GAP_EVENT_PASSKEY_ENTRY_REQ, + BLE_GAP_EVENT_SET_RPA_UPD_REASON_COMP, /** - * @brief The request for displaying a passkey has been received. - * @details - * This event notifies that a request for Passkey display in pairing has been received. + * @brief * - * ## Event Code: 0x1403 + * ## Event Data: + * None + */ + BLE_GAP_EVENT_DTM_RX_TEST_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * None + */ + BLE_GAP_EVENT_DTM_TX_TEST_COMP, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_passkey_display_evt_t + * ## Event Data: + * st_ble_gap_dtm_test_end_evt_t */ - BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ, + BLE_GAP_EVENT_DTM_TEST_END_COMP, /** - * @brief The request for confirmation with Numeric Comparison has received. - * @details - * This event notifies that a request for Numeric Comparison in pairing has been received. + * @brief * - * ## Event Code: 0x1404 + * ## Event Data: + * st_ble_gap_enhanced_read_tx_power_level_evt_t + */ + BLE_GAP_EVENT_ENHANCED_READ_TX_POWER_LEVEL_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * None + */ + BLE_GAP_EVENT_SET_HOST_FEAT_COMP, +} e_ble_gap_evt_t; + +/*@}*/ + +/* ================================================= ISO Event Code ================================================= */ + +/** @addtogroup ISO_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @enum e_ble_iso_evt_t + * @brief ISO Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief R_BLE_ISO_CreateBig() created a big successfully. + * @details * * ## Event Data: - * st_ble_gap_num_comp_evt_t + * st_ble_iso_big_comp_evt_t */ - BLE_GAP_EVENT_NUM_COMP_REQ, + BLE_ISO_EVENT_CREATE_BIG_COMP = 0x1500, /** - * @brief Key Notification from a remote device has been received. + * @brief Big Info is detected in a periodic adv data. * @details - * This event notifies the application layer that the remote device has input a key in Passkey Entry. - * - * ## Event Code: 0x1405 - * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
* * ## Event Data: - * st_ble_gap_key_press_ntf_evt_t + * st_ble_iso_biginfo_rept_evt_t */ - BLE_GAP_EVENT_KEY_PRESS_NTF, + BLE_ISO_EVENT_BIGINFO_REPT, /** - * @brief Pairing has been completed. + * @brief The sync-id specified by R_BLE_ISO_CreateBigSync() has already established + * a big sync. * @details - * This event notifies the application layer that the pairing has completed. * - * ## Event Code: 0x1406 * - * ## result: - *
- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL(0x2001)PassKey Entry is failed.
BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE(0x2002)OOB Data is not available.
BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET(0x2003)The requested pairing can not be performed because of IO Capability.
BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH(0x2004)Confirmation value does not match.
BLE_ERR_SMP_LE_PAIRING_NOT_SPRT(0x2005)Pairing is not supported.
BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE(0x2006)Encryption Key Size is insufficient.
BLE_ERR_SMP_LE_CMD_NOT_SPRT(0x2007)The pairing command received is not supported.
BLE_ERR_SMP_LE_UNSPECIFIED_REASON(0x2008)Pairing failed with an unspecified reason.
BLE_ERR_SMP_LE_REPEATED_ATTEMPTS(0x2009)The number of repetition exceeded the upper limit.
BLE_ERR_SMP_LE_INVALID_PARAM(0x200A)Invalid parameter is set.
BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL(0x200B)DHKey Check error.
BLE_ERR_SMP_LE_NUM_COMP_FAIL(0x200C)Numeric Comparison failure.
BLE_ERR_SMP_LE_DISCONNECTED(0x200F)Disconnection in pairing.
BLE_ERR_SMP_LE_TO(0x2011) Failure due to timeout.
BLE_ERR_SMP_LE_LOC_KEY_MISSING(0x2014)Pairing/Encryption failure because local device lost the LTK.
- *
+ * st_ble_iso_big_comp_evt_t + * */ + BLE_ISO_EVENT_CREATE_BIG_SYNC_COMP, + + /** + * @brief An ISO SDU is received. + * @details * * ## Event Data: - * st_ble_gap_pairing_info_evt_t + * st_ble_iso_sdu_t */ - BLE_GAP_EVENT_PAIRING_COMP, + BLE_ISO_EVENT_ISO_RX_DATA_IND, /** - * @brief Key Notification from a remote device has been received. + * @brief An ISO SDU is sent. * @details - * This event notifies the application layer that the encryption status of a link has been changed. * - * ## Event Code: 0x1407 + * ## Event Data: + * st_ble_iso_tx_comp_evt_t + */ + BLE_ISO_EVENT_ISO_TX_COMP, + + /** + * @brief This event notifies the application layer that the ISO sync has failed. * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_iso_group_hdl_evt_t + */ + BLE_ISO_EVENT_SYNC_LOST, + + /** + * @brief This event notifies the application layer that the BIG sync has been terminated * - * ## Event Data: - * st_ble_gap_enc_chg_evt_t + * ## Event Data: + * st_ble_iso_group_hdl_evt_t */ - BLE_GAP_EVENT_ENC_CHG, + BLE_ISO_EVENT_SYNC_TERM, /** - * @brief Keys has been received from a remote device. - * @details - * This event notifies the application layer that the remote device has distributed the keys. + * @brief The request for CIG setting parameter has been sent to Controller. * - * ## Event Code: 0x1408 + * ## Event Data: + * st_ble_iso_cig_set_evt_t + */ + BLE_ISO_EVENT_CIG_PARAM_SET_COMP, + + /** + * @brief The CIS request has been received from to remote device. * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_iso_cis_req_evt_t + */ + BLE_ISO_EVENT_CIS_REQ, + + /** + * @brief An CIS connection is estabilished. * - * ## Event Data: - * st_ble_gap_peer_key_info_evt_t + * ## Event Data: + * st_ble_iso_cis_est_evt_t */ - BLE_GAP_EVENT_PEER_KEY_INFO, + BLE_ISO_EVENT_CIS_EST, /** - * @brief The request for key distribution has been received. - * @details - * When local device has been received a request for key distribution to remote device, - * this event is notified to the application layer. + * @brief * - * ## Event Code: 0x1409 + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_ISO_EVENT_SETUP_DATA_PATH_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_iso_group_hdl_evt_t + */ + BLE_ISO_EVENT_CIG_REMOVE_COMP, + + /** + * @brief + * + * ## Event Data: + * st_ble_iso_group_hdl_evt_t + */ + BLE_ISO_EVENT_BIG_REMOVE_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_ISO_EVENT_REPLY_CIS_REQ_COMP, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_conn_hdl_evt_t + * ## Event Data: + * st_ble_iso_tx_sync_info_t */ - BLE_GAP_EVENT_EX_KEY_REQ, + BLE_ISO_EVENT_GET_TX_SYNC_COMP, /** - * @brief LTK has been request from a remote device. - * @details - * When local device has been received a LTK request from a remote device, - * this event is notified to the application layer. + * @brief * - * ## Event Code: 0x140A + * ## Event Data: + * st_ble_gap_cte_antenna_info_t + */ + BLE_ISO_EVENT_READ_ANT_INFO_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_ISO_EVENT_TX_TEST_COMP, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_ltk_req_evt_t + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t */ - BLE_GAP_EVENT_LTK_REQ, + BLE_ISO_EVENT_RX_TEST_COMP, /** - * @brief LTK reply has been sent to Controller. - * @details - * When local device has replied to the LTK request from the remote device, - * this event is notified to the application layer. + * @brief * - * ## Event Code: 0x140B + * ## Event Data: + * st_ble_iso_test_cnt_info_t + */ + BLE_ISO_EVENT_READ_TEST_CNT_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * st_ble_iso_test_end_rept_t + */ + BLE_ISO_EVENT_TEST_ENDED, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_ltk_rsp_evt_t + * ## Event Data: + * st_ble_iso_link_quality_info_t */ - BLE_GAP_EVENT_LTK_RSP_COMP, + BLE_ISO_EVENT_READ_LINK_QUALITY_COMP, /** - * @brief The authentication data to be used in Secure Connections OOB has been created. - * @details - * This event notifies OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + * @brief * - * ## Event Code: 0x140C + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_ISO_EVENT_REMOVE_DATAPATH_COMP, + + /** + * @brief * - * ## result: - *
- * - * - * - * - * - *
BLE_SUCCESS(0x0000)Success
- *
+ * ## Event Data: + * None + */ + BLE_ISO_EVENT_PER_ADV_RECV_ON, + + /** + * @brief * - * ## Event Data: - * st_ble_gap_sc_oob_data_evt_t + * ## Event Data: + * None */ - BLE_GAP_EVENT_SC_OOB_CREATE_COMP, -} e_ble_gap_evt_t; + BLE_ISO_EVENT_PER_ADV_RECV_OFF, +} e_ble_iso_evt_t; /*@}*/ @@ -7644,7 +9832,7 @@ typedef enum * @struct st_ble_gatt_value_t * @brief Attribute Value. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Length of the attribute value. @@ -7663,7 +9851,7 @@ typedef struct * @struct st_ble_gatt_hdl_value_pair_t * @brief Attribute handle and attribute Value. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Handle @@ -7680,7 +9868,7 @@ typedef struct * @struct st_ble_gatt_queue_att_val_t * @brief Queued writes Attribute Value. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Value for Queued Write . @@ -7702,7 +9890,7 @@ typedef struct * @struct st_ble_gatt_queue_pair_t * @brief Queued writes Attribute Value. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Value for Queued Write @@ -7719,7 +9907,7 @@ typedef struct * @struct st_ble_gatt_queue_elm_t * @brief Prepare Write Queue element for long chracteristic. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Part of Long Characteristic Value and Characteristic Value Handle. @@ -7736,7 +9924,7 @@ typedef struct * @struct st_ble_gatt_pre_queue_t * @brief Prepare Write Queue for long chracteristic. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Buffer start address for Write Long Characteristic Request. @@ -7778,7 +9966,7 @@ typedef struct * @struct st_ble_gatts_db_params_t * @brief Attribute value to be set to or retrieved from the GATT Database and the access type from the GATT Client. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute value to be set to or retrieved from the GATT Database. @@ -7802,7 +9990,7 @@ typedef struct * @struct st_ble_gatts_db_conn_hdl_t * @brief Information about the service or the characteristic that the attribute belongs to. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle identifying the GATT Client that accesses to the GATT DataBase. @@ -7824,7 +10012,7 @@ typedef struct * @struct st_ble_gatts_db_access_evt_t * @brief This structure notifies that the GATT Database has been accessed from a GATT Client. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Information about the service or the characteristic that the attribute belongs to. @@ -7842,7 +10030,7 @@ typedef struct * @struct st_ble_gatts_conn_evt_t * @brief This structure notifies that the link with the GATT Client has been established. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Address of the GATT Client. @@ -7854,7 +10042,7 @@ typedef struct * @struct st_ble_gatts_disconn_evt_t * @brief This structure notifies that the link with the GATT Client has been disconnected. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Address of the GATT Client. @@ -7866,7 +10054,7 @@ typedef struct * @struct st_ble_gatts_ex_mtu_req_evt_t * @brief This structure notifies that a MTU Exchange Request PDU has been received from a GATT Client. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Maximum receive MTU size by GATT Client. @@ -7878,7 +10066,7 @@ typedef struct * @struct st_ble_gatts_cfm_evt_t * @brief This structure notifies that a Confirmation PDU has been received from a GATT Client. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic sent by the Indication PDU. @@ -7890,7 +10078,7 @@ typedef struct * @struct st_ble_gatts_read_by_type_rsp_evt_t * @brief This structure notifies that a Read By Type Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic read by the Read By Type Request PDU. @@ -7902,7 +10090,7 @@ typedef struct * @struct st_ble_gatts_read_rsp_evt_t * @brief This structure notifies that a Read Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic read by the Read Request PDU. @@ -7914,7 +10102,7 @@ typedef struct * @struct st_ble_gatts_read_blob_rsp_evt_t * @brief This structure notifies that a Read Blob Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic read by the Read Blob Request PDU. @@ -7926,7 +10114,7 @@ typedef struct * @struct st_ble_gatts_read_multi_rsp_evt_t * @brief This structure notifies that a Read Multiple Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The number of attribute read by the Read Multiple Request PDU. @@ -7943,7 +10131,7 @@ typedef struct * @struct st_ble_gatts_write_rsp_evt_t * @brief This structure notifies that a Write Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic written by the Write Request PDU. @@ -7955,7 +10143,7 @@ typedef struct * @struct st_ble_gatts_prepare_write_rsp_evt_t * @brief This structure notifies that a Prepare Write Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle identifying the Characteristic written by the Prepare Write Request PDU. @@ -7977,7 +10165,7 @@ typedef struct * @struct st_ble_gatts_exe_write_rsp_evt_t * @brief This structure notifies that a Execute Write Response PDU has been sent from GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The flag that indicates whether execution or cancellation. @@ -7996,7 +10184,7 @@ typedef struct * @struct st_ble_gatts_db_uuid_cfg_t * @brief A structure that defines the information on the position where UUIDs are used. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The position of the defined UUID is specified by offset value in uuid_table of st_ble_gatts_db_cfg_t. @@ -8020,7 +10208,7 @@ typedef struct * @struct st_ble_gatts_db_attr_cfg_t * @brief A structure that defines the detailed information of the attributes. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The properties of attribute are specified. @@ -8122,7 +10310,7 @@ typedef struct * @struct st_ble_gatts_db_attr_list_t * @brief The number of attributes are stored. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The number of the services or the characteristics. @@ -8134,7 +10322,7 @@ typedef struct * @struct st_ble_gatts_db_char_cfg_t * @brief A structure that defines the detailed information of the characteristics. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The total number of attributes in the defined characteristic is specified. @@ -8156,7 +10344,7 @@ typedef struct * @struct st_ble_gatts_db_serv_cfg_t * @brief A structure that defines the detailed information of the characteristics. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The total number of service declarations in the defined service is specified. @@ -8290,7 +10478,7 @@ typedef struct * @struct st_ble_gatts_db_cfg_t * @brief This is the structure of GATT Database that is specified in R_BLE_GATTS_SetDbInst(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The array to register the UUID to be used. @@ -8362,7 +10550,7 @@ typedef struct * @struct st_ble_gatts_evt_data_t * @brief st_ble_gatts_evt_data_t is the type of the data notified in a GATT Server Event. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle identifying the GATT Client. @@ -8405,7 +10593,7 @@ typedef void (* ble_gatts_app_cb_t)(uint16_t event_type, ble_status_t event_resu * @struct st_ble_gatt_hdl_range_t * @brief Attribute handle range. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Start Attribute Handle. @@ -8424,7 +10612,7 @@ typedef struct * @brief This is used in R_BLE_GATTC_ReliableWrites() to specify the pair of Characteristic Value and * Characteristic Value Handle. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Pair of Characteristic Value and Characteristic Value Handle. @@ -8444,7 +10632,7 @@ typedef struct * @struct st_ble_gattc_conn_evt_t * @brief This structure notifies that the link with the GATT Server has been established. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Address of the GATT Server. @@ -8456,7 +10644,7 @@ typedef struct * @struct st_ble_gattc_disconn_evt_t * @brief This structure notifies that the link with the GATT Server has been disconnected. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Address of the GATT Server. @@ -8468,7 +10656,7 @@ typedef struct * @struct st_ble_gattc_ex_mtu_rsp_evt_t * @brief This structure notifies that a MTU Exchange Response PDU has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief MTU size(in bytes) that GATT Server can receive. @@ -8480,7 +10668,7 @@ typedef struct * @struct st_ble_gattc_serv_16_evt_t * @brief This structure notifies that a 16-bit UUID Service has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle range of the 16-bit UUID service. @@ -8497,7 +10685,7 @@ typedef struct * @struct st_ble_gattc_serv_128_evt_t * @brief This structure notifies that a 128-bit UUID Service has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle range of the 128-bit UUID service. @@ -8514,7 +10702,7 @@ typedef struct * @struct st_ble_gattc_inc_serv_16_evt_t * @brief This structure notifies that a 16-bit UUID Included Service has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Service Declaration handle of the 16-bit UUID Included Service. @@ -8531,7 +10719,7 @@ typedef struct * @struct st_ble_gattc_inc_serv_128_evt_t * @brief This structure notifies that a 128-bit UUID Included Service has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Service Declaration handle of the 128-bit UUID Included Service. @@ -8548,7 +10736,7 @@ typedef struct * @struct st_ble_gattc_char_16_evt_t * @brief This structure notifies that a 16-bit UUID Characteristic has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute handle of Characteristic Declaration. @@ -8588,7 +10776,7 @@ typedef struct * @struct st_ble_gattc_char_128_evt_t * @brief This structure notifies that a 128-bit UUID Characteristic has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Handle of Characteristic Declaration. @@ -8628,7 +10816,7 @@ typedef struct * @struct st_ble_gattc_char_desc_16_evt_t * @brief This structure notifies that a 16-bit UUID Characteristic Descriptor has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Handle of Characteristic Descriptor. @@ -8645,7 +10833,7 @@ typedef struct * @struct st_ble_gattc_char_desc_128_evt_t * @brief This structure notifies that a 128-bit UUID Characteristic Descriptor has been discovered. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Attribute Handle of Characteristic Descriptor. @@ -8662,7 +10850,7 @@ typedef struct * @struct st_ble_gattc_err_rsp_evt_t * @brief This structure notifies that a Error Response PDU has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The op code of the ATT Request that causes the Error Response. @@ -8809,7 +10997,7 @@ typedef struct * @struct st_ble_gattc_ntf_evt_t * @brief This structure notifies that a Notification PDU has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Characteristic that causes the Notification. @@ -8821,7 +11009,7 @@ typedef struct * @struct st_ble_gattc_ind_evt_t * @brief This structure notifies that a Indication PDU has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Characteristic that causes the Indication. @@ -8834,7 +11022,7 @@ typedef struct * @brief This structure notifies that read response to R_BLE_GATTC_ReadChar() or R_BLE_GATTC_ReadCharUsingUuid() * has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The contents of the Characteristic that has been read. @@ -8846,7 +11034,7 @@ typedef struct * @struct st_ble_gattc_wr_char_evt_t * @brief This structure notifies that write response to R_BLE_GATTC_WriteChar() has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Value Handle of the Characteristic/Characteristic Descriptor that has been written. @@ -8859,7 +11047,7 @@ typedef struct * @brief This structure notifies that read response to R_BLE_GATTC_ReadMultiChar() has been received * from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The number of Value Handles of the Characteristics that has been read. @@ -8877,7 +11065,7 @@ typedef struct * @brief This structure notifies that write response to R_BLE_GATTC_WriteLongChar() or R_BLE_GATTC_ReliableWrites() * has been received from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The data to be written to the Characteristic/Long Characteristic/Long Characteristic Descriptor. @@ -8895,7 +11083,7 @@ typedef struct * @brief This structure notifies that a response to R_BLE_GATTC_ExecWrite() has been received * from a GATT Server. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief This field indicates the command of the Execute Write that has been done. @@ -8914,7 +11102,7 @@ typedef struct * @struct st_ble_gattc_rd_multi_req_param_t * @brief This is used in R_BLE_GATTC_ReadMultiChar() to specify multiple Characteristics to be read. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief List of Value Handles that point the Characteristics to be read. @@ -8931,7 +11119,7 @@ typedef struct * @struct st_ble_gattc_evt_data_t * @brief st_ble_gattc_evt_data_t is the type of the data notified in a GATT Client Event. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle identifying the GATT Server. @@ -8974,7 +11162,7 @@ typedef void (* ble_gattc_app_cb_t)(uint16_t event_type, ble_status_t event_resu * @struct st_ble_l2cap_conn_req_param_t * @brief L2CAP CBFC Channel connection request parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on local device. @@ -9006,7 +11194,7 @@ typedef struct * @struct st_ble_l2cap_conn_rsp_param_t * @brief L2CAP CBFC Channel connection response parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief CID identifying the L2CAP CBFC Channel on local device. @@ -9074,7 +11262,7 @@ typedef struct * @struct st_ble_l2cap_cf_conn_evt_t * @brief L2CAP CBFC Channel connection parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief CID identifying the L2CAP CBFC Channel. @@ -9106,7 +11294,7 @@ typedef struct * @struct st_ble_l2cap_cf_data_evt_t * @brief Sent/Received Data parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief CID identifying the L2CAP CBFC Channel that has sent or received the data . @@ -9133,7 +11321,7 @@ typedef struct * @struct st_ble_l2cap_cf_credit_evt_t * @brief Credit parameters of local or remote device. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief CID identifying the L2CAP CBFC Channel. @@ -9155,7 +11343,7 @@ typedef struct * @struct st_ble_l2cap_cf_disconn_evt_t * @brief Disconnection parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief CID identifying the L2CAP CBFC Channel that has been disconnected. @@ -9167,7 +11355,7 @@ typedef struct * @struct st_ble_l2cap_rej_evt_t * @brief Command Reject parameters. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The reason that the remote device has sent Command Reject. @@ -9189,7 +11377,7 @@ typedef struct * @struct st_ble_l2cap_cf_evt_data_t * @brief st_ble_l2cap_cf_evt_data_t is the type of the data notified in a L2CAP Event. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle identifying the remote device. @@ -9490,7 +11678,7 @@ typedef enum * @struct st_ble_vs_tx_test_param_t * @brief This is the extended transmitter test parameters used in R_BLE_VS_StartTxTest(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Channel used in Tx test. @@ -9532,7 +11720,7 @@ typedef struct * @struct st_ble_vs_rx_test_param_t * @brief This is the extended receiver test parameters used in R_BLE_VS_StartRxTest(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Channel used in Rx test. @@ -9549,7 +11737,7 @@ typedef struct * @struct st_ble_vs_set_rf_ctrl_param_t * @brief This is the RF parameters used in R_BLE_VS_SetRfControl(). **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief RF power on/off. @@ -9586,7 +11774,7 @@ typedef struct * @struct st_ble_vs_test_end_evt_t * @brief This structure notifies that the extended test has been terminated. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The number of packet successfully received in the receiver test. @@ -9618,7 +11806,7 @@ typedef struct * @struct st_ble_vs_set_tx_pwr_comp_evt_t * @brief This structure notifies that tx power has been set. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle that identifying the link whose tx power has been set. @@ -9635,7 +11823,7 @@ typedef struct * @struct st_ble_vs_get_tx_pwr_comp_evt_t * @brief This structure notifies that tx power has been retrieved. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Connection handle that identifying the link whose tx power has been retrieved. @@ -9657,7 +11845,7 @@ typedef struct * @struct st_ble_vs_set_rf_ctrl_comp_evt_t * @brief This structure notifies that RF has been configured. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The result of RF power control. @@ -9669,7 +11857,7 @@ typedef struct * @struct st_ble_vs_get_bd_addr_comp_evt_t * @brief This structure notifies that BD_ADDR has been retrieved. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The area that public/random address has been retrieved. @@ -9690,7 +11878,7 @@ typedef struct * @struct st_ble_vs_get_rand_comp_evt_t * @brief This structure notifies that random number has been generated. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief Length of random number. @@ -9707,7 +11895,7 @@ typedef struct * @struct st_ble_vs_tx_flow_chg_evt_t * @brief This structure notifies that the state transition of TxFlow has been changed. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The state of the flow control. @@ -9728,7 +11916,7 @@ typedef struct * @struct st_ble_vs_evt_data_t * @brief st_ble_vs_evt_data_t is the type of the data notified in a Vendor Specific Event. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The size of Vendor Specific Event parameters. @@ -9745,7 +11933,7 @@ typedef struct * @struct st_ble_vs_get_scan_ch_map_comp_evt_t * @brief This structure notifies that current scan channel map. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The result of current scan channel map. @@ -9757,7 +11945,7 @@ typedef struct * @struct st_ble_vs_get_fw_version_comp_evt_t * @brief This structure notifies the current firmware version. **********************************************************************************************************************/ -typedef struct +typedef struct BLE_PACKED_OPTION { /** * @brief The result of get firmware version. @@ -10337,7 +12525,6 @@ typedef void (* ble_app_init_cb_t)(uint8_t param); * @ingroup BLE_API * @typedef ble_event_cb_t * @brief ble_event_cb_t is the callback function type for R_BLE_SetEvent(). - * @param[in] void * @return none **********************************************************************************************************************/ typedef void (* ble_event_cb_t)(void); @@ -11627,8 +13814,572 @@ void R_BLE_GAP_DeleteBondInfo(int32_t local, **********************************************************************************************************************/ ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, uint16_t ediv, uint8_t * p_peer_rand, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetCteConnlessParam(st_ble_gap_cte_connless_t * cte_param) + * @brief Set the parameters for the transmission of Constant Tone Extensions in any periodic advertising. + * @param[in] cte_param parameters of type, length, and antenna switching pattern. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetCteConnlessParam(st_ble_gap_cte_connless_t * cte_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_EnableCteConnless(uint16_t adv_hdl, uint8_t enable) + * @brief Enable or disable Constant Tone Extensions in periodic advertising identified by the adv_hdl. + * @param[in] adv_hdl handle of the periodic advertising which carries the CTE info. + * @param[in] enable Enable or disable address resolution function. + * | macro | description | + * |:------------------------------- |:----------------------------------------- | + * | BLE_GAP_CTE_DISABLED(0x00) | Disable connectionless CTE transmission | + * | BLE_GAP_CTE_ENABLED(0x01) | Enable connectionless CTE transmission | + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_EnableCteConnless(uint16_t adv_hdl, uint8_t enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartCteConnlessRecv(st_ble_gap_cte_connless_recv_t * p_cte_recv) + * @brief Enable sampling received Constant Tone Extension fields. + * @details Application should receive BLE_GAP_EVENT_CTE_CONNLESS_REPT event. + * @param[in] p_cte_recv antenna switching pattern and switching and sampling slot durations to be used. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartCteConnlessRecv(st_ble_gap_cte_connless_recv_t * p_cte_recv); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopCteConnlessRecv(uint16_t sync_hdl) + * @brief Disable sampling received Constant Tone Extension fields + * @param[in] sync_hdl handle of the periodic advertising sync which carries the CTE info. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopCteConnlessRecv(uint16_t sync_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetCteConnParam(st_ble_gap_cte_conn_t * p_cte_param) + * @brief Set the parameters for the transmission of Constant Tone Extensions in ACL link. + * @param[in] p_cte_param parameters of type, length, and antenna switching pattern. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetCteConnParam(st_ble_gap_cte_conn_t * p_cte_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_EnableCteConnRsp(uint16_t conn_hdl, uint8_t enable) + * @brief Enable or disable Constant Tone Extensions Transmission in ACL link by conn_hdl. + * @param[in] conn_hdl handle of the ACL link which carries the CTE info. + * @param[in] enable Enable or disable address resolution function. + * | macro | description | + * |:------------------------------- |:----------------------------------------- | + * | BLE_GAP_CTE_DISABLED(0x00) | Disable connectionless CTE transmission | + * | BLE_GAP_CTE_ENABLED(0x01) | Enable connectionless CTE transmission | + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_EnableCteConnRsp(uint16_t conn_hdl, uint8_t enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetCteConnRecvParam(st_ble_gap_cte_conn_rx_param_t * p_cte_param) + * @brief Set the parameters for the receiving of Constant Tone Extensions in ACL link. + * and start sampling. + * @param[in] p_cte_param parameters of type, length, and antenna switching pattern. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetCteConnRecvParam(st_ble_gap_cte_conn_rx_param_t * p_cte_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopCteConnRecvSampling(uint16_t conn_hdl) + * @brief Stop sampling of Constant Tone Extensions on the specified connection. + * @param[in] conn_hdl handle of the ACL link which carries the CTE info. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopCteConnRecvSampling(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartCteConnReq(st_ble_gap_cte_conn_req_t * p_req) + * @brief Set the parameters and start sending request of Constant Tone Extensions in ACL link to peer. + * @details If the request does not receive a CTE Response PDU with CTE info, BLE_GAP_EVENT_CTE_CONN_REQ_FAILED + * event is sent to application. Otherwise application should receive BLE_GAP_EVENT_CTE_CONN_REPT event. + * @param[in] p_req parameters connection CTE request. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartCteConnReq(st_ble_gap_cte_conn_req_t * p_req); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopCteConnReq(uint16_t handle) + * @brief Stop sending request of Constant Tone Extensions in ACL link to peer. + * @param[in] handle handle of the ACL link which carries the CTE info. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopCteConnReq(uint16_t handle); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDefaultSubrate(st_ble_gap_subrate_param_t * p_subrate_param) + * @brief Set the initial values for the acceptable parameters for subrating requests, + * @param[in] p_subrate_param default parameters of subrate. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDefaultSubrate(st_ble_gap_subrate_param_t * p_subrate_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_RequestSubrate(uint16_t conn_hdl, st_ble_gap_subrate_param_t * p_subrate_param) + * @brief Request a change to the subrating factor other parameters applied to an existing connection + * using the Connection Subrate Update procedure. + * @param[in] conn_hdl handle of the ACL link which carries the CTE info. + * @param[in] p_subrate_param request parameters of subrate. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_RequestSubrate(uint16_t conn_hdl, st_ble_gap_subrate_param_t * p_subrate_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPerdAdvSetInfoTransfer(uint16_t adv_hdl, uint16_t conn_hdl, uint16_t service_data) + * @brief This function starts Periodic advertising adv set info transfer to the connection. + * @details Send synchronization information about the periodic advertising in an advertising set to a connected device. + * @param[in] adv_hdl Identifies the advertising set. + * @param[in] conn_hdl Connection handle identifying the remote device. + * @param[in] service_data A value provided by the application for use by the application of the peer device. + * @retval BLE_SUCCESS(0x0000) Success + * + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPerdAdvSetInfoTransfer(uint16_t adv_hdl, uint16_t conn_hdl, uint16_t service_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPerdAdvSyncTransfer(uint16_t sync_hdl, uint16_t conn_hdl, uint16_t service_data) + * @brief This function starts Periodic advertising sync transfer. + * @details send synchronization information about the periodic advertising train identified by the Sync_Handle parameter + * to a connected device. + * @param[in] sync_hdl Sync handle identifying the Periodic Sync that has been established. + * @param[in] conn_hdl Connection handle identifying the remote device. + * @param[in] service_data A value provided by the application for use by the application of the peer device. + * @retval BLE_SUCCESS(0x0000) Success + * + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPerdAdvSyncTransfer(uint16_t sync_hdl, uint16_t conn_hdl, uint16_t service_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPerdAdvSyncTransferParam(uint16_t conn_hdl, st_ble_gap_past_param_t * p_past_param) + * @brief This function starts to accept Periodic advertising sync transfer from the connection. + * @details + * This API call enables BLE_GAP_EVENT_PAST_RECV event.n + * + * @param[in] conn_hdl Connection handle identifying the remote device. + * @param[in] p_past_param Periodic advertising sync transfer parameters. + * @retval BLE_SUCCESS(0x0000) Success + * + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPerdAdvSyncTransferParam(uint16_t conn_hdl, st_ble_gap_past_param_t * p_past_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDefPerdAdvSyncTransferParam(st_ble_gap_past_param_t * p_past_param) + * @brief This function set the default parameter of Periodic advertising sync transfer for all subsequent connection. + * It does not affect any existing connection. + * @details + * This API call enables BLE_GAP_EVENT_PAST_RECV event. + * + * @param[in] p_past_param Periodic advertising sync transfer parameters. + * @retval BLE_SUCCESS(0x0000) Success + * + **************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDefPerdAdvSyncTransferParam(st_ble_gap_past_param_t * p_past_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadAntennaInfo(void) + * @brief This function read the switching rates, the sampling rates, the number of antennae, and the + * maximum length of a transmitted Constant Tone Extension + * + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + * @retval BLE_ERR_UNSPECIFIED(0x0013) Unspecified error. + **************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadAntennaInfo(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReceiverTest(st_ble_gap_recv_test_param_t * p_rx_test_param) + * @brief Start a test where the DUT receives test reference + * packets at a fixed interval. The tester generates the test reference packets. + * @details + * @param[in] p_rx_test_param receiver test parameter + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReceiverTest(st_ble_gap_recv_test_param_t * p_rx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_TransmitterTest(st_ble_gap_trans_test_param_t * p_tx_test_param) + * @brief Start a test where the DUT generates test reference + * packets at a fixed interval. The Controller shall transmit at the power level + * indicated by the TX_Power_Level parameter. + * @details + * @param[in] p_tx_test_param transmitter test parameter + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_TransmitterTest(st_ble_gap_trans_test_param_t * p_tx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ModifySleepClockAccuracy(uint8_t act) + * @brief request that the Controller changes its sleep clock + * accuracy for testing purposes. It should not be used under other + * circumstances. + * @details + * @param[in] act Switch to a more/less accurate clock. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ModifySleepClockAccuracy(uint8_t act); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadRemoteTransmitPowerLevel(uint16_t conn_hdl, uint8_t phy) + * @brief Read the transmit power level used by the remote device. + * @details BLE_GAP_EVENT_TX_POWER_REPT is received as a result when R_BLE_GAP_SetTransmitPowerReportingEnable is enabled. + * @param[in] conn_hdl Connection handle. + * @param[in] phy The transmitter PHY of packets. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadRemoteTransmitPowerLevel(uint16_t conn_hdl, uint8_t phy); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPathLossReportingParam(st_ble_gap_set_path_loss_rpt_param_t * p_loss_rpt_param) + * @brief Set the path loss threshold reporting parameters for the ACL connection identified. + * @details + * @param[in] p_loss_rpt_param parameter for path loss report. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPathLossReportingParam(st_ble_gap_set_path_loss_rpt_param_t * p_loss_rpt_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPathLossReportingEnable(uint16_t conn_hdl, uint8_t enable) + * @brief Enable or disable path loss reporting for the ACL connection. + * @details + * @param[in] conn_hdl Connection handle. + * @param[in] enable Reporting enable/disable. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPathLossReportingEnable(uint16_t conn_hdl, uint8_t enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetTransmitPowerReportingEnable(uint16_t conn_hdl, uint8_t local_enable, uint8_t remote_enable) + * @brief Enable or disable the transmit power level changing report + * @details Enable or disable the reporting to the local Host of transmit power level + * changes in the local and remote Controllers for the ACL connection identified + * by the Connection_Handle parameter. + * @param[in] conn_hdl Connection handle. + * @param[in] local_enable Local transmit power reports enable/disable. + * @param[in] remote_enable Remote transmit power reports enable/disable. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetTransmitPowerReportingEnable(uint16_t conn_hdl, uint8_t local_enable, uint8_t remote_enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDataRelatedAddrChanges(uint8_t adv_hdl, uint8_t change_reason) + * @brief Specifies circumstances when the Controller shall refresh any Resolvable Private + * Address. + * @details Specifies circumstances when the Controller shall refresh any Resolvable Private Addresss + * used by the advertising set identified by the Advertising_Handle parameter, whether or not + * the address timeout period has been reached. This function may be used while advertising is enabled. + * @param[in] adv_hdl Used to identify an advertising set. + * @param[in] change_reason reason(s) for refreshing addresses. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDataRelatedAddrChanges(uint8_t adv_hdl, uint8_t change_reason); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_TestEnd(void) + * @brief Stop any test which is in progress. The Num_Packets + * for a transmitter test shall be reported as 0x0000. The Num_Packets is an + * unsigned number and contains the number of received packets. + * @details + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_TestEnd(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReqPeerSCA(uint16_t conn_hdl) + * @brief Read the Sleep Clock Accuracy (SCA) of the peer device. + * @details + * @param[in] conn_hdl Indicate an ACL connection. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReqPeerSCA(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_EnhancedReadTxPowerLevel(uint16_t conn_hdl, uint8_t phy) + * @brief Read the current and maximum transmit power levels of the local Controller on + * the ACL connection identified by the Connection_Handle parameter and the + * PHY indicated by the PHY parameter. + * @details + * @param[in] conn_hdl Indicate an ACL connection. + * @param[in] phy Indicate PHY. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_EnhancedReadTxPowerLevel(uint16_t conn_hdl, uint8_t phy); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetHostFeat(uint8_t bit_number, uint8_t bit_value) + * @brief Set or clear a bit controlled by the Host + * in the Link Layer FeatureSet stored in the Controller. + * @details + * @param[in] bit_number Bit position in the FeatureSet + * @param[in] bit_value Value of the bit + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetHostFeat(uint8_t bit_number, uint8_t bit_value); + /*@}*/ +/* ============================================== ISO API Declarations ============================================== */ + +/** @defgroup ISO_API ISO + * @ingroup BLE_API + * @{ + */ +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_CreateBig(uint8_t * big_hdl, uint8_t adv_hdl, st_ble_iso_big_param_t * p_big_param) + * @brief Create a BIG. + * @param[out] big_hdl BIG handle is assigned by host stack, and value is passed out. + * @param[in] adv_hdl Periodic adv handle which carries the biginfo. + * @param[in] p_big_param BIG param + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_CreateBig(uint8_t * big_hdl, uint8_t adv_hdl, st_ble_iso_big_param_t * p_big_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_StopBig(uint8_t big_hdl, uint8_t reason) + * @brief Stop a BIG of the big_handle + * @param[in] big_hdl handle of the BIG to be stopped. + * @param[in] reason reason of termination. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_StopBig(uint8_t big_hdl, uint8_t reason); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_CreateBigSync(uint8_t* big_hdl, + uint16_t sync_hdl, + st_ble_iso_big_sync_param_t * p_big_sync_param); + * @brief Create a BIG sync + * @param[out] big_hdl BIG handle is assigned by host stack, and value is passed out. + * @param[in] sync_hdl Periodic adv sid which carries the biginfo. + * @param[in] p_big_sync_param BIG param which is got from biginfo. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_CreateBigSync(uint8_t * big_hdl, + uint16_t sync_hdl, + st_ble_iso_big_sync_param_t * p_big_sync_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_TerminateBigSync(uint8_t big_hdl) + * @brief Terminate a BIG sync + * @param[in] big_hdl handle of the BIG sync to be terminated. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_TerminateBigSync(uint8_t big_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SetCigParam(uint8_t * cig_id, st_ble_iso_cig_param_t * p_cig_param) + * @brief Create a CIG with param. + * @details This function requests BLE system to create a CIG. + * The result of this API call is notified in @ref BLE_ISO_EVENT_CIG_PARAM_SET_COMP event. + * @param[out] cig_id CIG is assigned by host stack, and value is passed out. + * @param[in] p_cig_param CIG param + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SetCigParam(uint8_t * cig_id, st_ble_iso_cig_param_t * p_cig_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_CreateCis(st_ble_iso_cis_conn_t * p_cis_conn) + * @brief Create one or more CISes using the CIS param. + * @details This function send the CIS requests to the remote devices. + * The result of this API call is returned by a return value. + * Remote device receives BLE_ISO_EVENT_CIS_REQ event. + * The response from remote device is notified in @ref BLE_ISO_EVENT_CIS_EST event. + * Once CIS connectionis estabilished successfully, they can be disconnected by + * R_BLE_GAP_Disconnect. + * @param[in] p_cis_conn CIS param + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_CreateCis(st_ble_iso_cis_conn_t * p_cis_conn); + +/******************************************************************************************************************//** + * @fn R_BLE_ISO_RemoveCig(uint8_t cig_id) + * @brief remove a CIG of id and all of CIS streams in this CIG. + * @param[out] cig_id CIG id to be removed. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_RemoveCig(uint8_t cig_id); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_ReplyCisRequest(uint8_t cig_id, uint8_t cis_id, uint8_t response, uint8_t reason) + * @brief Reply the CIS request from a remote device. + * @details This function replies to the CIS request from the remote device. + * The CIS request from the remote device is notified in @ref BLE_ISO_EVENT_CIS_REQ event. + * The result of this API call is returned by a return value. + * The result is notified in BLE_ISO_EVENT_CIS_EST event. + * @param[in] cig_id CIG ID + * @param[in] cis_id CIS ID + * @param[in] response Accept or reject the pairing request from the remote device. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_ISO_CIS_ACCEPT(0x00) | Accept the CIS request. | + * | BLE_ISO_CIS_REJECT(0x01) | Reject the CIS request. | + * @param[in] reason The reason for rejecting CIS request. This parameter is ignored when response is + * BLE_ISO_CIS_ACCEPT. Refer the error code described in + * Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_ReplyCisRequest(uint8_t cig_id, uint8_t cis_id, uint8_t response, uint8_t reason); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SetupDataPath(uint16_t conn_hdl, st_ble_iso_chan_path * p_path) + * @brief Create the ISO data path between the Host and the Controller for a CIS. + * @details This function behaviors depending on the platform. For SoC without Bluetooth Audio + * support, only the following value are valid in param path: + * | field | value | + * |:----------------------------- |:-------------------------------- | + * | path_id | BLE_ISO_DATA_PATH_HCI | + * | coding_format | 0xFF (Vendor specific coding format) | + * @param[in] conn_hdl CIS handle + * @param[in] p_path data path configuration + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SetupDataPath(uint16_t conn_hdl, st_ble_iso_chan_path * p_path); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SendData(st_ble_iso_sdu_t * sdu_info) + * @brief Send a SDU payload to a ISO channel of conn_hdl. + * @details This function copies SDU payload into host's buffer and push the buffer into host's TX queue. + * Once the payload is accepted by controller scheduler, @ref BLE_ISO_EVENT_ISO_TX_COMP event + * is sent back to application. Due to limitation of host buffer capacity, the maximum size of + * SDU payload is 251 bytes (@ref BLE_ISO_DATA_MAX_PDU). + * @param[in] sdu_info SDU info and data + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SendData(st_ble_iso_sdu_t * sdu_info); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SendDataNoCopy(st_ble_iso_sdu_t * sdu_info) + * @brief Send SDU payload to a ISO channel of conn_hdl without copying data. + * @details This function behaviors similar to R_BLE_ISO_SendData, but without copying SDU payload + * to the buffer in host. For this reason application should hold the buffer until a @ref + * BLE_ISO_EVENT_ISO_TX_COMP event with the same conn_hdl and seq_number of sdu_info is received. + * The maximum size of SDU payload defined by @ref BLE_ISO_DATA_MAX_SDU. + * @param[in] sdu_info SDU info and data + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SendDataNoCopy(st_ble_iso_sdu_t * sdu_info); + +/****************************************************************************************************************** + * @fn ble_status_t R_BLE_ISO_GetTxSync(uint16_t conn_hdl) + * @brief This function read read the TX_Time_Stamp and Time_Offset of the last transmitted SDU. + * @param[out] tx_sync Address for tx sync information + * @retval BLE_SUCCESS(0x0000) Success + * + **************************************************************************************************************/ +ble_status_t R_BLE_ISO_GetTxSync(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_CreateBigTest(uint8_t * big_hdl, uint8_t adv_hdl, + * st_ble_iso_create_big_test_param_t * p_create_big_test_param); + * @brief Create one or more BISes of a BIG (see [Vol 6] Part B, + * Section 4.4.6). All BISes in the BIG have the same values for all parameters. + * @details + * @param[out] big_hdl Used to identify a BIG. + * @param[in] adv_hdl Used to identify an advertising set. + * @param[in] p_create_big_test_param specified parameter of BIG param test + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_CreateBigTest(uint8_t * big_hdl, + uint8_t adv_hdl, + st_ble_iso_create_big_test_param_t * p_create_big_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SetCigParamTest(uint8_t * cig_id, + * st_ble_iso_set_cig_param_test_param_t * p_set_cig_param_test_param) + * @brief Create a CIG and set the parameters of one or more CISes that are associated with a CIG in the + * Controller. + * @details + * @param[in] p_set_cig_param_test_param specified parameter of CIG param_test + * @param[out] cig_id cig ID is assigned by host stack, and value is passed out. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SetCigParamTest(uint8_t * cig_id, + st_ble_iso_set_cig_param_test_param_t * p_set_cig_param_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_TransmitTest(uint16_t conn_hdl, uint8_t payload_type) + * @brief Configure an established CIS or BIS and transmit test payloads which are + * generated by the Controller. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS. + * @param[in] payload_type Configuration of SDUs in the payload. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_TransmitTest(uint16_t conn_hdl, uint8_t payload_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_ReceiveTest(uint16_t conn_hdl, uint8_t payload_type) + * @brief Configure an established CIS or a synchronized BIG to receive payloads. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS. + * @param[in] payload_type Configuration of SDUs in the payload. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_ReceiveTest(uint16_t conn_hdl, uint8_t payload_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_ReadTestCounters(uint16_t conn_hdl) + * @brief Read the test counters (see [Vol 6] Part B, Section 7) + * in the Controller which is configured in ISO Receive Test mode for a CIS or BIS + * specified by the Connection_Handle. Reading the test counters does not reset + * the test counters. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_ReadTestCounters(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_TestEnd(uint16_t conn_hdl) + * @brief Terminate the ISO Transmit and/or Receive Test + * mode for a CIS or BIS specified by the Connection_Handle parameter but does + * not terminate the CIS or BIS. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_TestEnd(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_ReadLinkQuality(uint16_t conn_hdl) + * @brief Returns the values of various counters related to link quality that + * are associated with the isochronous stream specified by the + * Connection_Handle parameter. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS. + * @retval BLE_SUCCESS(0x0000) Success, otherwise "HCI Spec Error" in enum RBLE_STATUS_enum. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_ReadLinkQuality(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn R_BLE_ISO_RemoveDataPath(uint16_t conn_hdl, uint8_t dir) + * @brief Remove the input and/or output data path(s) associated with a CIS, CIS configuration, or BIS + * identified by the Connection_Handle parameter. + * @details + * @param[in] conn_hdl Connection handle of the CIS or BIS + * @param[in] dir Data path direction. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_CHAN(0x0005) The handle does not indicate a CIS or BIS channel. + * @retval BLE_ERR_UNSPECIFIED(0x0013) Unspecified error. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_RemoveDataPath(uint16_t conn_hdl, uint8_t dir); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_ISO_SetPerAdvRecvEnable(uint16_t sync_hdl, uint8_t enable) + * @brief Remove the input and/or output data path(s) associated with a CIS, CIS configuration, or BIS + * identified by the Connection_Handle parameter. + * @details + * @param[in] sync_hdl Identifying the periodic advertising train + * @param[in] enable Reporting enabled/disabled + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) When parameter 'enable' represents neither enable nor disable. + * @retval BLE_ERR_INVALID_HDL(0x000E) The handle does not indicate a synchronization connection. + * @retval BLE_ERR_UNSPECIFIED(0x0013) Unspecified error. + **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SetPerAdvRecvEnable(uint16_t sync_hdl, uint8_t enable); + +/** @} */ + /* ========================================== GATT Common API Declarations ========================================== */ /** @defgroup GATT_COMMON_API GATT_COMMON diff --git a/ra/fsp/inc/api/r_cac_api.h b/ra/fsp/inc/api/r_cac_api.h index 213dd8750..f9b9ca7fb 100644 --- a/ra/fsp/inc/api/r_cac_api.h +++ b/ra/fsp/inc/api/r_cac_api.h @@ -30,8 +30,6 @@ * The interface for the clock frequency accuracy measurement circuit (CAC) peripheral is used to check a system * clock frequency with a reference clock signal by counting the number of pulses of the clock to be measured. * - * Implemented by: - * @ref CAC * * @{ **********************************************************************************************************************/ @@ -63,8 +61,6 @@ typedef enum e_cac_event } cac_event_t; /** CAC control block. Allocate an instance specific control block to pass into the CAC API calls. - * @par Implemented as - * - cac_instance_ctrl_t */ typedef void cac_ctrl_t; @@ -75,6 +71,8 @@ typedef enum e_cac_clock_type CAC_CLOCK_REFERENCE ///< Reference clock } cac_clock_type_t; +#ifndef BSP_OVERRIDE_CAC_CLOCK_SOURCE_T + /** Enumeration of the possible clock sources for both the reference and measurement clocks. */ typedef enum e_cac_clock_source { @@ -87,6 +85,9 @@ typedef enum e_cac_clock_source CAC_CLOCK_SOURCE_IWDT = 0x06, ///< IWDT-dedicated on-chip oscillator CAC_CLOCK_SOURCE_EXTERNAL = 0x07, ///< Externally supplied measurement clock on CACREF pin } cac_clock_source_t; +#endif + +#ifndef BSP_OVERRIDE_CAC_REF_DIVIDER_T /** Enumeration of available dividers for the reference clock. */ typedef enum e_cac_ref_divider @@ -96,6 +97,7 @@ typedef enum e_cac_ref_divider CAC_REF_DIV_1024 = 0x02, ///< Reference clock divided by 1024 CAC_REF_DIV_8192 = 0x03, ///< Reference clock divided by 8192 } cac_ref_divider_t; +#endif /** Enumeration of available digital filter settings for an external reference clock. */ typedef enum e_cac_ref_digfilter @@ -114,6 +116,8 @@ typedef enum e_cac_ref_edge CAC_REF_EDGE_BOTH = 0x02 ///< Both Rising and Falling edges detect for the Reference clock } cac_ref_edge_t; +#ifndef BSP_OVERRIDE_CAC_MEAS_DIVIDER_T + /** Enumeration of available dividers for the measurement clock */ typedef enum e_cac_meas_divider { @@ -122,6 +126,7 @@ typedef enum e_cac_meas_divider CAC_MEAS_DIV_8 = 0x02, ///< Measurement clock divided by 8 CAC_MEAS_DIV_32 = 0x03 ///< Measurement clock divided by 32 } cac_meas_divider_t; +#endif /** Structure defining the settings that apply to reference clock configuration. */ typedef struct st_cac_ref_clock_config @@ -191,11 +196,9 @@ typedef struct st_cac_api * @param[in] p_ctrl Control for the CAC device context. * @param[in] p_counter Pointer to variable in which to store the current CACNTBR register contents. */ - fsp_err_t (* read)(cac_ctrl_t * const p_ctrl, uint16_t * const p_counter); + fsp_err_t (* read)(cac_ctrl_t * const p_ctrl, uint32_t * const p_counter); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_CAC_CallbackSet() * * @param[in] p_ctrl Control block set in @ref cac_api_t::open call * @param[in] p_callback Callback function to register @@ -203,7 +206,7 @@ typedef struct st_cac_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(cac_ctrl_t * const p_api_ctrl, void (* p_callback)(cac_callback_args_t *), + fsp_err_t (* callbackSet)(cac_ctrl_t * const p_ctrl, void (* p_callback)(cac_callback_args_t *), void const * const p_context, cac_callback_args_t * const p_callback_memory); /** Close function for CAC device. diff --git a/ra/fsp/inc/api/r_can_api.h b/ra/fsp/inc/api/r_can_api.h index 10249c0d0..d6573c1e0 100644 --- a/ra/fsp/inc/api/r_can_api.h +++ b/ra/fsp/inc/api/r_can_api.h @@ -34,10 +34,6 @@ * - Callback function support with returning event code * - Hardware resource locking during a transaction * - * Implemented by: - * - @ref CAN - * - @ref CANFD - * * @{ **********************************************************************************************************************/ @@ -186,9 +182,6 @@ typedef struct st_can_cfg } can_cfg_t; /** CAN control block. Allocate an instance specific control block to pass into the CAN API calls. - * @par Implemented as - * - can_instance_ctrl_t - * - canfd_instance_ctrl_t */ typedef void can_ctrl_t; @@ -196,9 +189,6 @@ typedef void can_ctrl_t; typedef struct st_can_api { /** Open function for CAN device - * @par Implemented as - * - R_CAN_Open() - * - R_CANFD_Open() * * @param[in,out] p_ctrl Pointer to the CAN control block. Must be declared by user. Value set here. * @param[in] can_cfg_t Pointer to CAN configuration structure. All elements of this structure must be set by @@ -207,9 +197,6 @@ typedef struct st_can_api fsp_err_t (* open)(can_ctrl_t * const p_ctrl, can_cfg_t const * const p_cfg); /** Write function for CAN device - * @par Implemented as - * - R_CAN_Write() - * - R_CANFD_Write() * @param[in] p_ctrl Pointer to the CAN control block. * @param[in] buffer Buffer number (mailbox or message buffer) to write to. * @param[in] p_frame Pointer for frame of CAN ID, DLC, data and frame type to write. @@ -217,8 +204,6 @@ typedef struct st_can_api fsp_err_t (* write)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); /** Read function for CAN device - * @par Implemented as - * - R_CANFD_Read() * @param[in] p_ctrl Pointer to the CAN control block. * @param[in] buffer Message buffer (number) to read from. * @param[in] p_frame Pointer to store the CAN ID, DLC, data and frame type. @@ -226,27 +211,19 @@ typedef struct st_can_api fsp_err_t (* read)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); /** Close function for CAN device - * @par Implemented as - * - R_CAN_Close() * @param[in] p_ctrl Pointer to the CAN control block. */ fsp_err_t (* close)(can_ctrl_t * const p_ctrl); /** Mode Transition function for CAN device - * @par Implemented as - * - R_CAN_ModeTransition() - * - R_CANFD_ModeTransition() * @param[in] p_ctrl Pointer to the CAN control block. * @param[in] operation_mode Destination CAN operation state. * @param[in] test_mode Destination CAN test state. */ - fsp_err_t (* modeTransition)(can_ctrl_t * const p_api_ctrl, can_operation_mode_t operation_mode, + fsp_err_t (* modeTransition)(can_ctrl_t * const p_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode); /** Get CAN channel info. - * @par Implemented as - * - R_CAN_InfoGet() - * - R_CANFD_InfoGet() * * @param[in] p_ctrl Handle for channel (pointer to channel control block) * @param[out] p_info Memory address to return channel specific data to. @@ -254,9 +231,6 @@ typedef struct st_can_api fsp_err_t (* infoGet)(can_ctrl_t * const p_ctrl, can_info_t * const p_info); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_CAN_CallbackSet() - * - R_CANFD_CallbackSet() * * @param[in] p_ctrl Control block set in @ref can_api_t::open call. * @param[in] p_callback Callback function to register @@ -264,7 +238,7 @@ typedef struct st_can_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(can_ctrl_t * const p_api_ctrl, void (* p_callback)(can_callback_args_t *), + fsp_err_t (* callbackSet)(can_ctrl_t * const p_ctrl, void (* p_callback)(can_callback_args_t *), void const * const p_context, can_callback_args_t * const p_callback_memory); } can_api_t; @@ -277,7 +251,7 @@ typedef struct st_can_instance } can_instance_t; /*******************************************************************************************************************//** - * @} (end addtogroup CAN_API) + * @} (end defgroup CAN_API) **********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_capture_api.h b/ra/fsp/inc/api/r_capture_api.h new file mode 100644 index 000000000..f1833fcf6 --- /dev/null +++ b/ra/fsp/inc/api/r_capture_api.h @@ -0,0 +1,158 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup CAPTURE_API CAPTURE Interface + * @brief Interface for CAPTURE functions. + * + * @section CAPTURE_API_SUMMARY Summary + * The CAPTURE interface provides the functionality for capturing an image from an image sensor/camera. + * When a capture is complete a capture complete interrupt is triggered. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_CAPTURE_API_H +#define R_CAPTURE_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CAPTURE states. */ +typedef enum e_capture_state +{ + CAPTURE_STATE_IDLE = 0, ///< CAPTURE is idle + CAPTURE_STATE_IN_PROGRESS = 1, ///< CAPTURE capture in progress + CAPTURE_STATE_BUSY = 2, ///< CAPTURE reset in progress +} capture_state_t; + +/** CAPTURE status */ +typedef struct e_capture_status +{ + capture_state_t state; ///< Current state + uint32_t * p_buffer; ///< Pointer to active buffer + uint32_t data_size; ///< Size of data written to provided buffer +} capture_status_t; + +/** CAPTURE callback event ID - see implimentation for details */ +typedef uint32_t capture_event_t; + +/** CAPTURE callback function parameter data */ +typedef struct st_capture_callback_args +{ + capture_event_t event; ///< Event causing the callback + uint8_t * p_buffer; ///< Pointer to buffer that contains captured data + void const * p_context; ///< Placeholder for user data. Set in @ref capture_api_t::open function in @ref capture_cfg_t. +} capture_callback_args_t; + +/** CAPTURE configuration parameters. */ +typedef struct st_capture_cfg +{ + uint16_t x_capture_start_pixel; ///< Horizontal position to start capture + uint16_t x_capture_pixels; ///< Number of horizontal pixels to capture + uint16_t y_capture_start_pixel; ///< Vertical position to start capture + uint16_t y_capture_pixels; ///< Number of vertical lines/pixels to capture + uint8_t bytes_per_pixel; ///< Number of bytes per pixel + void (* p_callback)(capture_callback_args_t * p_args); ///< Callback provided when a CAPTURE transfer ISR occurs + void const * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extension parameter for hardware specific settings +} capture_cfg_t; + +/** CAPTURE control block. Allocate an instance specific control block to pass into the CAPTURE API calls. + */ +typedef void capture_ctrl_t; + +/** CAPTURE functions implemented at the HAL layer will follow this API. */ +typedef struct st_capture_api +{ + /** Initial configuration. + * + * @note To reconfigure after calling this function, call @ref capture_api_t::close first. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg); + + /** Closes the driver and allows reconfiguration. May reduce power consumption. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(capture_ctrl_t * const p_ctrl); + + /** Start a capture. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buffer New pointer to store captured image data. + */ + fsp_err_t (* captureStart)(capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the CAPTURE control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(capture_ctrl_t * const p_ctrl, void (* p_callback)(capture_callback_args_t *), + void const * const p_context, capture_callback_args_t * const p_callback_memory); + + /** Check scan status. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_status Pointer to store current status in + */ + fsp_err_t (* statusGet)(capture_ctrl_t * const p_ctrl, capture_status_t * p_status); +} capture_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_capture_instance +{ + capture_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + capture_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + capture_api_t const * p_api; ///< Pointer to the API structure for this instance +} capture_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CAPTURE_H + +/*******************************************************************************************************************//** + * @} (end addtogroup CAPTURE_API) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_cec_api.h b/ra/fsp/inc/api/r_cec_api.h index e40386f38..1d117d161 100644 --- a/ra/fsp/inc/api/r_cec_api.h +++ b/ra/fsp/inc/api/r_cec_api.h @@ -32,8 +32,6 @@ * - Allocation for full range of local address settings (TV, Recording Device, Playback Device, etc.) * - Supports a user-callback function (required), invoked when transmit, receive, or error interrupts are received. * - * Implemented by: - * - @ref CEC * @{ **********************************************************************************************************************/ @@ -190,8 +188,6 @@ typedef struct st_cec_cfg } cec_cfg_t; /** CEC control block. Allocate an instance specific control block to pass into the CEC API calls. - * @par Implemented as - * - cec_instance_ctrl_t */ typedef void cec_ctrl_t; @@ -199,8 +195,6 @@ typedef void cec_ctrl_t; typedef struct st_cec_api { /** Open function for CEC device - * @par Implemented as - * - @ref R_CEC_Open() * * @param[in,out] p_ctrl Pointer to the CEC control block. Must be declared by user. Value set here. * @param[in] p_cfg Pointer to CEC configuration structure. All elements of this structure must be set by user. @@ -209,8 +203,6 @@ typedef struct st_cec_api /** Initializes the CEC device. May be called any time after the CEC module has been opened. * This API blocks until the device initialization procedure is complete. - * @par Implemented as - * - @ref R_CEC_MediaInit() * * @param[in] p_ctrl Pointer to CEC instance control block. * @param[out] local_address Desired Logical address for local device. @@ -218,8 +210,6 @@ typedef struct st_cec_api fsp_err_t (* mediaInit)(cec_ctrl_t * const p_ctrl, cec_addr_t local_address); /** Write function for CEC device - * @par Implemented as - * - @ref R_CEC_Write() * * @param[in] p_ctrl Pointer to CEC instance control block * @param[in] p_message Message data @@ -228,8 +218,6 @@ typedef struct st_cec_api fsp_err_t (* write)(cec_ctrl_t * const p_ctrl, cec_message_t const * const p_message, uint32_t message_size); /** Close function for CEC device - * @par Implemented as - * - @ref R_CEC_Close() * * @param[in] p_ctrl Pointer to CEC instance control block * @param[out] p_message Message data @@ -237,8 +225,6 @@ typedef struct st_cec_api fsp_err_t (* close)(cec_ctrl_t * const p_ctrl); /** Get CEC channel info. - * @par Implemented as - * - @ref R_CEC_StatusGet() * * @param[in] p_ctrl Pointer to CEC instance control block * @param[out] p_status Memory address to return channel specific data to. @@ -246,8 +232,6 @@ typedef struct st_cec_api fsp_err_t (* statusGet)(cec_ctrl_t * const p_ctrl, cec_status_t * const p_status); /** Specify callback function, optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_CEC_CallbackSet() * * @param[in] p_ctrl Control block set in @ref cec_api_t::open call. * @param[in] p_callback Callback function to register diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h index 0ce587e43..c95b25aee 100644 --- a/ra/fsp/inc/api/r_cgc_api.h +++ b/ra/fsp/inc/api/r_cgc_api.h @@ -36,8 +36,6 @@ * to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect * when the main oscillator has stopped, with the option of calling a user provided callback function. * - * The CGC interface is implemented by: - * - @ref CGC * * @{ **********************************************************************************************************************/ @@ -63,9 +61,12 @@ FSP_HEADER /** Events that can trigger a callback function */ typedef enum e_cgc_event { - CGC_EVENT_OSC_STOP_DETECT ///< Oscillator stop detection has caused the event + CGC_EVENT_OSC_STOP_DETECT_NMI = 0, ///< Main oscillator stop detection has caused the NMI event + CGC_EVENT_OSC_STOP_DETECT_MAIN_OSC = 1, ///< Main oscillator stop detection has caused the interrupt event + CGC_EVENT_OSC_STOP_DETECT_SUBCLOCK = 2, ///< Subclock oscillator stop detection has caused the interrupt event } cgc_event_t; + /** Callback function parameter data */ typedef struct st_cgc_callback_args { @@ -73,6 +74,8 @@ typedef struct st_cgc_callback_args void const * p_context; ///< Placeholder for user data } cgc_callback_args_t; +#ifndef BSP_OVERRIDE_CGC_CLOCK_T + /** System clock source identifiers - The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock * divider */ typedef enum e_cgc_clock @@ -85,6 +88,7 @@ typedef enum e_cgc_clock CGC_CLOCK_PLL = 5, ///< The PLL oscillator CGC_CLOCK_PLL2 = 6, ///< The PLL2 oscillator } cgc_clock_t; +#endif /** PLL divider values */ typedef enum e_cgc_pll_div @@ -108,7 +112,9 @@ typedef enum e_cgc_pll_out_div CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16 } cgc_pll_out_div_t; -/** System clock divider vlues - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, +#ifndef BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, * PCLKS A-D. */ typedef enum e_cgc_sys_clock_div { @@ -119,7 +125,11 @@ typedef enum e_cgc_sys_clock_div CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 7, ///< System clock divided by 3 (BCLK only) } cgc_sys_clock_div_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_PLL_CFG_T /** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ typedef struct st_cgc_pll_cfg @@ -131,10 +141,24 @@ typedef struct st_cgc_pll_cfg cgc_pll_out_div_t out_div_q; ///< PLL divisor for output clock Q cgc_pll_out_div_t out_div_r; ///< PLL divisor for output clock R } cgc_pll_cfg_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_PIN_OUTPUT_CONTROL_T + +/** Pin output control enable/disable (SDCLK, BCLK). */ +typedef enum e_cgc_pin_output_control +{ + CGC_PIN_OUTPUT_CONTROL_ENABLE = 0, ///< Enable pin output + CGC_PIN_OUTPUT_CONTROL_DISABLE = 1 ///< Disable pin output +} cgc_pin_output_control_t; + +#endif + +#ifndef BSP_OVERRIDE_CGC_DIVIDER_CFG_T /** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet * functions. */ -typedef struct u_cgc_divider_cfg +typedef struct st_cgc_divider_cfg { union { @@ -164,14 +188,21 @@ typedef struct u_cgc_divider_cfg } sckdivcr2_b; }; } cgc_divider_cfg_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_USB_CLOCK_DIV_T /** USB clock divider values */ typedef enum e_cgc_usb_clock_div { + CGC_USB_CLOCK_DIV_2 = 1, ///< Divide USB source clock by 2 CGC_USB_CLOCK_DIV_3 = 2, ///< Divide USB source clock by 3 CGC_USB_CLOCK_DIV_4 = 3, ///< Divide USB source clock by 4 CGC_USB_CLOCK_DIV_5 = 4, ///< Divide USB source clock by 5 } cgc_usb_clock_div_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_CLOCK_CHANGE_T /** Clock options */ typedef enum e_cgc_clock_change @@ -180,20 +211,22 @@ typedef enum e_cgc_clock_change CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock } cgc_clock_change_t; +#endif /** CGC control block. Allocate an instance specific control block to pass into the CGC API calls. - * @par Implemented as - * - cgc_instance_ctrl_t */ typedef void cgc_ctrl_t; /** Configuration options. */ -typedef struct s_cgc_cfg +typedef struct st_cgc_cfg { void (* p_callback)(cgc_callback_args_t * p_args); void const * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. } cgc_cfg_t; +#ifndef BSP_OVERRIDE_CGC_CLOCKS_CFG_T + /** Clock configuration */ typedef struct st_cgc_clocks_cfg { @@ -207,30 +240,26 @@ typedef struct st_cgc_clocks_cfg cgc_clock_change_t mainosc_state; ///< State of Main oscillator cgc_clock_change_t pll_state; ///< State of PLL cgc_clock_change_t pll2_state; ///< State of PLL2 + cgc_clock_change_t subosc_state; ///< State of Sub oscillator } cgc_clocks_cfg_t; +#endif /** CGC functions implemented at the HAL layer follow this API. */ typedef struct { /** Initial configuration - * @par Implemented as - * - @ref R_CGC_Open() * @param[in] p_ctrl Pointer to instance control block * @param[in] p_cfg Pointer to configuration */ fsp_err_t (* open)(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg); /** Configure all system clocks. - * @par Implemented as - * - @ref R_CGC_ClocksCfg() * @param[in] p_ctrl Pointer to instance control block * @param[in] p_clock_cfg Pointer to desired configuration of system clocks */ fsp_err_t (* clocksCfg)(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg); /** Start a clock. - * @par Implemented as - * - @ref R_CGC_ClockStart() * @param[in] p_ctrl Pointer to instance control block * @param[in] clock_source Clock source to start * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL or @@ -240,24 +269,18 @@ typedef struct cgc_pll_cfg_t const * const p_pll_cfg); /** Stop a clock. - * @par Implemented as - * - @ref R_CGC_ClockStop() * @param[in] p_ctrl Pointer to instance control block * @param[in] clock_source The clock source to stop */ fsp_err_t (* clockStop)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); /** Check the stability of the selected clock. - * @par Implemented as - * - @ref R_CGC_ClockCheck() * @param[in] p_ctrl Pointer to instance control block * @param[in] clock_source Which clock source to check for stability */ fsp_err_t (* clockCheck)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); /** Set the system clock. - * @par Implemented as - * - @ref R_CGC_SystemClockSet() * @param[in] p_ctrl Pointer to instance control block * @param[in] clock_source Clock source to set as system clock * @param[in] p_divider_cfg Pointer to the clock divider configuration @@ -266,8 +289,6 @@ typedef struct cgc_divider_cfg_t const * const p_divider_cfg); /** Get the system clock information. - * @par Implemented as - * - @ref R_CGC_SystemClockGet() * @param[in] p_ctrl Pointer to instance control block * @param[out] p_clock_source Returns the current system clock * @param[out] p_divider_cfg Returns the current system clock dividers @@ -276,33 +297,22 @@ typedef struct cgc_divider_cfg_t * const p_divider_cfg); /** Enable and optionally register a callback for Main Oscillator stop detection. - * @par Implemented as - * - @ref R_CGC_OscStopDetectEnable() * @param[in] p_ctrl Pointer to instance control block - * @param[in] p_callback Callback function that will be called by the NMI interrupt when an oscillation stop is - * detected. If the second argument is "false", then this argument can be NULL. - * @param[in] enable Enable/disable Oscillation Stop Detection */ fsp_err_t (* oscStopDetectEnable)(cgc_ctrl_t * const p_ctrl); /** Disable Main Oscillator stop detection. - * @par Implemented as - * - @ref R_CGC_OscStopDetectDisable() * @param[in] p_ctrl Pointer to instance control block */ fsp_err_t (* oscStopDetectDisable)(cgc_ctrl_t * const p_ctrl); /** Clear the oscillator stop detection flag. - * @par Implemented as - * - @ref R_CGC_OscStopStatusClear() * @param[in] p_ctrl Pointer to instance control block */ fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl); /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_CGC_CallbackSet() * * @param[in] p_ctrl Pointer to the CGC control block. * @param[in] p_callback Callback function @@ -310,12 +320,10 @@ typedef struct * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(cgc_ctrl_t * const p_api_ctrl, void (* p_callback)(cgc_callback_args_t *), + fsp_err_t (* callbackSet)(cgc_ctrl_t * const p_ctrl, void (* p_callback)(cgc_callback_args_t *), void const * const p_context, cgc_callback_args_t * const p_callback_memory); /** Close the CGC driver. - * @par Implemented as - * - @ref R_CGC_Close() * @param[in] p_ctrl Pointer to instance control block */ fsp_err_t (* close)(cgc_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/api/r_comparator_api.h b/ra/fsp/inc/api/r_comparator_api.h index 4bdbf3035..4bd82bd81 100644 --- a/ra/fsp/inc/api/r_comparator_api.h +++ b/ra/fsp/inc/api/r_comparator_api.h @@ -30,9 +30,6 @@ * The comparator interface provides standard comparator functionality, including generating an event when the * comparator result changes. * - * Implemented by: - * - @ref ACMPHS - * - @ref ACMPLP * * @{ **********************************************************************************************************************/ @@ -56,9 +53,6 @@ FSP_HEADER ******************************************************************************/ /** Comparator control block. Allocate an instance specific control block to pass into the comparator API calls. - * @par Implemented as - * - acmphs_instance_ctrl_t - * - acmplp_instance_ctrl_t */ typedef void comparator_ctrl_t; @@ -154,9 +148,6 @@ typedef struct st_comparator_cfg typedef struct st_comparator_api { /** Initialize the comparator. - * @par Implemented as - * - @ref R_ACMPHS_Open() - * - @ref R_ACMPLP_Open() * * @param[in] p_ctrl Pointer to instance control block * @param[in] p_cfg Pointer to configuration @@ -164,18 +155,12 @@ typedef struct st_comparator_api fsp_err_t (* open)(comparator_ctrl_t * const p_ctrl, comparator_cfg_t const * const p_cfg); /** Start the comparator. - * @par Implemented as - * - @ref R_ACMPHS_OutputEnable() - * - @ref R_ACMPLP_OutputEnable() * * @param[in] p_ctrl Pointer to instance control block */ fsp_err_t (* outputEnable)(comparator_ctrl_t * const p_ctrl); /** Provide information such as the recommended minimum stabilization wait time. - * @par Implemented as - * - @ref R_ACMPHS_InfoGet() - * - @ref R_ACMPLP_InfoGet() * * @param[in] p_ctrl Pointer to instance control block * @param[out] p_info Comparator information stored here @@ -183,9 +168,6 @@ typedef struct st_comparator_api fsp_err_t (* infoGet)(comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info); /** Provide current comparator status. - * @par Implemented as - * - @ref R_ACMPHS_StatusGet() - * - @ref R_ACMPLP_StatusGet() * * @param[in] p_ctrl Pointer to instance control block * @param[out] p_status Status stored here @@ -193,9 +175,6 @@ typedef struct st_comparator_api fsp_err_t (* statusGet)(comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status); /** Stop the comparator. - * @par Implemented as - * - @ref R_ACMPHS_Close() - * - @ref R_ACMPLP_Close() * * @param[in] p_ctrl Pointer to instance control block */ diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h index cc019a5d4..610b9583e 100644 --- a/ra/fsp/inc/api/r_crc_api.h +++ b/ra/fsp/inc/api/r_crc_api.h @@ -30,10 +30,8 @@ * @section CRC_API_SUMMARY Summary * The CRC (Cyclic Redundancy Check) calculator generates CRC codes using five different polynomials including 8 bit, * 16 bit, and 32 bit variations. Calculation can be performed by sending data to the block using the CPU or by snooping - * on read or write activity on one of 10 SCI channels. + * on read or write activity on one of SCI channels. * - * Implemented by: - * - @ref CRC * * @{ **********************************************************************************************************************/ @@ -85,52 +83,6 @@ typedef enum e_crc_snoop_direction CRC_SNOOP_DIRECTION_TRANSMIT, ///< Snoop-on-write } crc_snoop_direction_t; -/** Snoop SCI register Address (lower 14 bits) */ -typedef enum e_snoop_address_sci -{ - CRC_SNOOP_ADDRESS_NONE = 0x00, ///< Snoop mode disabled - CRC_SNOOP_ADDRESS_SCI0_TDR = 0x003, ///< Snoop SCI0 transmit data register - CRC_SNOOP_ADDRESS_SCI1_TDR = 0x023, ///< Snoop SCI1 transmit data register - CRC_SNOOP_ADDRESS_SCI2_TDR = 0x043, ///< Snoop SCI2 transmit data register - CRC_SNOOP_ADDRESS_SCI3_TDR = 0x063, ///< Snoop SCI3 transmit data register - CRC_SNOOP_ADDRESS_SCI4_TDR = 0x083, ///< Snoop SCI4 transmit data register - CRC_SNOOP_ADDRESS_SCI5_TDR = 0x0A3, ///< Snoop SCI5 transmit data register - CRC_SNOOP_ADDRESS_SCI6_TDR = 0x0C3, ///< Snoop SCI6 transmit data register - CRC_SNOOP_ADDRESS_SCI7_TDR = 0x0E3, ///< Snoop SCI7 transmit data register - CRC_SNOOP_ADDRESS_SCI8_TDR = 0x103, ///< Snoop SCI8 transmit data register - CRC_SNOOP_ADDRESS_SCI9_TDR = 0x123, ///< Snoop SCI9 transmit data register - CRC_SNOOP_ADDRESS_SCI0_FTDRL = 0x00F, ///< Snoop SCI0 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI1_FTDRL = 0x02F, ///< Snoop SCI1 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI2_FTDRL = 0x04F, ///< Snoop SCI2 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI3_FTDRL = 0x06F, ///< Snoop SCI3 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI4_FTDRL = 0x08F, ///< Snoop SCI4 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI5_FTDRL = 0x0AF, ///< Snoop SCI5 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI6_FTDRL = 0x0CF, ///< Snoop SCI6 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI7_FTDRL = 0x0EF, ///< Snoop SCI7 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI8_FTDRL = 0x10F, ///< Snoop SCI8 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI9_FTDRL = 0x12F, ///< Snoop SCI9 transmit FIFO data register - CRC_SNOOP_ADDRESS_SCI0_RDR = 0x005, ///< Snoop SCI0 receive data register - CRC_SNOOP_ADDRESS_SCI1_RDR = 0x025, ///< Snoop SCI1 receive data register - CRC_SNOOP_ADDRESS_SCI2_RDR = 0x045, ///< Snoop SCI2 receive data register - CRC_SNOOP_ADDRESS_SCI3_RDR = 0x065, ///< Snoop SCI3 receive data register - CRC_SNOOP_ADDRESS_SCI4_RDR = 0x085, ///< Snoop SCI4 receive data register - CRC_SNOOP_ADDRESS_SCI5_RDR = 0x0A5, ///< Snoop SCI5 receive data register - CRC_SNOOP_ADDRESS_SCI6_RDR = 0x0C5, ///< Snoop SCI6 receive data register - CRC_SNOOP_ADDRESS_SCI7_RDR = 0x0E5, ///< Snoop SCI7 receive data register - CRC_SNOOP_ADDRESS_SCI8_RDR = 0x105, ///< Snoop SCI8 receive data register - CRC_SNOOP_ADDRESS_SCI9_RDR = 0x125, ///< Snoop SCI9 receive data register - CRC_SNOOP_ADDRESS_SCI0_FRDRL = 0x011, ///< Snoop SCI0 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI1_FRDRL = 0x031, ///< Snoop SCI1 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI2_FRDRL = 0x051, ///< Snoop SCI2 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI3_FRDRL = 0x071, ///< Snoop SCI3 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI4_FRDRL = 0x091, ///< Snoop SCI4 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI5_FRDRL = 0x0B1, ///< Snoop SCI5 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI6_FRDRL = 0x0D1, ///< Snoop SCI6 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI7_FRDRL = 0x0F1, ///< Snoop SCI7 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI8_FRDRL = 0x111, ///< Snoop SCI8 receive FIFO data register - CRC_SNOOP_ADDRESS_SCI9_FRDRL = 0x131, ///< Snoop SCI9 receive FIFO data register -} crc_snoop_address_t; - /** Structure for CRC inputs */ typedef struct st_crc_input_t { @@ -140,28 +92,23 @@ typedef struct st_crc_input_t } crc_input_t; /** CRC control block. Allocate an instance specific control block to pass into the CRC API calls. - * @par Implemented as - * - crc_instance_ctrl_t */ typedef void crc_ctrl_t; /** User configuration structure, used in open function */ typedef struct st_crc_cfg { + uint8_t channel; ///< Channel number crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS) crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS) - - /* crc_snoop_address_t is to be deprecated. */ - int32_t snoop_address; ///< Register Snoop Address (CRCSA) - void const * p_extend; ///< CRC Hardware Dependent Configuration + int32_t snoop_address; ///< Register Snoop Address (CRCSA) + void const * p_extend; ///< CRC Hardware Dependent Configuration } crc_cfg_t; /** CRC driver structure. General CRC functions implemented at the HAL layer will follow this API. */ typedef struct st_crc_api { /** Open the CRC driver module. - * @par Implemented as - * - @ref R_CRC_Open() * * @param[in] p_ctrl Pointer to CRC device handle. * @param[in] p_cfg Pointer to a configuration structure. @@ -169,17 +116,13 @@ typedef struct st_crc_api fsp_err_t (* open)(crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg); /** Close the CRC module driver - * @par Implemented as - * - @ref R_CRC_Close() * - * @param[in] p_ctrl Pointer to crc device handle + * @param[in] p_ctrl Pointer to CRC device handle * @retval FSP_SUCCESS Configuration was successful. **/ fsp_err_t (* close)(crc_ctrl_t * const p_ctrl); /** Return the current calculated value. - * @par Implemented as - * - @ref R_CRC_CalculatedValueGet() * * @param[in] p_ctrl Pointer to CRC device handle. * @param[out] crc_result The calculated value from the last CRC calculation. @@ -187,8 +130,6 @@ typedef struct st_crc_api fsp_err_t (* crcResultGet)(crc_ctrl_t * const p_ctrl, uint32_t * crc_result); /** Configure and Enable snooping. - * @par Implemented as - * - @ref R_CRC_SnoopEnable() * * @param[in] p_ctrl Pointer to CRC device handle. * @param[in] crc_seed CRC seed. @@ -196,18 +137,14 @@ typedef struct st_crc_api fsp_err_t (* snoopEnable)(crc_ctrl_t * const p_ctrl, uint32_t crc_seed); /** Disable snooping. - * @par Implemented as - * - @ref R_CRC_SnoopDisable() * * @param[in] p_ctrl Pointer to CRC device handle. **/ fsp_err_t (* snoopDisable)(crc_ctrl_t * const p_ctrl); /** Perform a CRC calculation on a block of data. - * @par Implemented as - * - @ref R_CRC_Calculate() * - * @param[in] p_ctrl Pointer to crc device handle. + * @param[in] p_ctrl Pointer to CRC device handle. * @param[in] p_crc_input A pointer to structure for CRC inputs * @param[out] crc_result The calculated value of the CRC calculation. **/ diff --git a/ra/fsp/inc/api/r_ctsu_api.h b/ra/fsp/inc/api/r_ctsu_api.h index fe99b58df..12fce3011 100644 --- a/ra/fsp/inc/api/r_ctsu_api.h +++ b/ra/fsp/inc/api/r_ctsu_api.h @@ -26,8 +26,6 @@ * @section CTSU_API_Summary Summary * The CTSU interface provides CTSU functionality. * - * The CTSU interface can be implemented by: - * - @ref CTSU * * @{ **********************************************************************************************************************/ @@ -161,8 +159,6 @@ typedef struct st_ctsu_callback_args } ctsu_callback_args_t; /** CTSU Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - ctsu_instance_ctrl_t */ typedef void ctsu_ctrl_t; @@ -218,8 +214,6 @@ typedef struct st_ctsu_cfg typedef struct st_ctsu_api { /** Open driver. - * @par Implemented as - * - @ref R_CTSU_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -227,16 +221,12 @@ typedef struct st_ctsu_api fsp_err_t (* open)(ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cfg); /** Scan start. - * @par Implemented as - * - @ref R_CTSU_ScanStart() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* scanStart)(ctsu_ctrl_t * const p_ctrl); /** Data get. - * @par Implemented as - * - @ref R_CTSU_DataGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_data Pointer to get data array. @@ -244,24 +234,18 @@ typedef struct st_ctsu_api fsp_err_t (* dataGet)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_data); /** ScanStop. - * @par Implemented as - * - @ref R_CTSU_ScanStop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* scanStop)(ctsu_ctrl_t * const p_ctrl); /** Diagnosis. - * @par Implemented as - * - @ref R_CTSU_Diagnosis() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* diagnosis)(ctsu_ctrl_t * const p_ctrl); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_CTSU_CallbackSet() * * @param[in] p_ctrl Pointer to the CTSU control block. * @param[in] p_callback Callback function @@ -269,20 +253,16 @@ typedef struct st_ctsu_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(ctsu_ctrl_t * const p_api_ctrl, void (* p_callback)(ctsu_callback_args_t *), + fsp_err_t (* callbackSet)(ctsu_ctrl_t * const p_ctrl, void (* p_callback)(ctsu_callback_args_t *), void const * const p_context, ctsu_callback_args_t * const p_callback_memory); /** Close driver. - * @par Implemented as - * - @ref R_CTSU_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(ctsu_ctrl_t * const p_ctrl); /** Specific Data get. - * @par Implemented as - * - @ref R_CTSU_SpecificDataGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_specific_data Pointer to get specific data array. @@ -292,8 +272,6 @@ typedef struct st_ctsu_api ctsu_specific_data_type_t specific_data_type); /** Data Insert. - * @par Implemented as - * - @ref R_CTSU_DataInsert() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_insert_data Pointer to insert data. @@ -301,8 +279,6 @@ typedef struct st_ctsu_api fsp_err_t (* dataInsert)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_data); /** Adjust the offset value to tune the sensor. - * @par Implemented as - * - @ref R_CTSU_OffsetTuning() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/r_dac_api.h b/ra/fsp/inc/api/r_dac_api.h index 774991965..334ee5d82 100644 --- a/ra/fsp/inc/api/r_dac_api.h +++ b/ra/fsp/inc/api/r_dac_api.h @@ -27,9 +27,6 @@ * The DAC interface provides standard Digital/Analog Converter functionality. A DAC application writes digital * sample data to the device and generates analog output on the DAC output pin. * - * Implemented by: - * - @ref DAC - * - @ref DAC8 * * @{ **********************************************************************************************************************/ @@ -77,9 +74,6 @@ typedef struct st_dac_cfg } dac_cfg_t; /** DAC control block. Allocate an instance specific control block to pass into the DAC API calls. - * @par Implemented as - * - dac_instance_ctrl_t - * - dac8_instance_ctrl_t */ typedef void dac_ctrl_t; @@ -87,9 +81,6 @@ typedef void dac_ctrl_t; typedef struct st_dac_api { /** Initial configuration. - * @par Implemented as - * - @ref R_DAC_Open() - * - @ref R_DAC8_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -97,18 +88,12 @@ typedef struct st_dac_api fsp_err_t (* open)(dac_ctrl_t * const p_ctrl, dac_cfg_t const * const p_cfg); /** Close the D/A Converter. - * @par Implemented as - * - @ref R_DAC_Close() - * - @ref R_DAC8_Close() * * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. */ fsp_err_t (* close)(dac_ctrl_t * const p_ctrl); /** Write sample value to the D/A Converter. - * @par Implemented as - * - @ref R_DAC_Write() - * - @ref R_DAC8_Write() * * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. * @param[in] value Sample value to be written to the D/A Converter. @@ -116,18 +101,12 @@ typedef struct st_dac_api fsp_err_t (* write)(dac_ctrl_t * const p_ctrl, uint16_t value); /** Start the D/A Converter if it has not been started yet. - * @par Implemented as - * - @ref R_DAC_Start() - * - @ref R_DAC8_Start() * * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. */ fsp_err_t (* start)(dac_ctrl_t * const p_ctrl); /** Stop the D/A Converter if the converter is running. - * @par Implemented as - * - @ref R_DAC_Stop() - * - @ref R_DAC8_Stop() * * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. */ diff --git a/ra/fsp/inc/api/r_display_api.h b/ra/fsp/inc/api/r_display_api.h index a21b54227..e13037422 100644 --- a/ra/fsp/inc/api/r_display_api.h +++ b/ra/fsp/inc/api/r_display_api.h @@ -31,8 +31,6 @@ * - Color correction (brightness/configuration/gamma correction). * - Interrupts and callback function. * - * Implemented by: - * @ref GLCDC * * @{ **********************************************************************************************************************/ @@ -46,7 +44,6 @@ /* Includes board and MCU related header files. */ #include "bsp_api.h" -#include "r_glcdc_cfg.h" /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ FSP_HEADER @@ -82,8 +79,11 @@ typedef enum e_display_event DISPLAY_EVENT_GR1_UNDERFLOW = 1, ///< Graphics frame1 underflow occurs DISPLAY_EVENT_GR2_UNDERFLOW = 2, ///< Graphics frame2 underflow occurs DISPLAY_EVENT_LINE_DETECTION = 3, ///< Designated line is processed + DISPLAY_EVENT_FRAME_END = 4, ///< Frame end is processed } display_event_t; +#ifndef BSP_OVERRIDE_DISPLAY_IN_FORMAT_T + /** Input format setting */ typedef enum e_display_in_format { @@ -97,6 +97,8 @@ typedef enum e_display_in_format DISPLAY_IN_FORMAT_CLUT1 = 7, ///< CLUT1 } display_in_format_t; +#endif + /** Output format setting */ typedef enum e_display_out_format { @@ -121,7 +123,7 @@ typedef enum e_display_color_order } display_color_order_t; /** Polarity of a signal select */ -typedef enum st_display_signal_polarity +typedef enum e_display_signal_polarity { DISPLAY_SIGNAL_POLARITY_LOACTIVE, ///< Low active signal DISPLAY_SIGNAL_POLARITY_HIACTIVE, ///< High active signal @@ -150,6 +152,26 @@ typedef enum e_display_fade_status DISPLAY_FADE_STATUS_PENDING ///< Fade-in/fade-out is configured but not yet started } display_fade_status_t; +/** Color Keying enable or disable */ +typedef enum e_display_color_keying +{ + DISPLAY_COLOR_KEYING_DISABLE = 0, ///< Color keying disable + DISPLAY_COLOR_KEYING_ENABLE = 1 ///< Color keying enable +} display_color_keying_t; + +#ifndef BSP_OVERRIDE_DISPLAY_DATA_SWAP_T + +/** Data swap settings */ +typedef enum e_display_data_swap +{ + DISPLAY_DATA_SWAP_8BIT = 1, + DISPLAY_DATA_SWAP_16BIT = 2, + DISPLAY_DATA_SWAP_32BIT = 4, + DISPLAY_DATA_SWAP_64BIT = 8, +} display_data_swap_t; + +#endif + /** Display signal timing setting */ typedef struct st_display_timing { @@ -231,6 +253,22 @@ typedef struct st_display_clut const uint32_t * p_clut; ///< Address of the area storing the CLUT data (in ARGB8888 format) } display_clut_t; +/** Color Keying setting */ +typedef struct st_display_colorkeying_cfg +{ + display_color_t src_color; ///< Source color + display_color_t dst_color; ///< Destination color + display_color_keying_t enable_ckey; ///< Select enable or disable +} display_colorkeying_cfg_t; + +/** Color Keying layer setting */ +typedef struct st_display_colorkeying_layer +{ + display_colorkeying_cfg_t layer[2]; +} display_colorkeying_layer_t; + +#ifndef BSP_OVERRIDE_DISPLAY_INPUT_CFG_T + /** Graphics plane input configuration structure */ typedef struct st_display_input_cfg { @@ -244,23 +282,23 @@ typedef struct st_display_input_cfg uint16_t lines_repeat_times; ///< Expected number of line repeating } display_input_cfg_t; +#endif + /** Display output configuration structure */ typedef struct st_display_output_cfg { - display_timing_t htiming; ///< Horizontal display cycle setting - display_timing_t vtiming; ///< Vertical display cycle setting - display_out_format_t format; ///< Output format setting - display_endian_t endian; ///< Bit order of output data - display_color_order_t color_order; ///< Color order in pixel - display_signal_polarity_t data_enable_polarity; ///< Data Enable signal polarity - display_sync_edge_t sync_edge; ///< Signal sync edge selection - display_color_t bg_color; ///< Background color -#if GLCDC_CFG_COLOR_CORRECTION_ENABLE - display_brightness_t brightness; ///< Brightness setting - display_contrast_t contrast; ///< Contrast setting - display_gamma_correction_t * p_gamma_correction; ///< Pointer to gamma correction setting -#endif - bool dithering_on; ///< Dithering on/off + display_timing_t htiming; ///< Horizontal display cycle setting + display_timing_t vtiming; ///< Vertical display cycle setting + display_out_format_t format; ///< Output format setting + display_endian_t endian; ///< Bit order of output data + display_color_order_t color_order; ///< Color order in pixel + display_signal_polarity_t data_enable_polarity; ///< Data Enable signal polarity + display_sync_edge_t sync_edge; ///< Signal sync edge selection + display_color_t bg_color; ///< Background color + display_brightness_t brightness; ///< Brightness setting + display_contrast_t contrast; ///< Contrast setting + display_gamma_correction_t * p_gamma_correction; ///< Pointer to gamma correction setting + bool dithering_on; ///< Dithering on/off } display_output_cfg_t; /** Graphics layer blend setup parameter structure */ @@ -318,8 +356,6 @@ typedef struct st_display_clut_cfg } display_clut_cfg_t; /** Display control block. Allocate an instance specific control block to pass into the display API calls. - * @par Implemented as - * - glcdc_instance_ctrl_t */ /** Display control block */ @@ -328,7 +364,7 @@ typedef void display_ctrl_t; /** Display Status */ typedef struct st_display_status { - display_state_t state; ///< Status of GLCDC module + display_state_t state; ///< Status of display module display_fade_status_t fade_status[DISPLAY_FRAME_LAYER_2 + 1]; ///< Status of fade-in/fade-out status } display_status_t; @@ -336,8 +372,6 @@ typedef struct st_display_status typedef struct st_display_api { /** Open display device. - * @par Implemented as - * - @ref R_GLCDC_Open() * @param[in,out] p_ctrl Pointer to display interface control block. Must be declared by user. Value set * here. * @param[in] p_cfg Pointer to display configuration structure. All elements of this structure must be @@ -346,29 +380,21 @@ typedef struct st_display_api fsp_err_t (* open)(display_ctrl_t * const p_ctrl, display_cfg_t const * const p_cfg); /** Close display device. - * @par Implemented as - * - @ref R_GLCDC_Close() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* close)(display_ctrl_t * const p_ctrl); /** Display start. - * @par Implemented as - * - @ref R_GLCDC_Start() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* start)(display_ctrl_t * const p_ctrl); /** Display stop. - * @par Implemented as - * - @ref R_GLCDC_Stop() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* stop)(display_ctrl_t * const p_ctrl); /** Change layer parameters at runtime. - * @par Implemented as - * - @ref R_GLCDC_LayerChange() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] p_cfg Pointer to run-time layer configuration structure. * @param[in] frame Number of graphic frames. @@ -377,8 +403,6 @@ typedef struct st_display_api display_frame_layer_t frame); /** Change layer framebuffer pointer. - * @par Implemented as - * - @ref R_GLCDC_BufferChange() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] framebuffer Pointer to desired framebuffer. * @param[in] frame Number of graphic frames. @@ -386,20 +410,13 @@ typedef struct st_display_api fsp_err_t (* bufferChange)(display_ctrl_t const * const p_ctrl, uint8_t * const framebuffer, display_frame_layer_t frame); -#if GLCDC_CFG_COLOR_CORRECTION_ENABLE - /** Color correction. - * @par Implemented as - * - @ref R_GLCDC_ColorCorrection() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] param Pointer to color correction configuration structure. */ fsp_err_t (* correction)(display_ctrl_t const * const p_ctrl, display_correction_t const * const p_param); -#endif /** Set CLUT for display device. - * @par Implemented as - * - @ref R_GLCDC_ClutUpdate() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] p_clut_cfg Pointer to CLUT configuration structure. * @param[in] layer Layer number corresponding to the CLUT. @@ -408,8 +425,6 @@ typedef struct st_display_api display_frame_layer_t layer); /** Set CLUT element for display device. - * @par Implemented as - * - @ref R_GLCDC_ClutEdit() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] layer Layer number corresponding to the CLUT. * @param[in] index CLUT element index. @@ -418,9 +433,15 @@ typedef struct st_display_api fsp_err_t (* clutEdit)(display_ctrl_t const * const p_ctrl, display_frame_layer_t layer, uint8_t index, uint32_t color); + /** Configure color keying. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] key_cfg Pointer to color keying configuration. + * @param[in] layer Layer to apply color keying. + */ + fsp_err_t (* colorKeySet)(display_ctrl_t const * const p_ctrl, display_colorkeying_layer_t key_cfg, + display_frame_layer_t layer); + /** Get status for display device. - * @par Implemented as - * - @ref R_GLCDC_StatusGet() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] status Pointer to display interface status structure. */ diff --git a/ra/fsp/inc/api/r_doc_api.h b/ra/fsp/inc/api/r_doc_api.h index 523dfef26..020df4e16 100644 --- a/ra/fsp/inc/api/r_doc_api.h +++ b/ra/fsp/inc/api/r_doc_api.h @@ -29,8 +29,6 @@ * @section DOC_API_SUMMARY Summary * @brief This module implements the DOC_API using the Data Operation Circuit (DOC). * - * Implemented by: - * @ref DOC * * @{ **********************************************************************************************************************/ @@ -85,8 +83,6 @@ typedef struct st_doc_callback_args } doc_callback_args_t; /** DOC control block. Allocate an instance specific control block to pass into the DOC API calls. - * @par Implemented as - * - doc_instance_ctrl_t */ typedef void doc_ctrl_t; @@ -111,7 +107,7 @@ typedef struct st_doc_cfg uint32_t doc_data_extra; uint8_t ipl; ///< DOC interrupt priority - IRQn_Type irq; ///< NVIC interrupt number assigned to this instance + IRQn_Type irq; ///< Interrupt number assigned to this instance /** Callback provided when a DOC ISR occurs. */ void (* p_callback)(doc_callback_args_t * p_args); @@ -124,23 +120,17 @@ typedef struct st_doc_cfg typedef struct st_doc_api { /** Initial configuration. - * @par Implemented as - * - @ref R_DOC_Open() * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. */ fsp_err_t (* open)(doc_ctrl_t * const p_ctrl, doc_cfg_t const * const p_cfg); /**Allow the driver to be reconfigured. Will reduce power consumption. - * @par Implemented as - * - @ref R_DOC_Close() * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. */ fsp_err_t (* close)(doc_ctrl_t * const p_ctrl); /** Gets the result of addition/subtraction operations and stores it in the provided pointer p_result. - * @par Implemented as - * - @ref R_DOC_Read() * * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. * @param[in] p_result The result of the DOC operation. @@ -148,8 +138,6 @@ typedef struct st_doc_api fsp_err_t (* read)(doc_ctrl_t * const p_ctrl, uint32_t * p_result); /** Write to the DODIR register. - * @par Implemented as - * - @ref R_DOC_Write() * * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. * @param[in] data data to be written to DOC DODIR register. @@ -158,8 +146,6 @@ typedef struct st_doc_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_DOC_CallbackSet() * * @param[in] p_ctrl Pointer to the DOC control block. * @param[in] p_callback Callback function @@ -167,7 +153,7 @@ typedef struct st_doc_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(doc_ctrl_t * const p_api_ctrl, void (* p_callback)(doc_callback_args_t *), + fsp_err_t (* callbackSet)(doc_ctrl_t * const p_ctrl, void (* p_callback)(doc_callback_args_t *), void const * const p_context, doc_callback_args_t * const p_callback_memory); } doc_api_t; @@ -185,5 +171,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup DOC_API) + * @} (end defgroup DOC_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_elc_api.h b/ra/fsp/inc/api/r_elc_api.h index 4b0dc2e5a..d6dffc723 100644 --- a/ra/fsp/inc/api/r_elc_api.h +++ b/ra/fsp/inc/api/r_elc_api.h @@ -84,17 +84,17 @@ typedef enum e_elc_peripheral #endif /** ELC control block. Allocate an instance specific control block to pass into the ELC API calls. - * @par Implemented as - * - elc_instance_ctrl_t */ typedef void elc_ctrl_t; /** Main configuration structure for the Event Link Controller */ typedef struct st_elc_cfg { - elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register (ELSR) settings + elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register settings } elc_cfg_t; +#ifndef BSP_OVERRIDE_ELC_SOFTWARE_EVENT_T + /** Software event number */ typedef enum e_elc_software_event { @@ -102,12 +102,12 @@ typedef enum e_elc_software_event ELC_SOFTWARE_EVENT_1, ///< Software event 1 } elc_software_event_t; +#endif + /** ELC driver structure. General ELC functions implemented at the HAL layer follow this API. */ typedef struct st_elc_api { /** Initialize all links in the Event Link Controller. - * @par Implemented as - * - @ref R_ELC_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -115,16 +115,12 @@ typedef struct st_elc_api fsp_err_t (* open)(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg); /** Disable all links in the Event Link Controller and close the API. - * @par Implemented as - * - @ref R_ELC_Close() * * @param[in] p_ctrl Pointer to control structure. **/ fsp_err_t (* close)(elc_ctrl_t * const p_ctrl); /** Generate a software event in the Event Link Controller. - * @par Implemented as - * - @ref R_ELC_SoftwareEventGenerate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] eventNum Software event number to be generated. @@ -132,8 +128,6 @@ typedef struct st_elc_api fsp_err_t (* softwareEventGenerate)(elc_ctrl_t * const p_ctrl, elc_software_event_t event_num); /** Create a single event link. - * @par Implemented as - * - @ref R_ELC_LinkSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] peripheral The peripheral block that will receive the event signal. @@ -142,8 +136,6 @@ typedef struct st_elc_api fsp_err_t (* linkSet)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal); /** Break an event link. - * @par Implemented as - * - @ref R_ELC_LinkBreak() * * @param[in] p_ctrl Pointer to control structure. * @param[in] peripheral The peripheral that should no longer be linked. @@ -151,16 +143,12 @@ typedef struct st_elc_api fsp_err_t (* linkBreak)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral); /** Enable the operation of the Event Link Controller. - * @par Implemented as - * - @ref R_ELC_Enable() * * @param[in] p_ctrl Pointer to control structure. **/ fsp_err_t (* enable)(elc_ctrl_t * const p_ctrl); /** Disable the operation of the Event Link Controller. - * @par Implemented as - * - @ref R_ELC_Disable() * * @param[in] p_ctrl Pointer to control structure. **/ @@ -181,5 +169,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup ELC_API) + * @} (end defgroup ELC_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_ether_api.h b/ra/fsp/inc/api/r_ether_api.h index ce3bb989c..6f5a1311d 100644 --- a/ra/fsp/inc/api/r_ether_api.h +++ b/ra/fsp/inc/api/r_ether_api.h @@ -33,8 +33,6 @@ * - Flow control support * - Multicast filtering support * - * Implemented by: - * - @ref ETHER * * @{ **********************************************************************************************************************/ @@ -104,14 +102,19 @@ typedef enum e_ether_padding ETHER_PADDING_3BYTE = 3, } ether_padding_t; +#ifndef BSP_OVERRIDE_ETHER_EVENT_T + /** Event code of callback function */ -typedef enum +typedef enum e_ether_event { ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event ETHER_EVENT_LINK_ON, ///< Link up detection event ETHER_EVENT_LINK_OFF, ///< Link down detection event ETHER_EVENT_INTERRUPT, ///< Interrupt event } ether_event_t; +#endif + +#ifndef BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T /** Callback function parameter data */ typedef struct st_ether_callback_args @@ -123,10 +126,9 @@ typedef struct st_ether_callback_args void const * p_context; ///< Placeholder for user data. Set in @ref ether_api_t::open function in @ref ether_cfg_t. } ether_callback_args_t; +#endif /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - ether_instance_ctrl_t */ typedef void ether_ctrl_t; @@ -150,8 +152,8 @@ typedef struct st_ether_cfg uint32_t ether_buffer_size; ///< Size of transmit and receive buffer - IRQn_Type irq; ///< NVIC interrupt number - uint32_t interrupt_priority; ///< NVIC interrupt priority + IRQn_Type irq; ///< Interrupt number + uint32_t interrupt_priority; ///< Interrupt priority void (* p_callback)(ether_callback_args_t * p_args); ///< Callback provided when an ISR occurs. @@ -166,88 +168,68 @@ typedef struct st_ether_cfg typedef struct st_ether_api { /** Open driver. - * @par Implemented as - * - @ref R_ETHER_Open() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. */ - fsp_err_t (* open)(ether_ctrl_t * const p_api_ctrl, ether_cfg_t const * const p_cfg); + fsp_err_t (* open)(ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref R_ETHER_Close() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* close)(ether_ctrl_t * const p_api_ctrl); + fsp_err_t (* close)(ether_ctrl_t * const p_ctrl); /** Read packet if data is available. - * @par Implemented as - * - @ref R_ETHER_Read() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buffer Pointer to where to store read data. * @param[in] length_bytes Number of bytes in buffer */ - fsp_err_t (* read)(ether_ctrl_t * const p_api_ctrl, void * const p_buffer, uint32_t * const length_bytes); + fsp_err_t (* read)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes); /** Release rx buffer from buffer pool process in zero-copy read operation. - * @par Implemented as - * - @ref R_ETHER_BufferRelease() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* bufferRelease)(ether_ctrl_t * const p_api_ctrl); + fsp_err_t (* bufferRelease)(ether_ctrl_t * const p_ctrl); /** Update the buffer pointer in the current receive descriptor. - * @par Implemented as - * - @ref R_ETHER_RxBufferUpdate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buffer New address to write into the rx buffer descriptor. */ - fsp_err_t (* rxBufferUpdate)(ether_ctrl_t * const p_api_ctrl, void * const p_buffer); + fsp_err_t (* rxBufferUpdate)(ether_ctrl_t * const p_ctrl, void * const p_buffer); /** Write packet. - * @par Implemented as - * - @ref R_ETHER_Write() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buffer Pointer to data to write. * @param[in] frame_length Send ethernet frame size (without 4 bytes of CRC data size). */ - fsp_err_t (* write)(ether_ctrl_t * const p_api_ctrl, void * const p_buffer, uint32_t const frame_length); + fsp_err_t (* write)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length); /** Process link. - * @par Implemented as - * - @ref R_ETHER_LinkProcess() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* linkProcess)(ether_ctrl_t * const p_api_ctrl); + fsp_err_t (* linkProcess)(ether_ctrl_t * const p_ctrl); /** Enable magic packet detection. - * @par Implemented as - * - @ref R_ETHER_WakeOnLANEnable() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* wakeOnLANEnable)(ether_ctrl_t * const p_api_ctrl); + fsp_err_t (* wakeOnLANEnable)(ether_ctrl_t * const p_ctrl); /** Get the address of the most recently sent buffer. - * @par Implemented as - * - @ref R_ETHER_TxStatusGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[out] p_buffer_address Pointer to the address of the most recently sent buffer. */ - fsp_err_t (* txStatusGet)(ether_ctrl_t * const p_api_ctrl, void * const p_buffer_address); + fsp_err_t (* txStatusGet)(ether_ctrl_t * const p_ctrl, void * const p_buffer_address); /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_ETHER_CallbackSet() * * @param[in] p_ctrl Pointer to the ETHER control block. * @param[in] p_callback Callback function @@ -255,7 +237,7 @@ typedef struct st_ether_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(ether_ctrl_t * const p_api_ctrl, void (* p_callback)(ether_callback_args_t *), + fsp_err_t (* callbackSet)(ether_ctrl_t * const p_ctrl, void (* p_callback)(ether_callback_args_t *), void const * const p_context, ether_callback_args_t * const p_callback_memory); } ether_api_t; @@ -268,7 +250,7 @@ typedef struct st_ether_instance } ether_instance_t; /*******************************************************************************************************************//** - * @} (end addtogroup ETHER_API) + * @} (end defgroup ETHER_API) **********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_ether_phy_api.h b/ra/fsp/inc/api/r_ether_phy_api.h index 5128d6978..396d132ca 100644 --- a/ra/fsp/inc/api/r_ether_phy_api.h +++ b/ra/fsp/inc/api/r_ether_phy_api.h @@ -32,8 +32,6 @@ * - Flow control support * - Link status check support * - * Implemented by: - * - @ref ETHER_PHY * * @{ **********************************************************************************************************************/ @@ -59,15 +57,19 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T + /** Phy LSI */ typedef enum e_ether_phy_lsi_type { - ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. - ETHER_PHY_LSI_TYPE_KSZ8091RNB = 1, ///< Select configuration for KSZ8091RNB. - ETHER_PHY_LSI_TYPE_KSZ8041 = 2, ///< Select configuration for KSZ8041. - ETHER_PHY_LSI_TYPE_DP83620 = 3, ///< Select configuration for DP83620. - ETHER_PHY_LSI_TYPE_ICS1894 = 4, ///< Select configuration for ICS1894. + ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. + ETHER_PHY_LSI_TYPE_KSZ8091RNB = 1, ///< Select configuration for KSZ8091RNB. + ETHER_PHY_LSI_TYPE_KSZ8041 = 2, ///< Select configuration for KSZ8041. + ETHER_PHY_LSI_TYPE_DP83620 = 3, ///< Select configuration for DP83620. + ETHER_PHY_LSI_TYPE_ICS1894 = 4, ///< Select configuration for ICS1894. + ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. } ether_phy_lsi_type_t; +#endif /** Flow control functionality */ typedef enum e_ether_phy_flow_control @@ -83,88 +85,102 @@ typedef enum e_ether_phy_link_speed ETHER_PHY_LINK_SPEED_10H = 1, ///< Link status is 10Mbit/s and half duplex ETHER_PHY_LINK_SPEED_10F = 2, ///< Link status is 10Mbit/s and full duplex ETHER_PHY_LINK_SPEED_100H = 3, ///< Link status is 100Mbit/s and half duplex - ETHER_PHY_LINK_SPEED_100F = 4 ///< Link status is 100Mbit/s and full duplex + ETHER_PHY_LINK_SPEED_100F = 4, ///< Link status is 100Mbit/s and full duplex + ETHER_PHY_LINK_SPEED_1000H = 5, ///< Link status is 1000Mbit/s and half duplex + ETHER_PHY_LINK_SPEED_1000F = 6 ///< Link status is 1000Mbit/s and full duplex } ether_phy_link_speed_t; /** Media-independent interface */ typedef enum e_ether_phy_mii_type { - ETHER_PHY_MII_TYPE_MII = 0, ///< MII - ETHER_PHY_MII_TYPE_RMII = 1, ///< RMII + ETHER_PHY_MII_TYPE_MII = 0, ///< MII + ETHER_PHY_MII_TYPE_RMII = 1, ///< RMII + ETHER_PHY_MII_TYPE_GMII = 2, ///< GMII + ETHER_PHY_MII_TYPE_RGMII = 3 ///< RGMII } ether_phy_mii_type_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - ether_phy_instance_ctrl_t */ typedef void ether_phy_ctrl_t; /** Configuration parameters. */ typedef struct st_ether_phy_cfg { - uint8_t channel; ///< Channel - uint8_t phy_lsi_address; ///< Address of PHY-LSI - - uint32_t phy_reset_wait_time; ///< Wait time for PHY-LSI reboot - int32_t mii_bit_access_wait_time; ///< Wait time for MII/RMII access + uint8_t channel; ///< Channel + uint8_t phy_lsi_address; ///< Address of PHY-LSI - ether_phy_lsi_type_t phy_lsi_type; ///< Phy LSI type + uint32_t phy_reset_wait_time; ///< Wait time for PHY-LSI reboot + int32_t mii_bit_access_wait_time; ///< Wait time for MII/RMII access + ether_phy_lsi_type_t phy_lsi_type; ///< Phy LSI type - ether_phy_flow_control_t flow_control; ///< Flow control functionally enable or disable - ether_phy_mii_type_t mii_type; ///< Interface type is MII or RMII + ether_phy_flow_control_t flow_control; ///< Flow control functionally enable or disable + ether_phy_mii_type_t mii_type; ///< Interface type is MII or RMII /** Placeholder for user data. Passed to the user callback in ether_phy_callback_args_t. */ void const * p_context; - void const * p_extend; ///< Placeholder for user extension. + void const * p_extend; ///< Placeholder for user extension. } ether_phy_cfg_t; /** Functions implemented at the HAL layer will follow this API. */ typedef struct st_ether_phy_api { /** Open driver. - * @par Implemented as - * - @ref R_ETHER_PHY_Open() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. */ - fsp_err_t (* open)(ether_phy_ctrl_t * const p_api_ctrl, ether_phy_cfg_t const * const p_cfg); + fsp_err_t (* open)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref R_ETHER_PHY_Close() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ether_phy_ctrl_t * const p_ctrl); + + /** Initialize PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* chipInit)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); + + /** Read register value of PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] reg_addr Register address. + * @param[out] p_data Pointer to the location to store read data. + */ + fsp_err_t (* read)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data); + + /** Write data to register of PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] reg_addr Register address. + * @param[in] data Data written to register. */ - fsp_err_t (* close)(ether_phy_ctrl_t * const p_api_ctrl); + fsp_err_t (* write)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data); /** Start auto negotiation. - * @par Implemented as - * - @ref R_ETHER_PHY_StartAutoNegotiate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* startAutoNegotiate)(ether_phy_ctrl_t * const p_api_ctrl); + fsp_err_t (* startAutoNegotiate)(ether_phy_ctrl_t * const p_ctrl); /** Get the partner ability. - * @par Implemented as - * - @ref R_ETHER_PHY_LinkPartnerAbilityGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[out] p_line_speed_duplex Pointer to the location of both the line speed and the duplex. - * @param[out] p_local_pause Pointer to the location to store the local pause bits. - * @param[out] p_partner_pause Pointer to the location to store the partner pause bits. + * @param[out] p_local_pause Pointer to the location to store the local pause bits. + * @param[out] p_partner_pause Pointer to the location to store the partner pause bits. */ - fsp_err_t (* linkPartnerAbilityGet)(ether_phy_ctrl_t * const p_api_ctrl, uint32_t * const p_line_speed_duplex, + fsp_err_t (* linkPartnerAbilityGet)(ether_phy_ctrl_t * const p_ctrl, uint32_t * const p_line_speed_duplex, uint32_t * const p_local_pause, uint32_t * const p_partner_pause); /** Get Link status from PHY-LSI interface. - * @par Implemented as - * - @ref R_ETHER_PHY_LinkStatusGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* linkStatusGet)(ether_phy_ctrl_t * const p_api_ctrl); + fsp_err_t (* linkStatusGet)(ether_phy_ctrl_t * const p_ctrl); } ether_phy_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ @@ -176,7 +192,7 @@ typedef struct st_ether_phy_instance } ether_phy_instance_t; /*******************************************************************************************************************//** - * @} (end addtogroup ETHER_PHY_API) + * @} (end defgroup ETHER_PHY_API) **********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_external_irq_api.h b/ra/fsp/inc/api/r_external_irq_api.h index 1f60b32dd..447712918 100644 --- a/ra/fsp/inc/api/r_external_irq_api.h +++ b/ra/fsp/inc/api/r_external_irq_api.h @@ -27,8 +27,6 @@ * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an * external IRQ pin. * - * The External IRQ Interface can be implemented by: - * - @ref ICU * * @{ **********************************************************************************************************************/ @@ -62,35 +60,42 @@ typedef struct st_external_irq_callback_args uint32_t channel; ///< The physical hardware channel that caused the interrupt. } external_irq_callback_args_t; +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_TRIGGER_T + /** Condition that will trigger an interrupt when detected. */ typedef enum e_external_irq_trigger { - EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger - EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger - EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger - EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger + EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger + EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger + EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger + EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger + EXTERNAL_IRQ_TRIG_LEVEL_HIGH = 4 ///< High level trigger } external_irq_trigger_t; +#endif + +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_PCLK_DIV_T /** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger * conditions that are shorter than 3 periods of the filter clock. */ -typedef enum e_external_irq_pclk_div +typedef enum e_external_irq_clock_source_div { - EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1 - EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8 - EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32 - EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64 -} external_irq_pclk_div_t; + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1 = 0, ///< Filter using clock source divided by 1 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_8 = 1, ///< Filter using clock source divided by 8 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_32 = 2, ///< Filter using clock source divided by 32 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64 = 3, ///< Filter using clock source divided by 64 +} external_irq_clock_source_div_t; +#endif /** User configuration structure, used in open function */ typedef struct st_external_irq_cfg { - uint8_t channel; ///< Hardware channel used. - uint8_t ipl; ///< Interrupt priority - IRQn_Type irq; ///< NVIC interrupt number assigned to this instance - external_irq_trigger_t trigger; ///< Trigger setting. - external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting. - bool filter_enable; ///< Digital filter enable/disable setting. + uint8_t channel; ///< Hardware channel used. + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt number assigned to this instance + external_irq_trigger_t trigger; ///< Trigger setting. + external_irq_clock_source_div_t clock_source_div; ///< Digital filter clock divisor setting. + bool filter_enable; ///< Digital filter enable/disable setting. /** Callback provided external input trigger occurs. */ void (* p_callback)(external_irq_callback_args_t * p_args); @@ -101,8 +106,6 @@ typedef struct st_external_irq_cfg } external_irq_cfg_t; /** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. - * @par Implemented as - * - icu_instance_ctrl_t */ typedef void external_irq_ctrl_t; @@ -110,8 +113,6 @@ typedef void external_irq_ctrl_t; typedef struct st_external_irq_api { /** Initial configuration. - * @par Implemented as - * - @ref R_ICU_ExternalIrqOpen() * * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. @@ -119,16 +120,12 @@ typedef struct st_external_irq_api fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); /** Enable callback when an external trigger condition occurs. - * @par Implemented as - * - @ref R_ICU_ExternalIrqEnable() * * @param[in] p_ctrl Control block set in Open call for this external interrupt. */ fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); /** Disable callback when external trigger condition occurs. - * @par Implemented as - * - @ref R_ICU_ExternalIrqDisable() * * @param[in] p_ctrl Control block set in Open call for this external interrupt. */ @@ -136,23 +133,17 @@ typedef struct st_external_irq_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_ICU_ExternalIrqCallbackSet() * - * @param[in] p_ctrl Pointer to the Extneral IRQ control block. + * @param[in] p_ctrl Pointer to the External IRQ control block. * @param[in] p_callback Callback function * @param[in] p_context Pointer to send to callback function * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl, - void ( * p_callback)(external_irq_callback_args_t *), - void const * const p_context, - external_irq_callback_args_t * const p_callback_memory); + fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_ctrl, void (* p_callback)(external_irq_callback_args_t *), + void const * const p_context, external_irq_callback_args_t * const p_callback_memory); /** Allow driver to be reconfigured. May reduce power consumption. - * @par Implemented as - * - @ref R_ICU_ExternalIrqClose() * * @param[in] p_ctrl Control block set in Open call for this external interrupt. */ diff --git a/ra/fsp/inc/api/r_flash_api.h b/ra/fsp/inc/api/r_flash_api.h index bb96af929..348cb224f 100644 --- a/ra/fsp/inc/api/r_flash_api.h +++ b/ra/fsp/inc/api/r_flash_api.h @@ -28,8 +28,6 @@ * The Flash interface provides the ability to read, write, erase, and blank check the code flash and data flash * regions. * - * The Flash interface is implemented by: - * - @ref FLASH_LP * * @{ **********************************************************************************************************************/ @@ -124,9 +122,6 @@ typedef struct st_flash_info } flash_info_t; /** Flash control block. Allocate an instance specific control block to pass into the flash API calls. - * @par Implemented as - * - flash_lp_instance_ctrl_t - * - flash_hp_instance_ctrl_t */ typedef void flash_ctrl_t; @@ -158,9 +153,6 @@ typedef struct st_flash_cfg typedef struct st_flash_api { /** Open FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_Open() - * - @ref R_FLASH_HP_Open() * * @param[out] p_ctrl Pointer to FLASH device control. Must be declared by user. Value set here. * @param[in] flash_cfg_t Pointer to FLASH configuration structure. All elements of this structure @@ -169,9 +161,6 @@ typedef struct st_flash_api fsp_err_t (* open)(flash_ctrl_t * const p_ctrl, flash_cfg_t const * const p_cfg); /** Write FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_Write() - * - @ref R_FLASH_HP_Write() * * @param[in] p_ctrl Control for the FLASH device context. * @param[in] src_address Address of the buffer containing the data to write to Flash. @@ -187,9 +176,6 @@ typedef struct st_flash_api uint32_t const num_bytes); /** Erase FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_Erase() - * - @ref R_FLASH_HP_Erase() * * @param[in] p_ctrl Control for the FLASH device. * @param[in] address The block containing this address is the first block erased. @@ -199,14 +185,11 @@ typedef struct st_flash_api fsp_err_t (* erase)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_blocks); /** Blank check FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_BlankCheck() - * - @ref R_FLASH_HP_BlankCheck() * - * @param[in] p_ctrl Control for the FLASH device context. - * @param[in] address The starting address of the Flash area to blank check. - * @param[in] num_bytes Specifies the number of bytes that need to be checked. - * See the specific handler for details. + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * See the specific handler for details. * @param[out] p_blank_check_result Pointer that will be populated by the API with the results of the blank check * operation in non-BGO (blocking) mode. In this case the blank check operation * completes here and the result is returned. In Data Flash BGO mode the blank @@ -218,9 +201,6 @@ typedef struct st_flash_api flash_result_t * const p_blank_check_result); /** Close FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_InfoGet() - * - @ref R_FLASH_HP_InfoGet() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[out] p_info Pointer to FLASH info structure. @@ -228,18 +208,12 @@ typedef struct st_flash_api fsp_err_t (* infoGet)(flash_ctrl_t * const p_ctrl, flash_info_t * const p_info); /** Close FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_Close() - * - @ref R_FLASH_HP_Close() * * @param[in] p_ctrl Pointer to FLASH device control. */ fsp_err_t (* close)(flash_ctrl_t * const p_ctrl); /** Get Status for FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_StatusGet() - * - @ref R_FLASH_HP_StatusGet() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[out] p_ctrl Pointer to the current flash status. @@ -247,9 +221,6 @@ typedef struct st_flash_api fsp_err_t (* statusGet)(flash_ctrl_t * const p_ctrl, flash_status_t * const p_status); /** Set Access Window for FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_AccessWindowSet() - * - @ref R_FLASH_HP_AccessWindowSet() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[in] start_addr Determines the Starting block for the Code Flash access window. @@ -259,9 +230,6 @@ typedef struct st_flash_api fsp_err_t (* accessWindowSet)(flash_ctrl_t * const p_ctrl, uint32_t const start_addr, uint32_t const end_addr); /** Clear any existing Code Flash access window for FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_AccessWindowClear() - * - @ref R_FLASH_HP_AccessWindowClear() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[in] start_addr Determines the Starting block for the Code Flash access window. @@ -280,9 +248,6 @@ typedef struct st_flash_api * With mode FLASH_ID_CODE_MODE_LOCKED, it * will result in an ID code of 00112233445566778899aabbccddee80 * - * @par Implemented as - * - @ref R_FLASH_LP_IdCodeSet() - * - @ref R_FLASH_HP_IdCodeSet() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[in] p_id_bytes Ponter to the ID Code to be written. @@ -291,26 +256,17 @@ typedef struct st_flash_api fsp_err_t (* idCodeSet)(flash_ctrl_t * const p_ctrl, uint8_t const * const p_id_bytes, flash_id_code_mode_t mode); /** Reset function for FLASH device. - * @par Implemented as - * - @ref R_FLASH_LP_Reset() - * - @ref R_FLASH_HP_Reset() * * @param[in] p_ctrl Pointer to FLASH device control. */ fsp_err_t (* reset)(flash_ctrl_t * const p_ctrl); /** Update Flash clock frequency (FCLK) and recalculate timeout values - * @par Implemented as - * - @ref R_FLASH_LP_UpdateFlashClockFreq() - * - @ref R_FLASH_HP_UpdateFlashClockFreq() * @param[in] p_ctrl Pointer to FLASH device control. */ fsp_err_t (* updateFlashClockFreq)(flash_ctrl_t * const p_ctrl); /** Select which block - Default (Block 0) or Alternate (Block 1) is used as the start-up area block. - * @par Implemented as - * - @ref R_FLASH_LP_StartUpAreaSelect() - * - @ref R_FLASH_HP_StartUpAreaSelect() * * @param[in] p_ctrl Pointer to FLASH device control. * @param[in] swap_type FLASH_STARTUP_AREA_BLOCK0, FLASH_STARTUP_AREA_BLOCK1 or FLASH_STARTUP_AREA_BTFLG. @@ -326,17 +282,13 @@ typedef struct st_flash_api fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type, bool is_temporary); - /** Swap the bank used as the startup area. Only valid in dual bank mode. - * @par Implemented as - * - @ref R_FLASH_HP_BankSwap() + /** Swap the bank used as the startup area. On Flash HP, need to change into dual bank mode to use this feature. * * @param[in] p_ctrl Pointer to FLASH device control. */ fsp_err_t (* bankSwap)(flash_ctrl_t * const p_ctrl); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_FLASH_HP_CallbackSet() * * @param[in] p_ctrl Control block set in @ref flash_api_t::open call for this timer. * @param[in] p_callback Callback function to register @@ -344,7 +296,7 @@ typedef struct st_flash_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(flash_ctrl_t * const p_api_ctrl, void (* p_callback)(flash_callback_args_t *), + fsp_err_t (* callbackSet)(flash_ctrl_t * const p_ctrl, void (* p_callback)(flash_callback_args_t *), void const * const p_context, flash_callback_args_t * const p_callback_memory); } flash_api_t; diff --git a/ra/fsp/inc/api/r_i2c_master_api.h b/ra/fsp/inc/api/r_i2c_master_api.h index 733f3c71a..5de71033b 100644 --- a/ra/fsp/inc/api/r_i2c_master_api.h +++ b/ra/fsp/inc/api/r_i2c_master_api.h @@ -31,11 +31,6 @@ * - Interrupt driven transmit/receive processing * - Callback function support which can return an event code * - * Implemented by: - * - @ref IIC_MASTER - * - @ref SCI_I2C - * - @ref IIC_B_MASTER - * - @ref SCI_B_I2C * * @{ **********************************************************************************************************************/ @@ -109,9 +104,9 @@ typedef struct st_i2c_master_cfg IRQn_Type tei_irq; ///< Transmit end IRQ number IRQn_Type eri_irq; ///< Error IRQ number - /** DTC support */ - transfer_instance_t const * p_transfer_tx; ///< DTC instance for I2C transmit.Set to NULL if unused. - transfer_instance_t const * p_transfer_rx; ///< DTC instance for I2C receive. Set to NULL if unused. + /** Transfer API support */ + transfer_instance_t const * p_transfer_tx; ///< Transfer instance for I2C transmit. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< Transfer instance for I2C receive. Set to NULL if unused. /** Parameters to control software behavior */ void (* p_callback)(i2c_master_callback_args_t * p_args); ///< Pointer to callback function @@ -122,8 +117,6 @@ typedef struct st_i2c_master_cfg } i2c_master_cfg_t; /** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. - * @par Implemented as - * - iic_master_instance_ctrl_t */ typedef void i2c_master_ctrl_t; @@ -131,11 +124,6 @@ typedef void i2c_master_ctrl_t; typedef struct st_i2c_master_api { /** Opens the I2C Master driver and initializes the hardware. - * @par Implemented as - * - @ref R_IIC_MASTER_Open() - * - @ref R_SCI_I2C_Open() - * - @ref R_IIC_B_MASTER_Open() - * - @ref R_SCI_B_I2C_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. * @param[in] p_cfg Pointer to configuration structure. @@ -143,13 +131,8 @@ typedef struct st_i2c_master_api fsp_err_t (* open)(i2c_master_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); /** Performs a read operation on an I2C Master device. - * @par Implemented as - * - @ref R_SCI_I2C_Read() - * - @ref R_IIC_MASTER_Read() - * - @ref R_IIC_B_MASTER_Read() - * - @ref R_SCI_B_I2C_Read() * - * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. * @param[in] p_dest Pointer to the location to store read data. * @param[in] bytes Number of bytes to read. * @param[in] restart Specify if the restart condition should be issued after reading. @@ -158,13 +141,8 @@ typedef struct st_i2c_master_api bool const restart); /** Performs a write operation on an I2C Master device. - * @par Implemented as - * - @ref R_IIC_MASTER_Write() - * - @ref R_SCI_I2C_Write() - * - @ref R_IIC_B_MASTER_Write() - * - @ref R_SCI_B_I2C_Write() * - * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. * @param[in] p_src Pointer to the location to get write data from. * @param[in] bytes Number of bytes to write. * @param[in] restart Specify if the restart condition should be issued after writing. @@ -173,24 +151,14 @@ typedef struct st_i2c_master_api bool const restart); /** Performs a reset of the peripheral. - * @par Implemented as - * - @ref R_IIC_MASTER_Abort() - * - @ref R_SCI_I2C_Abort() - * - @ref R_IIC_B_MASTER_Abort() - * - @ref R_SCI_B_I2C_Abort() * - * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. */ fsp_err_t (* abort)(i2c_master_ctrl_t * const p_ctrl); /** Sets address of the slave device without reconfiguring the bus. - * @par Implemented as - * - @ref R_IIC_MASTER_SlaveAddressSet() - * - @ref R_SCI_I2C_SlaveAddressSet() - * - @ref R_IIC_B_MASTER_SlaveAddressSet() - * - @ref R_SCI_B_I2C_SlaveAddressSet() * - * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. * @param[in] slave_address Address of the slave device. * @param[in] address_mode Addressing mode. */ @@ -199,11 +167,6 @@ typedef struct st_i2c_master_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_IIC_MASTER_CallbackSet() - * - @ref R_SCI_I2C_CallbackSet() - * - @ref R_IIC_B_MASTER_CallbackSet() - * - @ref R_SCI_B_I2C_CallbackSet() * * @param[in] p_ctrl Pointer to the IIC Master control block. * @param[in] p_callback Callback function @@ -211,29 +174,19 @@ typedef struct st_i2c_master_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_master_callback_args_t *), + fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_ctrl, void (* p_callback)(i2c_master_callback_args_t *), void const * const p_context, i2c_master_callback_args_t * const p_callback_memory); /** Gets the status of the configured I2C device. - * @par Implemented as - * - @ref R_IIC_MASTER_StatusGet() - * - @ref R_SCI_I2C_StatusGet() - * - @ref R_IIC_B_MASTER_StatusGet() - * - @ref R_SCI_B_I2C_StatusGet() * * @param[in] p_ctrl Pointer to the IIC Master control block. * @param[out] p_status Pointer to store current status. */ - fsp_err_t (* statusGet)(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + fsp_err_t (* statusGet)(i2c_master_ctrl_t * const p_ctrl, i2c_master_status_t * p_status); /** Closes the driver and releases the I2C Master device. - * @par Implemented as - * - @ref R_IIC_MASTER_Close() - * - @ref R_SCI_I2C_Close() - * - @ref R_IIC_B_MASTER_Close() - * - @ref R_SCI_B_I2C_Close() * - * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. */ fsp_err_t (* close)(i2c_master_ctrl_t * const p_ctrl); } i2c_master_api_t; @@ -247,7 +200,7 @@ typedef struct st_i2c_master_instance } i2c_master_instance_t; /******************************************************************************************************************//** - * @} (end addtogroup I2C_MASTER_API) + * @} (end defgroup I2C_MASTER_API) *********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_i2c_slave_api.h b/ra/fsp/inc/api/r_i2c_slave_api.h index 1ec67ef94..66b6256d8 100644 --- a/ra/fsp/inc/api/r_i2c_slave_api.h +++ b/ra/fsp/inc/api/r_i2c_slave_api.h @@ -31,9 +31,6 @@ * - Interrupt driven transmit/receive processing * - Callback function support which returns a event codes * - * Implemented by: - * - @ref IIC_SLAVE - * - @ref IIC_B_SLAVE * * @{ **********************************************************************************************************************/ @@ -44,6 +41,7 @@ /* Register definitions, common services and error codes. */ #include "bsp_api.h" +#include "r_transfer_api.h" /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ FSP_HEADER @@ -106,10 +104,14 @@ typedef struct st_i2c_slave_cfg IRQn_Type txi_irq; ///< Transmit IRQ number IRQn_Type tei_irq; ///< Transmit end IRQ number IRQn_Type eri_irq; ///< Error IRQ number - uint8_t ipl; ///< Interrupt priority level for RXI, TXI and TER interrupts - uint8_t eri_ipl; ///< Interrupt priority level for ERI interrupt + uint8_t ipl; ///< Interrupt priority level for receive, transmit, and transmit end interrupts + uint8_t eri_ipl; ///< Interrupt priority level for error interrupt bool clock_stretching_enable; ///< Low Hold SCL during reception for the period between the 9th and the 1st clock cycle + /** DTC support */ + transfer_instance_t const * p_transfer_tx; ///< DTC instance for I2C transmit.Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< DTC instance for I2C receive. Set to NULL if unused. + /** Parameters to control software behavior */ void (* p_callback)(i2c_slave_callback_args_t * p_args); ///< Pointer to callback function void const * p_context; ///< Pointer to the user-provided context @@ -119,8 +121,6 @@ typedef struct st_i2c_slave_cfg } i2c_slave_cfg_t; /** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. - * @par Implemented as - * - iic_slave_instance_ctrl_t */ typedef void i2c_slave_ctrl_t; @@ -128,9 +128,6 @@ typedef void i2c_slave_ctrl_t; typedef struct st_i2c_slave_api { /** Opens the I2C Slave driver and initializes the hardware. - * @par Implemented as - * - @ref R_IIC_SLAVE_Open() - * - @ref R_IIC_B_SLAVE_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. * @param[in] p_cfg Pointer to configuration structure. @@ -138,9 +135,6 @@ typedef struct st_i2c_slave_api fsp_err_t (* open)(i2c_slave_ctrl_t * const p_ctrl, i2c_slave_cfg_t const * const p_cfg); /** Performs a read operation on an I2C Slave device. - * @par Implemented as - * - @ref R_IIC_SLAVE_Read() - * - @ref R_IIC_B_SLAVE_Read() * * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. * @param[in] p_dest Pointer to the location to store read data. @@ -149,9 +143,6 @@ typedef struct st_i2c_slave_api fsp_err_t (* read)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); /** Performs a write operation on an I2C Slave device. - * @par Implemented as - * - @ref R_IIC_SLAVE_Write() - * - @ref R_IIC_B_SLAVE_Write() * * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. * @param[in] p_src Pointer to the location to get write data from. @@ -161,9 +152,6 @@ typedef struct st_i2c_slave_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_IIC_SLAVE_CallbackSet() - * - @ref R_IIC_B_SLAVE_CallbackSet() * * @param[in] p_ctrl Pointer to the IIC Slave control block. * @param[in] p_callback Callback function @@ -171,13 +159,10 @@ typedef struct st_i2c_slave_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(i2c_slave_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_slave_callback_args_t *), + fsp_err_t (* callbackSet)(i2c_slave_ctrl_t * const p_ctrl, void (* p_callback)(i2c_slave_callback_args_t *), void const * const p_context, i2c_slave_callback_args_t * const p_callback_memory); /** Closes the driver and releases the I2C Slave device. - * @par Implemented as - * - @ref R_IIC_SLAVE_Close() - * - @ref R_IIC_B_SLAVE_Close() * * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. */ @@ -193,7 +178,7 @@ typedef struct st_i2c_slave_instance } i2c_slave_instance_t; /******************************************************************************************************************//** - * @} (end addtogroup I2C_SLAVE_API) + * @} (end defgroup I2C_SLAVE_API) *********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_i2s_api.h b/ra/fsp/inc/api/r_i2s_api.h index 35d51428b..bdb3d522e 100644 --- a/ra/fsp/inc/api/r_i2s_api.h +++ b/ra/fsp/inc/api/r_i2s_api.h @@ -26,8 +26,6 @@ * @section I2S_API_SUMMARY Summary * @brief The I2S (Inter-IC Sound) interface provides APIs and definitions for I2S audio communication. * - * @section I2S_API_INSTANCES Known Implementations - * @ref SSI * @{ **********************************************************************************************************************/ @@ -40,7 +38,9 @@ /* Register definitions, common services and error codes. */ #include "bsp_api.h" -#include "r_timer_api.h" +#ifndef BSP_OVERRIDE_I2S_INCLUDE + #include "r_timer_api.h" +#endif #include "r_transfer_api.h" /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ @@ -53,6 +53,7 @@ FSP_HEADER /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_I2S_PCM_WIDTH_T /** Audio PCM width */ typedef enum e_i2s_pcm_width @@ -63,8 +64,11 @@ typedef enum e_i2s_pcm_width I2S_PCM_WIDTH_20_BITS = 3, ///< Using 20-bit PCM I2S_PCM_WIDTH_22_BITS = 4, ///< Using 22-bit PCM I2S_PCM_WIDTH_24_BITS = 5, ///< Using 24-bit PCM - I2S_PCM_WIDTH_32_BITS = 6, ///< Using 24-bit PCM + I2S_PCM_WIDTH_32_BITS = 6, ///< Using 32-bit PCM } i2s_pcm_width_t; +#endif + +#ifndef BSP_OVERRIDE_I2S_WORD_LENGTH_T /** Audio system word length. */ typedef enum e_i2s_word_length @@ -78,6 +82,7 @@ typedef enum e_i2s_word_length I2S_WORD_LENGTH_128_BITS = 6, ///< Using 128-bit system word length I2S_WORD_LENGTH_256_BITS = 7, ///< Using 256-bit system word length } i2s_word_length_t; +#endif /** Events that can trigger a callback function */ typedef enum e_i2s_event @@ -87,12 +92,15 @@ typedef enum e_i2s_event I2S_EVENT_RX_FULL, ///< Receive buffer is above FIFO trigger level } i2s_event_t; +#ifndef BSP_OVERRIDE_I2S_MODE_T + /** I2S communication mode */ typedef enum e_i2s_mode { I2S_MODE_SLAVE = 0, ///< Slave mode I2S_MODE_MASTER = 1, ///< Master mode } i2s_mode_t; +#endif /** Mute audio samples. */ typedef enum e_i2s_mute @@ -124,8 +132,6 @@ typedef struct st_i2s_callback_args } i2s_callback_args_t; /** I2S control block. Allocate an instance specific control block to pass into the I2S API calls. - * @par Implemented as - * - ssi_instance_ctrl_t */ typedef void i2s_ctrl_t; @@ -145,10 +151,10 @@ typedef struct st_i2s_cfg i2s_ws_continue_t ws_continue; ///< Whether to continue WS transmission during idle state. i2s_mode_t operating_mode; ///< Master or slave mode - /** To use DTC during write, link a DTC instance here. Set to NULL if unused. */ + /** To use DMA for transmitting link a Transfer instance here. Set to NULL if unused. */ transfer_instance_t const * p_transfer_tx; - /** To use DTC during read, link a DTC instance here. Set to NULL if unused. */ + /** To use DMA for receiving link a Transfer instance here. Set to NULL if unused. */ transfer_instance_t const * p_transfer_rx; /** Callback provided when an I2S ISR occurs. Set to NULL for no CPU interrupt. */ @@ -169,8 +175,6 @@ typedef struct st_i2s_cfg typedef struct st_i2s_api { /** Initial configuration. - * @par Implemented as - * - @ref R_SSI_Open() * * @pre Peripheral clocks and any required output pins should be configured prior to calling this function. * @note To reconfigure after calling this function, call @ref i2s_api_t::close first. @@ -181,16 +185,12 @@ typedef struct st_i2s_api /** Stop communication. Communication is stopped when callback is called with I2S_EVENT_IDLE. * - * @par Implemented as - * - @ref R_SSI_Stop() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. */ fsp_err_t (* stop)(i2s_ctrl_t * const p_ctrl); /** Enable or disable mute. - * @par Implemented as - * - @ref R_SSI_Mute() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. * @param[in] mute_enable Whether to enable or disable mute. @@ -199,8 +199,6 @@ typedef struct st_i2s_api /** Write I2S data. All transmit data is queued when callback is called with I2S_EVENT_TX_EMPTY. * Transmission is complete when callback is called with I2S_EVENT_IDLE. - * @par Implemented as - * - @ref R_SSI_Write() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. @@ -210,8 +208,6 @@ typedef struct st_i2s_api fsp_err_t (* write)(i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes); /** Read I2S data. Reception is complete when callback is called with I2S_EVENT_RX_EMPTY. - * @par Implemented as - * - @ref R_SSI_Read() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. @@ -222,8 +218,6 @@ typedef struct st_i2s_api /** Simultaneously write and read I2S data. Transmission and reception are complete when * callback is called with I2S_EVENT_IDLE. - * @par Implemented as - * - @ref R_SSI_WriteRead() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. @@ -236,8 +230,6 @@ typedef struct st_i2s_api uint32_t const bytes); /** Get current status and store it in provided pointer p_status. - * @par Implemented as - * - @ref R_SSI_StatusGet() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. * @param[out] p_status Current status of the driver. @@ -245,8 +237,6 @@ typedef struct st_i2s_api fsp_err_t (* statusGet)(i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status); /** Allows driver to be reconfigured and may reduce power consumption. - * @par Implemented as - * - @ref R_SSI_Close() * * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. */ @@ -254,8 +244,6 @@ typedef struct st_i2s_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_SSI_CallbackSet() * * @param[in] p_ctrl Pointer to the I2S control block. * @param[in] p_callback Callback function @@ -263,7 +251,7 @@ typedef struct st_i2s_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(i2s_ctrl_t * const p_api_ctrl, void (* p_callback)(i2s_callback_args_t *), + fsp_err_t (* callbackSet)(i2s_ctrl_t * const p_ctrl, void (* p_callback)(i2s_callback_args_t *), void const * const p_context, i2s_callback_args_t * const p_callback_memory); } i2s_api_t; @@ -281,5 +269,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup I2S_API) + * @} (end defgroup I2S_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_i3c_api.h b/ra/fsp/inc/api/r_i3c_api.h index 3f2c2313f..6090b1f54 100644 --- a/ra/fsp/inc/api/r_i3c_api.h +++ b/ra/fsp/inc/api/r_i3c_api.h @@ -26,8 +26,6 @@ * @section I3C_API_SUMMARY Summary * @brief The I3C interface provides APIs and definitions for I3C communication. * - * @section I3C_API_INSTANCES Known Implementations - * @ref I3C * @{ **********************************************************************************************************************/ @@ -328,8 +326,6 @@ typedef struct st_i3c_cfg } i3c_cfg_t; /** I3C control block. Allocate an instance specific control block to pass into the I3C API calls. - * @par Implemented as - * - i3c_instance_ctrl_t */ typedef void i3c_ctrl_t; @@ -337,8 +333,6 @@ typedef void i3c_ctrl_t; typedef struct st_i3c_api { /** Initial configuration. - * @par Implemented as - * - @ref R_I3C_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -348,8 +342,6 @@ typedef struct st_i3c_api /** * Enable the I3C device. * - * @par Implemented as - * - @ref R_I3C_Enable() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. */ @@ -358,8 +350,6 @@ typedef struct st_i3c_api /** * Set the configuration of this device. * - * @par Implemented as - * - @ref R_I3C_DeviceCfgSet() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_device_cfg Pointer to device configuration. @@ -372,8 +362,6 @@ typedef struct st_i3c_api * * Note: This function is not used in slave mode. * - * @par Implemented as - * - @ref R_I3C_MasterDeviceTableSet() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] device_index Index into the device table. @@ -387,8 +375,6 @@ typedef struct st_i3c_api * * Note: This function is not used in slave mode. * - * @par Implemented as - * - @ref R_I3C_DeviceSelect() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] device_index Index into the device table. @@ -401,8 +387,6 @@ typedef struct st_i3c_api * * Note: This function is not used in slave mode. * - * @par Implemented as - * - @ref R_I3C_DynamicAddressAssignmentStart() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] address_assignment_mode The command to use for Dynamic Address Assignment. @@ -418,8 +402,6 @@ typedef struct st_i3c_api * * Note: This function is not used in master mode. * - * @par Implemented as - * - @ref R_I3C_SlaveStatusSet() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] device_status New status settings for responding to the GETSTATUS command code. @@ -431,8 +413,6 @@ typedef struct st_i3c_api * * Note: This function is not used in slave mode. * - * @par Implemented as - * - @ref R_I3C_CommandSend() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_command_descriptor A descriptor for executing the command. @@ -444,8 +424,6 @@ typedef struct st_i3c_api * In slave mode: Set the write buffer and configure the number of bytes that will be transferred before the the transfer * is ended by the slave via the 'T' bit or by the master issueing a stop condition. * - * @par Implemented as - * - @ref R_I3C_Write() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_data Pointer to a buffer to write. @@ -460,8 +438,6 @@ typedef struct st_i3c_api * will receive a callback requesting a new read buffer. If no buffer is provided by the application, the driver will * discard any remaining bytes read during the transfer. * - * @par Implemented as - * - @ref R_I3C_Read() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_data Pointer to a buffer to store the bytes read during the transfer. @@ -475,8 +451,6 @@ typedef struct st_i3c_api * * Note: This function is not used in master mode. * - * @par Implemented as - * - @ref R_I3C_IbiWrite() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_data Pointer to a buffer to start the bytes read during the transfer. @@ -488,8 +462,6 @@ typedef struct st_i3c_api /** * Set the read buffer for storing received IBI data (This function is not used in slave mode). * - * @par Implemented as - * - @ref R_I3C_IbiRead() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. * @param[in] p_data Pointer to a buffer to store the bytes read during the transfer. @@ -498,8 +470,6 @@ typedef struct st_i3c_api fsp_err_t (* ibiRead)(i3c_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t length); /** Allows driver to be reconfigured and may reduce power consumption. - * @par Implemented as - * - @ref R_I3C_Close() * * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. */ @@ -520,5 +490,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup I3C_API) + * @} (end defgroup I3C_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_iir_api.h b/ra/fsp/inc/api/r_iir_api.h index 29ef5a5ff..f7a2f4ad0 100644 --- a/ra/fsp/inc/api/r_iir_api.h +++ b/ra/fsp/inc/api/r_iir_api.h @@ -27,8 +27,6 @@ * The IIR interface allows access to the IIRFA peripheral for hardware acceleration of direct form 2 * transposed biquad IIR filters. * - * Implemented by: - * - @ref IIRFA * * @{ **********************************************************************************************************************/ @@ -94,8 +92,6 @@ typedef struct st_iir_cfg } iir_cfg_t; /** IIR control block. Allocate an instance specific control block to pass into the DAC API calls. - * @par Implemented as - * - iirfa_instance_ctrl_t */ typedef void iir_ctrl_t; @@ -103,8 +99,6 @@ typedef void iir_ctrl_t; typedef struct st_iir_api { /** Initial configuration. - * @par Implemented as - * - @ref R_IIRFA_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -112,16 +106,12 @@ typedef struct st_iir_api fsp_err_t (* open)(iir_ctrl_t * const p_ctrl, iir_cfg_t const * const p_cfg); /** Close the IIRFA channel. - * @par Implemented as - * - @ref R_IIRFA_Close() * * @param[in] p_ctrl Control block set in @ref iir_api_t::open. */ fsp_err_t (* close)(iir_ctrl_t * const p_ctrl); /** Configure filter coefficients and state variables. - * @par Implemented as - * - @ref R_IIRFA_Configure() * * @param[in] p_ctrl Control block set in @ref iir_api_t::open. * @param[in] p_filter_cfg Pointer to filter configuration to write. @@ -129,8 +119,6 @@ typedef struct st_iir_api fsp_err_t (* configure)(iir_ctrl_t * const p_ctrl, iir_filter_cfg_t const * const p_filter_cfg); /** Filter the specified data. - * @par Implemented as - * - @ref R_IIRFA_Filter() * * @param[in] p_ctrl Control block set in @ref iir_api_t::open. * @param[in] p_data_in Pointer to float input data. @@ -141,8 +129,6 @@ typedef struct st_iir_api uint16_t const num_samples); /** Retrieve current status (including state registers). - * @par Implemented as - * - @ref R_IIRFA_StatusGet() * * @param[in] p_ctrl Control block set in @ref iir_api_t::open. * @param[in] p_status Pointer to status struct. diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h index 533d483a2..ad9106e9e 100644 --- a/ra/fsp/inc/api/r_ioport_api.h +++ b/ra/fsp/inc/api/r_ioport_api.h @@ -27,7 +27,6 @@ * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. * Port and pin direction can be changed. * - * IOPORT Interface description: @ref IOPORT * * @{ **********************************************************************************************************************/ @@ -49,206 +48,31 @@ FSP_HEADER * Macro definitions **********************************************************************************************************************/ -/* Private definition to set enumeration values. */ -#define IOPORT_PRV_PFS_PSEL_OFFSET (24) - /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T /** IO port type used with ports */ -typedef uint16_t ioport_size_t; ///< IO port size on this device - -/** Superset of all peripheral functions. */ -typedef enum e_ioport_peripheral -{ - /** Pin will functions as an IO pin */ - IOPORT_PERIPHERAL_IO = 0x00, - - /** Pin will function as a DEBUG pin */ - IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an AGT peripheral pin */ - IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI peripheral pin */ - IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a SPI peripheral pin */ - IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a IIC peripheral pin */ - IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a KEY peripheral pin */ - IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a clock/comparator/RTC peripheral pin */ - IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC/ADC peripheral pin */ - IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a BUS peripheral pin */ - IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CTSU peripheral pin */ - IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CMPHS peripheral pin */ - IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a segment LCD peripheral pin */ - IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - -#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), -#else - - /** Pin will function as an SCI peripheral DEn pin */ - IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SCI DEn peripheral pin */ - IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +typedef uint16_t ioport_size_t; ///< IO port size #endif - /** Pin will function as a DALI peripheral pin */ - IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEU peripheral pin */ - IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAN peripheral pin */ - IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a QSPI peripheral pin */ - IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SSI peripheral pin */ - IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB full speed peripheral pin */ - IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a USB high speed peripheral pin */ - IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an SD/MMC peripheral pin */ - IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet MMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a GPT peripheral pin */ - IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as an Ethernet RMMI peripheral pin */ - IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PDC peripheral pin */ - IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a graphics LCD peripheral pin */ - IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CAC peripheral pin */ - IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a debug trace peripheral pin */ - IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a OSPI peripheral pin */ - IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a CEC peripheral pin */ - IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a PGAOUT peripheral pin */ - IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a ULPT peripheral pin */ - IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), - - /** Pin will function as a MIPI DSI peripheral pin */ - IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), -} ioport_peripheral_t; - -/** Options to configure pin functions */ -typedef enum e_ioport_cfg_options -{ - IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) - IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output - IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low - IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high - IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up - IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode - IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output - IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput - IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium - IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed - IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port - IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high - IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge - IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge - IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges - IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin - IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin - IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin -} ioport_cfg_options_t; - -/* PFS writing enable/disable. */ -typedef enum e_ioport_pwpr -{ - IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access - IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access -} ioport_pwpr_t; - -/** Pin identifier and pin PFS pin configuration value */ +/** Pin identifier and pin configuration value */ typedef struct st_ioport_pin_cfg { - uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure bsp_io_port_pin_t pin; ///< Pin identifier } ioport_pin_cfg_t; -/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */ +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ typedef struct st_ioport_cfg { uint16_t number_of_pins; ///< Number of pins for which there is configuration data ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration } ioport_cfg_t; /** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. - * @par Implemented as - * - ioport_instance_ctrl_t */ typedef void ioport_ctrl_t; @@ -258,88 +82,86 @@ typedef struct st_ioport_api /** Initialize internal driver data and initial pin configurations. Called during startup. Do * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of * multiple pins. - * @par Implemented as - * - @ref R_IOPORT_Open() - * @param[in] p_cfg Pointer to pin configuration data array. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. */ fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); /** Close the API. - * @par Implemented as - * - @ref R_IOPORT_Close() * * @param[in] p_ctrl Pointer to control structure. **/ fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); /** Configure multiple pins. - * @par Implemented as - * - @ref R_IOPORT_PinsCfg() - * @param[in] p_cfg Pointer to pin configuration data array. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. */ fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); /** Configure settings for an individual pin. - * @par Implemented as - * - @ref R_IOPORT_PinCfg() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] pin Pin to be read. * @param[in] cfg Configuration options for the pin. */ fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); /** Read the event input data of the specified pin and return the level. - * @par Implemented as - * - @ref R_IOPORT_PinEventInputRead() - * @param[in] pin Pin to be read. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. * @param[in] p_pin_event Pointer to return the event data. */ fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); /** Write pin event data. - * @par Implemented as - * - @ref R_IOPORT_PinEventOutputWrite() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] pin Pin event data is to be written to. * @param[in] pin_value Level to be written to pin output event. */ fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); /** Read level of a pin. - * @par Implemented as - * - @ref R_IOPORT_PinRead() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] pin Pin to be read. * @param[in] p_pin_value Pointer to return the pin level. */ fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); /** Write specified level to a pin. - * @par Implemented as - * - @ref R_IOPORT_PinWrite() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] pin Pin to be written to. * @param[in] level State to be written to the pin. */ fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); /** Set the direction of one or more pins on a port. - * @par Implemented as - * - @ref R_IOPORT_PortDirectionSet() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] port Port being configured. - * @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input). + * @param[in] direction_values Value controlling direction of pins on port. * @param[in] mask Mask controlling which pins on the port are to be configured. */ fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, ioport_size_t mask); /** Read captured event data for a port. - * @par Implemented as - * - @ref R_IOPORT_PortEventInputRead() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] port Port to be read. * @param[in] p_event_data Pointer to return the event data. */ fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); /** Write event output data for a port. - * @par Implemented as - * - @ref R_IOPORT_PortEventOutputWrite() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] port Port event data will be written to. * @param[in] event_data Data to be written as event data to specified port. * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. @@ -349,16 +171,16 @@ typedef struct st_ioport_api ioport_size_t mask_value); /** Read states of pins on the specified port. - * @par Implemented as - * - @ref R_IOPORT_PortRead() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] port Port to be read. * @param[in] p_port_value Pointer to return the port value. */ fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); /** Write to multiple pins on a port. - * @par Implemented as - * - @ref R_IOPORT_PortWrite() + * + * @param[in] p_ctrl Pointer to control structure. * @param[in] port Port to be written to. * @param[in] value Value to be written to the port. * @param[in] mask Mask controlling which pins on the port are written to. diff --git a/ra/fsp/inc/api/r_jpeg_api.h b/ra/fsp/inc/api/r_jpeg_api.h index 20eb98449..460f6cd9e 100644 --- a/ra/fsp/inc/api/r_jpeg_api.h +++ b/ra/fsp/inc/api/r_jpeg_api.h @@ -180,8 +180,6 @@ typedef struct st_jpeg_cfg } jpeg_cfg_t; /** JPEG decode control block. Allocate an instance specific control block to pass into the JPEG decode API calls. - * @par Implemented as - * - jpeg_instance_ctrl_t */ typedef void jpeg_ctrl_t; @@ -189,8 +187,6 @@ typedef void jpeg_ctrl_t; typedef struct st_jpeg_api { /** Initial configuration - * @par Implemented as - * - @ref R_JPEG_Open() * * @pre none * @@ -200,8 +196,6 @@ typedef struct st_jpeg_api fsp_err_t (* open)(jpeg_ctrl_t * const p_ctrl, jpeg_cfg_t const * const p_cfg); /** Assign input data buffer to JPEG codec. - * @par Implemented as - * - @ref R_JPEG_InputBufferSet() * * @pre the JPEG codec module must have been opened properly. * @note The buffer starting address must be 8-byte aligned. @@ -212,8 +206,6 @@ typedef struct st_jpeg_api fsp_err_t (* inputBufferSet)(jpeg_ctrl_t * const p_ctrl, void * p_buffer, uint32_t buffer_size); /** Assign output buffer to JPEG codec for storing output data. - * @par Implemented as - * - @ref R_JPEG_OutputBufferSet() * * @pre The JPEG codec module must have been opened properly. * @note The buffer starting address must be 8-byte aligned. @@ -228,8 +220,6 @@ typedef struct st_jpeg_api fsp_err_t (* outputBufferSet)(jpeg_ctrl_t * const p_ctrl, void * p_buffer, uint32_t buffer_size); /** Retrieve current status of the JPEG codec module. - * @par Implemented as - * - @ref R_JPEG_StatusGet() * * @pre the JPEG codec module must have been opened properly. * @param[in] p_ctrl Control block set in jpeg_api_t::open call. @@ -238,8 +228,6 @@ typedef struct st_jpeg_api fsp_err_t (* statusGet)(jpeg_ctrl_t * const p_ctrl, jpeg_status_t * const p_status); /** Cancel an outstanding operation. - * @par Implemented as - * - @ref R_JPEG_Close() * * @pre the JPEG codec module must have been opened properly. * @note If the encoding or the decoding operation is finished without errors, the HLD driver @@ -252,19 +240,15 @@ typedef struct st_jpeg_api #if JPEG_CFG_DECODE_ENABLE /** Configure the horizontal stride value. - * @par Implemented as - * - @ref R_JPEG_DecodeHorizontalStrideSet() * * @pre The JPEG codec module must have been opened properly. - * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. * @param[in] horizontal_stride Horizontal stride value to be used for the decoded image data. - * @param[in] buffer_size Size of the output buffer + * @param[in] buffer_size Size of the output buffer */ fsp_err_t (* horizontalStrideSet)(jpeg_ctrl_t * const p_ctrl, uint32_t horizontal_stride); /** Get the input pixel format. - * @par Implemented as - * - @ref R_JPEG_DecodePixelFormatGet() * * @pre the JPEG codec module must have been opened properly. * @param[in] p_ctrl Control block set in jpeg_api_t::open call. @@ -273,11 +257,9 @@ typedef struct st_jpeg_api fsp_err_t (* pixelFormatGet)(jpeg_ctrl_t * const p_ctrl, jpeg_color_space_t * const p_color_space); /** Configure the horizontal and vertical subsample settings. - * @par Implemented as - * - @ref R_JPEG_DecodeImageSubsampleSet() * * @pre The JPEG codec module must have been opened properly. - * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. * @param[in] horizontal_subsample Horizontal subsample value * @param[in] vertical_subsample Vertical subsample value */ @@ -285,8 +267,6 @@ typedef struct st_jpeg_api jpeg_decode_subsample_t vertical_subsample); /** Return the number of lines decoded into the output buffer. - * @par Implemented as - * - @ref R_JPEG_DecodeLinesDecodedGet() * * @pre the JPEG codec module must have been opened properly. * @param[in] p_ctrl Control block set in jpeg_api_t::open call. @@ -295,8 +275,6 @@ typedef struct st_jpeg_api fsp_err_t (* linesDecodedGet)(jpeg_ctrl_t * const p_ctrl, uint32_t * const p_lines); /** Retrieve image size during decoding operation. - * @par Implemented as - * - @ref R_JPEG_DecodeImageSizeGet() * * @pre the JPEG codec module must have been opened properly. * @note If the encoding or the decoding operation is finished without errors, the HLD driver @@ -312,8 +290,6 @@ typedef struct st_jpeg_api #if JPEG_CFG_ENCODE_ENABLE /** Set image parameters to JPEG Codec - * @par Implemented as - * - @ref R_JPEG_EncodeImageSizeSet() * * @pre The JPEG codec module must have been opened properly. * @@ -325,8 +301,6 @@ typedef struct st_jpeg_api #if JPEG_CFG_DECODE_ENABLE /** Switch between encode and decode mode or vice-versa. - * @par Implemented as - * - @ref R_JPEG_ModeSet() * * @pre The JPEG codec module must have been opened properly. * The JPEG Codec can only perform one operation at a time and requires different configuration for encode and diff --git a/ra/fsp/inc/api/r_keymatrix_api.h b/ra/fsp/inc/api/r_keymatrix_api.h index a0ba4bec0..724aaed20 100644 --- a/ra/fsp/inc/api/r_keymatrix_api.h +++ b/ra/fsp/inc/api/r_keymatrix_api.h @@ -29,8 +29,6 @@ * that instant via a bit mask. This allows the interface to be used with a matrix configuration or a one-to-one * hardware implementation that is triggered on either a rising or a falling edge. * - * Implemented by: - * - @ref KINT * @{ **********************************************************************************************************************/ @@ -56,8 +54,6 @@ FSP_HEADER *********************************************************************************************************************/ /** Key matrix control block. Allocate an instance specific control block to pass into the key matrix API calls. - * @par Implemented as - * - kint_instance_ctrl_t */ typedef void keymatrix_ctrl_t; @@ -94,8 +90,6 @@ typedef struct st_keymatrix_cfg typedef struct st_keymatrix_api { /** Initial configuration. - * @par Implemented as - * - @ref R_KINT_Open() * * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set in this function. * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. @@ -103,24 +97,18 @@ typedef struct st_keymatrix_api fsp_err_t (* open)(keymatrix_ctrl_t * const p_ctrl, keymatrix_cfg_t const * const p_cfg); /** Enable Key interrupt - * @par Implemented as - * - @ref R_KINT_Enable() * * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. */ fsp_err_t (* enable)(keymatrix_ctrl_t * const p_ctrl); /** Disable Key interrupt. - * @par Implemented as - * - @ref R_KINT_Disable() * * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. */ fsp_err_t (* disable)(keymatrix_ctrl_t * const p_ctrl); /** Allow driver to be reconfigured. May reduce power consumption. - * @par Implemented as - * - @ref R_KINT_Close() * * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. */ diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h index 0996d2793..c38260392 100644 --- a/ra/fsp/inc/api/r_lpm_api.h +++ b/ra/fsp/inc/api/r_lpm_api.h @@ -32,8 +32,6 @@ * * @note Not all low power modes are available on all MCUs. * - * The LPM interface is implemented by: - * - @ref LPM * * @{ **********************************************************************************************************************/ @@ -68,6 +66,8 @@ typedef enum e_lpm_mode LPM_MODE_DEEP, ///< Deep Software Standby mode } lpm_mode_t; +#ifndef BSP_OVERRIDE_LPM_SNOOZE_REQUEST_T + /** Snooze request sources */ typedef enum e_lpm_snooze_request { @@ -103,6 +103,9 @@ typedef enum e_lpm_snooze_request LPM_SNOOZE_REQUEST_AGT3_COMPARE_A = 0x200000000ULL, ///< Enable AGT3 compare match A snooze request LPM_SNOOZE_REQUEST_AGT3_COMPARE_B = 0x400000000ULL, ///< Enable AGT3 compare match B snooze request } lpm_snooze_request_t; +#endif + +#ifndef BSP_OVERRIDE_LPM_SNOOZE_END_T /** Snooze end control */ typedef enum e_lpm_snooze_end @@ -121,31 +124,35 @@ typedef enum e_lpm_snooze_end } lpm_snooze_end_t; typedef uint16_t lpm_snooze_end_bits_t; +#endif + +#ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T /** Snooze cancel control */ typedef enum e_lpm_snooze_cancel { - LPM_SNOOZE_CANCEL_SOURCE_NONE = ELC_EVENT_NONE, ///< No snooze cancel source - LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPM = ELC_EVENT_ADC0_COMPARE_MATCH, ///< ADC Channel 0 window compare match -#if (2U != BSP_FEATURE_ELC_VERSION) - LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPUM = ELC_EVENT_ADC0_COMPARE_MISMATCH, ///< ADC Channel 0 window compare mismatch -#endif -#if BSP_FEATURE_ADC_VALID_UNIT_MASK & (1U << 1) // If ADC has unit 1 - LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPM = ELC_EVENT_ADC1_COMPARE_MATCH, ///< ADC Channel 1 window compare match + LPM_SNOOZE_CANCEL_SOURCE_NONE = ELC_EVENT_NONE, ///< No snooze cancel source + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPM = ELC_EVENT_ADC0_COMPARE_MATCH, ///< ADC Channel 0 window compare match #if (2U != BSP_FEATURE_ELC_VERSION) - LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH, ///< ADC Channel 1 window compare mismatch + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPUM = ELC_EVENT_ADC0_COMPARE_MISMATCH, ///< ADC Channel 0 window compare mismatch + #endif + #if BSP_FEATURE_ADC_VALID_UNIT_MASK & (1U << 1) // If ADC has unit 1 + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPM = ELC_EVENT_ADC1_COMPARE_MATCH, ///< ADC Channel 1 window compare match + #if (2U != BSP_FEATURE_ELC_VERSION) + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH, ///< ADC Channel 1 window compare mismatch + #endif + #endif + #if (BSP_FEATURE_SCI_CHANNELS & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0 + LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM = ELC_EVENT_SCI0_AM, ///< SCI0 address match event + LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI, ///< SCI0 receive error + #endif + LPM_SNOOZE_CANCEL_SOURCE_DTC_COMPLETE = ELC_EVENT_DTC_COMPLETE, ///< DTC transfer completion + LPM_SNOOZE_CANCEL_SOURCE_DOC_DOPCI = ELC_EVENT_DOC_INT, ///< Data operation circuit interrupt + #if BSP_FEATURE_CTSU_VERSION + LPM_SNOOZE_CANCEL_SOURCE_CTSU_CTSUFN = ELC_EVENT_CTSU_END, ///< CTSU measurement end interrupt #endif -#endif -#if (BSP_FEATURE_SCI_CHANNELS & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0 - LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM = ELC_EVENT_SCI0_AM, ///< SCI0 address match event - LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI, ///< SCI0 receive error -#endif - LPM_SNOOZE_CANCEL_SOURCE_DTC_COMPLETE = ELC_EVENT_DTC_COMPLETE, ///< DTC transfer completion - LPM_SNOOZE_CANCEL_SOURCE_DOC_DOPCI = ELC_EVENT_DOC_INT, ///< Data operation circuit interrupt -#if BSP_FEATURE_CTSU_VERSION - LPM_SNOOZE_CANCEL_SOURCE_CTSU_CTSUFN = ELC_EVENT_CTSU_END, ///< CTSU measurement end interrupt -#endif } lpm_snooze_cancel_t; +#endif /** DTC Enable in Snooze Mode */ typedef enum e_lpm_snooze_dtc @@ -154,6 +161,8 @@ typedef enum e_lpm_snooze_dtc LPM_SNOOZE_DTC_ENABLE = 1U, ///< Enable DTC operation } lpm_snooze_dtc_t; +#ifndef BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T + /** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ typedef enum e_lpm_standby_wake_source { @@ -218,6 +227,7 @@ typedef enum e_lpm_standby_wake_source } lpm_standby_wake_source_t; typedef uint64_t lpm_standby_wake_source_bits_t; +#endif /** I/O port state after Deep Software Standby mode */ typedef enum e_lpm_io_port @@ -324,6 +334,8 @@ typedef enum e_lpm_deep_standby_cancel_edge typedef uint32_t lpm_deep_standby_cancel_edge_bits_t; +#ifndef BSP_OVERRIDE_LPM_DEEP_STANDBY_WAKE_SOURCE_T + /** Deep Standby cancel sources */ typedef enum e_lpm_deep_standby_cancel_source { @@ -362,6 +374,7 @@ typedef enum e_lpm_deep_standby_cancel_source LPM_DEEP_STANDBY_CANCEL_SOURCE_IWDT = 0x20000000U, ///< IWDT Underflow LPM_DEEP_STANDBY_CANCEL_SOURCE_VBATT = 0x80000000U, ///< VBATT Tamper Detection } lpm_deep_standby_cancel_source_t; +#endif typedef uint32_t lpm_deep_standby_cancel_source_bits_t; @@ -441,8 +454,13 @@ typedef struct st_lpm_cfg /** Bitwise list of snooze end sources */ lpm_snooze_end_bits_t snooze_end_sources; + #ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T + /** List of snooze cancel sources */ lpm_snooze_cancel_t snooze_cancel_sources; + #else + lpm_snooze_cancel_source_bits_t snooze_cancel_sources; + #endif #endif /** State of DTC in snooze mode, enabled or disabled */ @@ -484,8 +502,6 @@ typedef struct st_lpm_cfg } lpm_cfg_t; /** LPM control block. Allocate an instance specific control block to pass into the LPM API calls. - * @par Implemented as - * - lpm_instance_ctrl_t */ typedef void lpm_ctrl_t; @@ -493,38 +509,28 @@ typedef void lpm_ctrl_t; typedef struct st_lpm_api { /** Initialization function - * @par Implemented as - * - @ref R_LPM_Open() - **/ + **/ - fsp_err_t (* open)(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); + fsp_err_t (* open)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); /** Initialization function - * @par Implemented as - * - @ref R_LPM_Close() - **/ - fsp_err_t (* close)(lpm_ctrl_t * const p_api_ctrl); + **/ + fsp_err_t (* close)(lpm_ctrl_t * const p_ctrl); /** Configure a low power mode. - * @par Implemented as - * - @ref R_LPM_LowPowerReconfigure() * * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. **/ - fsp_err_t (* lowPowerReconfigure)(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); + fsp_err_t (* lowPowerReconfigure)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); /** Enter low power mode (sleep/standby/deep standby) using WFI macro. * Function will return after waking from low power mode. - * @par Implemented as - * - @ref R_LPM_LowPowerModeEnter() **/ - fsp_err_t (* lowPowerModeEnter)(lpm_ctrl_t * const p_api_ctrl); + fsp_err_t (* lowPowerModeEnter)(lpm_ctrl_t * const p_ctrl); /** Clear the IOKEEP bit after deep software standby. - * * @par Implemented as - * - @ref R_LPM_IoKeepClear() - **/ - fsp_err_t (* ioKeepClear)(lpm_ctrl_t * const p_api_ctrl); + **/ + fsp_err_t (* ioKeepClear)(lpm_ctrl_t * const p_ctrl); } lpm_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/api/r_lvd_api.h b/ra/fsp/inc/api/r_lvd_api.h index 0031ba2fc..d4dc8680c 100644 --- a/ra/fsp/inc/api/r_lvd_api.h +++ b/ra/fsp/inc/api/r_lvd_api.h @@ -26,8 +26,6 @@ * @section LVD_API_SUMMARY Summary * The LVD driver provides functions for configuring the LVD voltage monitors and detectors. * - * Implemented by: - * - @ref LVD * * @{ **********************************************************************************************************************/ @@ -104,11 +102,12 @@ typedef enum e_lvd_response { LVD_RESPONSE_NMI, ///< Non-maskable interrupt LVD_RESPONSE_INTERRUPT, ///< Maskable interrupt - LVD_RESPONSE_RESET, ///< Reset + LVD_RESPONSE_RESET, ///< Reset on VCC-fall + LVD_RESPONSE_RESET_ON_RISING, ///< Reset on VCC-rise LVD_RESPONSE_NONE, ///< No response, status must be requested via statusGet function } lvd_response_t; -/** The direction from which Vcc must cross the threshold to trigger a detection (rising, falling, or both). */ +/** The direction from which VCC must cross the threshold to trigger a detection (rising, falling, or both). */ typedef enum e_lvd_voltage_slope { LVD_VOLTAGE_SLOPE_RISING = 0, ///< When VCC >= Vdet2 (rise) is detected @@ -220,8 +219,6 @@ typedef struct st_lvd_cfg } lvd_cfg_t; /** LVD control block. Allocate an instance specific control block to pass into the LVD API calls. - * @par Implemented as - * - lvd_instance_ctrl_t */ typedef void lvd_ctrl_t; @@ -231,8 +228,6 @@ typedef void lvd_ctrl_t; typedef struct st_lvd_api { /** Initializes a low voltage detection driver according to the passed-in configuration structure. - * @par Implemented as - * - @ref R_LVD_Open() * @param[in] p_ctrl Pointer to control structure for the driver instance * @param[in] p_cfg Pointer to the configuration structure for the driver instance **/ @@ -240,8 +235,6 @@ typedef struct st_lvd_api /** Get the current state of the monitor, (threshold crossing detected, voltage currently above or below threshold). * Must be used if the peripheral was initialized with lvd_response_t set to LVD_RESPONSE_NONE. - * @par Implemented as - * - @ref R_LVD_StatusGet() * @param[in] p_ctrl Pointer to the control structure for the driver instance * @param[in,out] p_lvd_status Pointer to a lvd_status_t structure **/ @@ -249,16 +242,12 @@ typedef struct st_lvd_api /** Clears the latched status of the monitor. * Must be used if the peripheral was initialized with lvd_response_t set to LVD_RESPONSE_NONE. - * @par Implemented as - * - @ref R_LVD_StatusClear() * @param[in] p_ctrl Pointer to the control structure for the driver instance **/ fsp_err_t (* statusClear)(lvd_ctrl_t * const p_ctrl); /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_LVD_CallbackSet() * * @param[in] p_ctrl Pointer to the LVD control block. * @param[in] p_callback Callback function @@ -266,13 +255,11 @@ typedef struct st_lvd_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(lvd_ctrl_t * const p_api_ctrl, void (* p_callback)(lvd_callback_args_t *), + fsp_err_t (* callbackSet)(lvd_ctrl_t * const p_ctrl, void (* p_callback)(lvd_callback_args_t *), void const * const p_context, lvd_callback_args_t * const p_callback_memory); /** Disables the LVD peripheral. * Closes the driver instance. - * @par Implemented as - * - @ref R_LVD_Close() * @param[in] p_ctrl Pointer to the control structure for the driver instance **/ fsp_err_t (* close)(lvd_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/api/r_opamp_api.h b/ra/fsp/inc/api/r_opamp_api.h index 371a7d151..dcb2727f1 100644 --- a/ra/fsp/inc/api/r_opamp_api.h +++ b/ra/fsp/inc/api/r_opamp_api.h @@ -30,8 +30,6 @@ * The OPAMP interface provides standard operational amplifier functionality, including starting and stopping the * amplifier. * - * Implemented by: - * @ref OPAMP * * @{ **********************************************************************************************************************/ @@ -101,8 +99,6 @@ typedef void opamp_ctrl_t; typedef struct st_opamp_api { /** Initialize the operational amplifier. - * @par Implemented as - * - @ref R_OPAMP_Open() * * @param[in] p_ctrl Pointer to instance control block * @param[in] p_cfg Pointer to configuration @@ -110,8 +106,6 @@ typedef struct st_opamp_api fsp_err_t (* open)(opamp_ctrl_t * const p_ctrl, opamp_cfg_t const * const p_cfg); /** Start the op-amp(s). - * @par Implemented as - * - @ref R_OPAMP_Start() * * @param[in] p_ctrl Pointer to instance control block * @param[in] channel_mask Bitmask of channels to start @@ -119,8 +113,6 @@ typedef struct st_opamp_api fsp_err_t (* start)(opamp_ctrl_t * const p_ctrl, uint32_t const channel_mask); /** Stop the op-amp(s). - * @par Implemented as - * - @ref R_OPAMP_Stop() * * @param[in] p_ctrl Pointer to instance control block * @param[in] channel_mask Bitmask of channels to stop @@ -128,8 +120,6 @@ typedef struct st_opamp_api fsp_err_t (* stop)(opamp_ctrl_t * const p_ctrl, uint32_t const channel_mask); /** Trim the op-amp(s). Not supported on all MCUs. See implementation for procedure details. - * @par Implemented as - * - @ref R_OPAMP_Trim() * * @param[in] p_ctrl Pointer to instance control block * @param[in] cmd Trim command @@ -138,8 +128,6 @@ typedef struct st_opamp_api fsp_err_t (* trim)(opamp_ctrl_t * const p_ctrl, opamp_trim_cmd_t const cmd, opamp_trim_args_t const * const p_args); /** Provide information such as the recommended minimum stabilization wait time. - * @par Implemented as - * - @ref R_OPAMP_InfoGet() * * @param[in] p_ctrl Pointer to instance control block * @param[out] p_info OPAMP information stored here @@ -147,8 +135,6 @@ typedef struct st_opamp_api fsp_err_t (* infoGet)(opamp_ctrl_t * const p_ctrl, opamp_info_t * const p_info); /** Provide status of each op-amp channel. - * @par Implemented as - * - @ref R_OPAMP_StatusGet() * * @param[in] p_ctrl Pointer to instance control block * @param[out] p_status Status stored here @@ -157,8 +143,6 @@ typedef struct st_opamp_api /** Close the specified OPAMP unit by ending any scan in progress, disabling interrupts, and removing power to the * specified A/D unit. - * @par Implemented as - * - @ref R_OPAMP_Close() * * @param[in] p_ctrl Pointer to instance control block */ diff --git a/ra/fsp/inc/api/r_pdc_api.h b/ra/fsp/inc/api/r_pdc_api.h deleted file mode 100644 index 5fbae9b01..000000000 --- a/ra/fsp/inc/api/r_pdc_api.h +++ /dev/null @@ -1,191 +0,0 @@ -/*********************************************************************************************************************** - * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - * - * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products - * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are - * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use - * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property - * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas - * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION - * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT - * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR - * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM - * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION - * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, - * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, - * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY - * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_INTERFACES - * @defgroup PDC_API PDC Interface - * @brief Interface for PDC functions. - * - * @section PDC_API_SUMMARY Summary - * - * DEPRECATED - PDC API will be replaced with CAPTURE API in the next major release - * - * The PDC interface provides the functionality for capturing an image from an image sensor/camera. - * When a capture is complete a transfer complete interrupt is triggered. - * - * Implemented by: - * - @ref PDC - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_PDC_API_H -#define R_PDC_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Register definitions, common services and error codes. */ -#include "bsp_api.h" -#include "r_transfer_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** Clock divider applied to PDC clock to provide PCKO output frequency */ -typedef enum e_pdc_clock_division -{ - PDC_CLOCK_DIVISION_2 = 0U, ///< CLK / 2 - PDC_CLOCK_DIVISION_4 = 1U, ///< CLK / 4 - PDC_CLOCK_DIVISION_6 = 2U, ///< CLK / 6 - PDC_CLOCK_DIVISION_8 = 3U, ///< CLK / 8 - PDC_CLOCK_DIVISION_10 = 4U, ///< CLK / 10 - PDC_CLOCK_DIVISION_12 = 5U, ///< CLK / 12 - PDC_CLOCK_DIVISION_14 = 6U, ///< CLK / 14 - PDC_CLOCK_DIVISION_16 = 7U, ///< CLK / 16 -} pdc_clock_division_t; - -/** Endian of captured data */ -typedef enum e_pdc_endian -{ - PDC_ENDIAN_LITTLE = 0U, ///< Data is in little endian format - PDC_ENDIAN_BIG = 1U, ///< Data is in big endian format -} pdc_endian_t; - -/** Polarity of input HSYNC signal */ -typedef enum e_pdc_hsync_polarity -{ - PDC_HSYNC_POLARITY_HIGH = 0U, ///< HSYNC signal is active high - PDC_HSYNC_POLARITY_LOW = 1U, ///< HSYNC signal is active low -} pdc_hsync_polarity_t; - -/** Polarity of input VSYNC signal */ -typedef enum e_pdc_vsync_polarity -{ - PDC_VSYNC_POLARITY_HIGH = 0U, ///< VSYNC signal is active high - PDC_VSYNC_POLARITY_LOW = 1U, ///< VSYNC signal is active low -} pdc_vsync_polarity_t; - -/** PDC events */ -typedef enum e_pdc_event -{ - PDC_EVENT_TRANSFER_COMPLETE = 0U, ///< Complete frame transferred by DMAC/DTC - PDC_EVENT_RX_DATA_READY = 0x01U, ///< Receive data ready interrupt - PDC_EVENT_FRAME_END = 0x04U, ///< Frame end interrupt - PDC_EVENT_ERR_OVERRUN = 0x08U, ///< Overrun interrupt - PDC_EVENT_ERR_UNDERRUN = 0x10U, ///< Underrun interrupt - PDC_EVENT_ERR_V_SET = 0x20U, ///< Vertical line setting error interrupt - PDC_EVENT_ERR_H_SET = 0x40U, ///< Horizontal byte number setting error interrupt -} pdc_event_t; - -/** Callback function parameter data */ -typedef struct st_pdc_callback_args -{ - pdc_event_t event; ///< Event causing the callback - uint8_t * p_buffer; ///< Pointer to buffer containing the captured data - void const * p_context; ///< Placeholder for user data. Set in @ref pdc_api_t::open function in @ref pdc_cfg_t. -} pdc_callback_args_t; - -/** PDC configuration parameters. */ -typedef struct st_pdc_cfg -{ - uint16_t x_capture_start_pixel; ///< Horizontal position to start capture - uint16_t x_capture_pixels; ///< Number of horizontal pixels to capture - uint16_t y_capture_start_pixel; ///< Vertical position to start capture - uint16_t y_capture_pixels; ///< Number of vertical lines/pixels to capture - pdc_clock_division_t clock_division; ///< Clock divider - pdc_endian_t endian; ///< Endian of capture data - pdc_hsync_polarity_t hsync_polarity; ///< Polarity of HSYNC input - pdc_vsync_polarity_t vsync_polarity; ///< Polarity of VSYNC input - uint8_t * p_buffer; ///< Pointer to buffer to write image into - uint8_t bytes_per_pixel; ///< Number of bytes per pixel - uint8_t pdc_ipl; ///< PDC interrupt priority - uint8_t transfer_req_ipl; ///< Transfer interrupt priority - IRQn_Type pdc_irq; ///< PDC IRQ number - IRQn_Type transfer_req_irq; ///< Transfer request IRQ number - transfer_instance_t const * p_lower_lvl_transfer; ///< Pointer to the transfer instance the PDC should use - void (* p_callback)(pdc_callback_args_t * p_args); ///< Callback provided when a PDC transfer ISR occurs. - void const * p_context; ///< User defined context passed to callback function - void const * p_extend; ///< Placeholder for user data. -} pdc_cfg_t; - -/** PDC control block. Allocate an instance specific control block to pass into the PDC API calls. - * @par Implemented as - * - pdc_instance_ctrl_t - */ -typedef void pdc_ctrl_t; - -/** PDC functions implemented at the HAL layer will follow this API. - * DEPRECATED - PDC API will be replaced with CAPTURE API in the next major release */ -typedef struct st_pdc_api -{ - /** Initial configuration. - * @par Implemented as - * - @ref R_PDC_Open() - * - * @note To reconfigure after calling this function, call @ref pdc_api_t::close first. - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_cfg Pointer to pin configuration structure. - */ - fsp_err_t (* open)(pdc_ctrl_t * const p_ctrl, pdc_cfg_t const * const p_cfg); - - /** Closes the driver and allows reconfiguration. May reduce power consumption. - * @par Implemented as - * - @ref R_PDC_Close() - * - * @param[in] p_ctrl Pointer to control structure. - */ - fsp_err_t (* close)(pdc_ctrl_t * const p_ctrl); - - /** Start a capture. - * @par Implemented as - * - @ref R_PDC_CaptureStart() - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] p_buffer Pointer to store captured image data. - */ - fsp_err_t (* captureStart)(pdc_ctrl_t * const p_ctrl, uint8_t * const p_buffer); -} pdc_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_pdc_instance -{ - pdc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - pdc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - pdc_api_t const * p_api; ///< Pointer to the API structure for this instance -} pdc_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif - -/*******************************************************************************************************************//** - * @} (end addtogroup PDC_API) - **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_poeg_api.h b/ra/fsp/inc/api/r_poeg_api.h index 13e0f12e9..0aa4c28f1 100644 --- a/ra/fsp/inc/api/r_poeg_api.h +++ b/ra/fsp/inc/api/r_poeg_api.h @@ -29,8 +29,6 @@ * @section POEG_API_SUMMARY Summary * @brief The POEG disables GPT output pins based on configurable events. * - * Implemented by: - * @ref POEG * * @{ **********************************************************************************************************************/ @@ -98,11 +96,11 @@ typedef enum e_poeg_gtetrg_polarity */ typedef enum e_poeg_gtetrg_noise_filter { - POEG_GTETRG_NOISE_FILTER_DISABLED = 0U, ///< No noise filter applied to GTETRG input - POEG_GTETRG_NOISE_FILTER_PCLKB_DIV_1 = 1U, ///< Apply noise filter with sample clock PCLKB - POEG_GTETRG_NOISE_FILTER_PCLKB_DIV_8 = 3U, ///< Apply noise filter with sample clock PCLKB/8 - POEG_GTETRG_NOISE_FILTER_PCLKB_DIV_32 = 5U, ///< Apply noise filter with sample clock PCLKB/32 - POEG_GTETRG_NOISE_FILTER_PCLKB_DIV_128 = 7U, ///< Apply noise filter with sample clock PCLKB/128 + POEG_GTETRG_NOISE_FILTER_DISABLED = 0U, ///< No noise filter applied to GTETRG input + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_1 = 1U, ///< Apply noise filter with sample clock equal to Clock source/1 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_8 = 3U, ///< Apply noise filter with sample clock equal to Clock source/8 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_32 = 5U, ///< Apply noise filter with sample clock equal to Clock source/32 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_128 = 7U, ///< Apply noise filter with sample clock equal to Clock source/128 } poeg_gtetrg_noise_filter_t; /** POEG status */ @@ -117,9 +115,7 @@ typedef struct st_poeg_callback_args void const * p_context; ///< Placeholder for user data, set in @ref poeg_cfg_t. } poeg_callback_args_t; -/** DOC control block. Allocate an instance specific control block to pass into the DOC API calls. - * @par Implemented as - * - @ref poeg_instance_ctrl_t +/** POEG control block. Allocate an instance specific control block to pass into the POEG API calls. */ typedef void poeg_ctrl_t; @@ -136,7 +132,7 @@ typedef struct st_poeg_cfg /** Placeholder for user data. Passed to the user callback in @ref poeg_callback_args_t. */ void const * p_context; uint32_t channel; ///< Channel 0 corresponds to GTETRGA, 1 to GTETRGB, etc. - IRQn_Type irq; ///< NVIC interrupt number assigned to this instance + IRQn_Type irq; ///< Interrupt number assigned to this instance uint8_t ipl; ///< POEG interrupt priority } poeg_cfg_t; @@ -144,8 +140,6 @@ typedef struct st_poeg_cfg typedef struct st_poeg_api { /** Initial configuration. - * @par Implemented as - * - @ref R_POEG_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -153,8 +147,6 @@ typedef struct st_poeg_api fsp_err_t (* open)(poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cfg); /** Gets the current driver state. - * @par Implemented as - * - @ref R_POEG_StatusGet() * * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. * @param[out] p_status Provides the current state of the POEG. @@ -162,8 +154,6 @@ typedef struct st_poeg_api fsp_err_t (* statusGet)(poeg_ctrl_t * const p_ctrl, poeg_status_t * p_status); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_POEG_CallbackSet() * * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call for this timer. * @param[in] p_callback Callback function to register @@ -171,12 +161,10 @@ typedef struct st_poeg_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(poeg_ctrl_t * const p_api_ctrl, void (* p_callback)(poeg_callback_args_t *), + fsp_err_t (* callbackSet)(poeg_ctrl_t * const p_ctrl, void (* p_callback)(poeg_callback_args_t *), void const * const p_context, poeg_callback_args_t * const p_callback_memory); /** Disables GPT output pins by software request. - * @par Implemented as - * - @ref R_POEG_OutputDisable() * * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. */ @@ -184,16 +172,12 @@ typedef struct st_poeg_api /** Attempts to clear status flags to reenable GPT output pins. Confirm all status flags are cleared after calling * this function by calling poeg_api_t::statusGet(). - * @par Implemented as - * - @ref R_POEG_Reset() * * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. */ fsp_err_t (* reset)(poeg_ctrl_t * const p_ctrl); /** Disables POEG interrupt. - * @par Implemented as - * - @ref R_POEG_Close() * * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. */ @@ -214,5 +198,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup POEG_API) + * @} (end defgroup POEG_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_ptp_api.h b/ra/fsp/inc/api/r_ptp_api.h index 53d67041a..b0c903517 100644 --- a/ra/fsp/inc/api/r_ptp_api.h +++ b/ra/fsp/inc/api/r_ptp_api.h @@ -26,8 +26,6 @@ * @section PTP_API_SUMMARY Summary * The PTP interface provides the functionality for using PTP. * - * Implemented by: - * - @ref PTP * * @{ **********************************************************************************************************************/ @@ -565,8 +563,6 @@ typedef void ptp_ctrl_t; typedef struct st_ptp_api { /** Initial configuration. - * @par Implemented as - * - @ref R_PTP_Open() * * @note To reconfigure after calling this function, call @ref ptp_api_t::close first. * @param[in] p_ctrl Pointer to control structure. @@ -575,8 +571,6 @@ typedef struct st_ptp_api fsp_err_t (* open)(ptp_ctrl_t * const p_ctrl, ptp_cfg_t const * const p_cfg); /** Set the MAC address for the PTP. - * @par Implemented as - * - @ref R_PTP_MacAddrSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_hw_addr Pointer to the 6 byte MAC address. @@ -584,8 +578,6 @@ typedef struct st_ptp_api fsp_err_t (* macAddrSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_mac_addr); /** Set the IP address for the PTP. - * @par Implemented as - * - @ref R_PTP_IpAddrSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] ip_addr 32 bit IPv4 address of the PTP. @@ -593,8 +585,6 @@ typedef struct st_ptp_api fsp_err_t (* ipAddrSet)(ptp_ctrl_t * const p_ctrl, uint32_t ip_addr); /** Set the local clock ID (Usually based off of the PTP MAC address). - * @par Implemented as - * - @ref R_PTP_LocalClockIdSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_clock_id Pointer to 8 byte clock ID. @@ -602,8 +592,6 @@ typedef struct st_ptp_api fsp_err_t (* localClockIdSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id); /** Set the master clock ID (Usually obtained from previously received announce message). - * @par Implemented as - * - @ref R_PTP_MasterClockIdSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_clock_id Pointer to 8 byte clock ID. @@ -612,8 +600,6 @@ typedef struct st_ptp_api fsp_err_t (* masterClockIdSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id, uint16_t port_id); /** Set the flags field for the given message type. - * @par Implemented as - * - @ref R_PTP_MessageFlagsSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] message_type The message type. @@ -623,8 +609,6 @@ typedef struct st_ptp_api ptp_message_flags_t flags); /** Sets the offsetFromMaster field in announce messages. - * @par Implemented as - * - @ref R_PTP_CurrentUtcOffsetSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] offset New currentUtcOffset value. @@ -633,8 +617,6 @@ typedef struct st_ptp_api /** Transition to a new clock state. * - * @par Implemented as - * - @ref R_PTP_PortStateSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] state The state to transition into. @@ -644,8 +626,6 @@ typedef struct st_ptp_api /** Send a PTP message. Appropriate fields in the PTP message will be endian swapped. * The application must ensure that the TLV data is in big endian format. * - * @par Implemented as - * - @ref R_PTP_MessageSend() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_message Pointer to a PTP message. @@ -657,8 +637,6 @@ typedef struct st_ptp_api /** Set the local clock value. * - * @par Implemented as - * - @ref R_PTP_LocalClockValueSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_time Pointer to the new time setting. @@ -667,8 +645,6 @@ typedef struct st_ptp_api /** Get the local clock value. * - * @par Implemented as - * - @ref R_PTP_LocalClockValueGet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_time Pointer to store the current time setting. @@ -677,8 +653,6 @@ typedef struct st_ptp_api /** Configuration that is common to all of the pulse timers. * - * @par Implemented as - * - @ref R_PTP_PulseTimerCommonConfig() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_timer_cfg Pointer to the pulse timer common configuration. @@ -687,8 +661,6 @@ typedef struct st_ptp_api /** Setup a pulse timer. * - * @par Implemented as - * - @ref R_PTP_PulseTimerEnable() * * @param[in] p_ctrl Pointer to control structure. * @param[in] channel The pulse timer channel to setup. @@ -699,8 +671,6 @@ typedef struct st_ptp_api /** Stop a pulse timer. * - * @par Implemented as - * - @ref R_PTP_PulseTimerDisable() * * @param[in] p_ctrl Pointer to control structure. * @param[in] channel The pulse timer channel to stop. @@ -709,8 +679,6 @@ typedef struct st_ptp_api /** Stop PTP operation. * - * @par Implemented as - * - @ref R_PTP_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/r_rsip_key_injection_api.h b/ra/fsp/inc/api/r_rsip_key_injection_api.h new file mode 100644 index 000000000..a0f40bd96 --- /dev/null +++ b/ra/fsp/inc/api/r_rsip_key_injection_api.h @@ -0,0 +1,480 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup RSIP_KEY_INJECTION_API RSIP key injection Interface + * @brief Interface for key injection by Renesas Secure IP (RSIP) functions. + * + * @section RSIP_API_Summary Summary + * The RSIP key injection interface provides RSIP functionality. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_RSIP_KEY_INJECTION_API_H +#define R_RSIP_KEY_INJECTION_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* For AES operation. */ +#define R_RSIP_AES256_KEY_INDEX_WORD_SIZE (13U) + +/* For RSA operation. */ +#define R_RSIP_RSA2048_PUBLIC_KEY_INDEX_WORD_SIZE (73U) +#define R_RSIP_RSA3072_PUBLIC_KEY_INDEX_WORD_SIZE (105U) +#define R_RSIP_RSA4096_PUBLIC_KEY_INDEX_WORD_SIZE (137U) +#define R_RSIP_RSA2048_PRIVATE_KEY_INDEX_WORD_SIZE (133U) +#define R_RSIP_RSA3072_PRIVATE_KEY_INDEX_WORD_SIZE (197U) +#define R_RSIP_RSA4096_PRIVATE_KEY_INDEX_WORD_SIZE (261U) + +/* For ECC operation. */ +#define R_RSIP_ECCP384_PUBLIC_KEY_INDEX_WORD_SIZE (29U) +#define R_RSIP_ECCP384_PRIVATE_KEY_INDEX_WORD_SIZE (17U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Key injection type. */ +typedef enum e_rsip_key_injection_type +{ + RSIP_KEY_INJECTION_TYPE_ENCRYPTED = 0, ///< Input encrypted user key + RSIP_KEY_INJECTION_TYPE_PLAIN = 1, ///< Input plain user key +} rsip_key_injection_type_t; + + +/*******************************************************************************************************************//** + * @cond + **********************************************************************************************************************/ + +/** AES128/256 wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_aes_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_AES256_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_aes_wrapped_key_t; + +/** RSA 2048bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa2048_public_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA2048_PUBLIC_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa2048_public_wrapped_key_t; + +/** RSA 3072bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa3072_public_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA3072_PUBLIC_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa3072_public_wrapped_key_t; + +/** RSA 4096bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa4096_public_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA4096_PUBLIC_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa4096_public_wrapped_key_t; + +/** RSA 2048bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa2048_private_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA2048_PRIVATE_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa2048_private_wrapped_key_t; + +/** RSA 3072bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa3072_private_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA3072_PRIVATE_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa3072_private_wrapped_key_t; + +/** RSA 4096bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct rsip_rsa4096_private_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_RSA4096_PRIVATE_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_rsa4096_private_wrapped_key_t; + +/** ECC 256/384 public wrapped key data structure */ +typedef struct rsip_ecc_public_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_ECCP384_PUBLIC_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_ecc_public_wrapped_key_t; + +/** ECC 256/384 private wrapped key data structure */ +typedef struct rsip_ecc_private_wrapped_key +{ + uint32_t type; ///< Key type + uint32_t value[R_RSIP_ECCP384_PRIVATE_KEY_INDEX_WORD_SIZE]; ///< Wrapped key value +} rsip_ecc_private_wrapped_key_t; + +/*******************************************************************************************************************//** + * @endcond + **********************************************************************************************************************/ + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_rsip_key_injection_api +{ + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_RSIP_AES128_InitialKeyWrap "R_RSIP_AES128_InitialKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128_InitialKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_aes_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_RSIP_AES256_InitialKeyWrap "R_RSIP_AES256_InitialKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256_InitialKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_aes_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 2048-bit RSA wrapped public key. + * @par Implemented as + * - @ref R_RSIP_RSA2048_InitialPublicKeyWrap "R_RSIP_RSA2048_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 2048-bit RSA wrapped public key + */ + fsp_err_t (* RSA2048_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa2048_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 2048-bit RSA wrapped private key. + * @par Implemented as + * - @ref R_RSIP_RSA2048_InitialPrivateKeyWrap "R_RSIP_RSA2048_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 2048-bit RSA wrapped private key + */ + fsp_err_t (* RSA2048_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa2048_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 3072-bit RSA wrapped public key. + * @par Implemented as + * - @ref R_RSIP_RSA3072_InitialPublicKeyWrap "R_RSIP_RSA3072_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 3072-bit RSA wrapped public key + */ + fsp_err_t (* RSA3072_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa3072_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 3072-bit RSA wrapped private key. + * @par Implemented as + * - @ref R_RSIP_RSA3072_InitialPrivateKeyWrap "R_RSIP_RSA3072_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 3072-bit RSA wrapped private key + */ + fsp_err_t (* RSA3072_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa3072_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 4096-bit RSA wrapped public key. + * @par Implemented as + * - @ref R_RSIP_RSA4096_InitialPublicKeyWrap "R_RSIP_RSA4096_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 4096-bit RSA wrapped public key + */ + fsp_err_t (* RSA4096_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa4096_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 4096-bit RSA wrapped private key. + * @par Implemented as + * - @ref R_RSIP_RSA4096_InitialPrivateKeyWrap "R_RSIP_RSA4096_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 4096-bit RSA wrapped private key + */ + fsp_err_t (* RSA4096_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_rsa4096_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit ECC wrapped public key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp256r1_InitialPublicKeyWrap "R_RSIP_ECC_secp256r1_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped public key + */ + fsp_err_t (* ECC_secp256r1_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit ECC wrapped private key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp256r1_InitialPrivateKeyWrap "R_RSIP_ECC_secp256r1_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped private key + */ + fsp_err_t (* ECC_secp256r1_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 384-bit ECC wrapped public key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp384r1_InitialPublicKeyWrap "R_RSIP_ECC_secp384r1_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 384-bit ECC wrapped public key + */ + fsp_err_t (* ECC_secp384r1_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 384-bit ECC wrapped private key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp384r1_InitialPrivateKeyWrap "R_RSIP_ECC_secp384r1_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 384-bit ECC wrapped private key + */ + fsp_err_t (* ECC_secp384r1_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit ECC wrapped public key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp256k1_InitialPublicKeyWrap "R_RSIP_ECC_secp256k1_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped public key + */ + fsp_err_t (* ECC_secp256k1_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit ECC wrapped private key. + * @par Implemented as + * - @ref R_RSIP_ECC_secp256k1_InitialPrivateKeyWrap "R_RSIP_ECC_secp256k1_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped private key + */ + fsp_err_t (* ECC_secp256k1_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit brainpool ECC wrapped public key. + * @par Implemented as + * - @ref R_RSIP_ECC_brainpoolP256r1_InitialPublicKeyWrap "R_RSIP_ECC_brainpoolP256r1_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped public key + */ + fsp_err_t (* ECC_brainpoolP256r1_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 256-bit brainpool ECC wrapped private key. + * @par Implemented as + * - @ref R_RSIP_ECC_brainpoolP256r1_InitialPrivateKeyWrap "R_RSIP_ECC_brainpoolP256r1_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 256-bit ECC wrapped private key + */ + fsp_err_t (* ECC_brainpoolP256r1_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_private_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 384-bit brainpool ECC wrapped public key. + * @par Implemented as + * - @ref R_RSIP_ECC_brainpoolP384r1_InitialPublicKeyWrap "R_RSIP_ECC_brainpoolP384r1_InitialPublicKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 384-bit ECC wrapped public key + */ + fsp_err_t (* ECC_brainpoolP384r1_InitialPublicKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_public_wrapped_key_t * const p_wrapped_key); + + /** This API outputs 384-bit brainpool ECC wrapped private key. + * @par Implemented as + * - @ref R_RSIP_ECC_brainpoolP384r1_InitialPrivateKeyWrap "R_RSIP_ECC_brainpoolP384r1_InitialPrivateKeyWrap()" + * + * @param[in] key_injection_type Selection key injection type when generating wrapped key + * @param[in] p_wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_initial_vector Initialization vector when generating encrypted key. + * When key injection type is plain, this is not required and any value can be specified. + * @param[in] p_user_key User key. If key injection type is not plain, it must be encrypted and have MAC appended. + * @param[out] p_wrapped_key 384-bit ECC wrapped private key + */ + fsp_err_t (* ECC_brainpoolP384r1_InitialPrivateKeyWrap)(rsip_key_injection_type_t const key_injection_type, + uint8_t const * const p_wrapped_user_factory_programming_key, + uint8_t const * const p_initial_vector, + uint8_t const * const p_user_key, + rsip_ecc_private_wrapped_key_t * const p_wrapped_key); + +} rsip_key_injection_api_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_RSIP_KEY_INJECTION_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_KEY_INJECTION_API) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_rtc_api.h b/ra/fsp/inc/api/r_rtc_api.h index cdb5fa9a7..72712da67 100644 --- a/ra/fsp/inc/api/r_rtc_api.h +++ b/ra/fsp/inc/api/r_rtc_api.h @@ -28,11 +28,9 @@ * * * @section RTC_API_Summary Summary - * The RTC Interface is for configuring Real Time Clock (RTC) functionality including alarm, periodic notiification and + * The RTC Interface is for configuring Real Time Clock (RTC) functionality including alarm, periodic notification and * error adjustment. * - * The Real Time Clock Interface can be implemented by: - * - @ref RTC * * @{ **********************************************************************************************************************/ @@ -57,6 +55,7 @@ FSP_HEADER /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_RTC_EVENT_T /** Events that can trigger a callback function */ typedef enum e_rtc_event @@ -65,6 +64,7 @@ typedef enum e_rtc_event RTC_EVENT_ALARM1_IRQ, ///< Real Time Clock ALARM 1 IRQ RTC_EVENT_PERIODIC_IRQ, ///< Real Time Clock PERIODIC IRQ } rtc_event_t; +#endif /** RTC alarm channel */ typedef enum e_rtc_alarm_channel @@ -83,8 +83,9 @@ typedef struct st_rtc_callback_args /** Clock source for the RTC block */ typedef enum e_rtc_count_source { - RTC_CLOCK_SOURCE_SUBCLK = 0, ///< Sub-clock oscillator - RTC_CLOCK_SOURCE_LOCO = 1 ///< Low power On Chip Oscillator + RTC_CLOCK_SOURCE_SUBCLK = 0, ///< Sub-clock oscillator + RTC_CLOCK_SOURCE_LOCO = 1, ///< Low power On Chip Oscillator + RTC_CLOCK_SOURCE_MAINCLK = 2 ///< Main clock oscillator } rtc_clock_source_t; /** RTC run state */ @@ -126,6 +127,8 @@ typedef struct st_rtc_error_adjustment_cfg uint32_t adjustment_value; ///< Value of the prescaler for error adjustment } rtc_error_adjustment_cfg_t; +#ifndef BSP_OVERRIDE_RTC_PERIODIC_IRQ_SELECT_T + /** Periodic Interrupt select */ typedef enum e_rtc_periodic_irq_select { @@ -139,7 +142,12 @@ typedef enum e_rtc_periodic_irq_select RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_2_SECOND = 13, ///< A periodic irq is generated every 1/2 second RTC_PERIODIC_IRQ_SELECT_1_SECOND = 14, ///< A periodic irq is generated every 1 second RTC_PERIODIC_IRQ_SELECT_2_SECOND = 15, ///< A periodic irq is generated every 2 seconds + RTC_PERIODIC_IRQ_SELECT_1_MINUTE = 16, ///< A periodic irq is generated every 1 minute + RTC_PERIODIC_IRQ_SELECT_1_HOUR = 17, ///< A periodic irq is generated every 1 hour + RTC_PERIODIC_IRQ_SELECT_1_DAY = 18, ///< A periodic irq is generated every 1 day + RTC_PERIODIC_IRQ_SELECT_1_MONTH = 19, ///< A periodic irq is generated every 1 month } rtc_periodic_irq_select_t; +#endif /** Date and time structure defined in C standard library */ typedef struct tm rtc_time_t; @@ -155,6 +163,13 @@ typedef struct st_rtc_alarm_time bool mon_match; ///< Enable the alarm based on a match of the months field bool year_match; ///< Enable the alarm based on a match of the years field bool dayofweek_match; ///< Enable the alarm based on a match of the dayofweek field + bool sunday_match; ///< Enable the alarm on Sunday + bool monday_match; ///< Enable the alarm on Monday + bool tuesday_match; ///< Enable the alarm on Tuesday + bool wednesday_match; ///< Enable the alarm on Wednesday + bool thursday_match; ///< Enable the alarm on Thursday + bool friday_match; ///< Enable the alarm on Friday + bool saturday_match; ///< Enable the alarm on Saturday rtc_alarm_channel_t channel; ///< Select alarm 0 or alarm 1 } rtc_alarm_time_t; @@ -169,7 +184,7 @@ typedef struct st_rtc_info typedef struct st_rtc_cfg { rtc_clock_source_t clock_source; ///< Clock source for the RTC block - uint32_t freq_compare_value_loco; ///< The frequency comparison value for LOCO + uint32_t freq_compare_value; ///< The frequency comparison value rtc_error_adjustment_cfg_t const * const p_err_cfg; ///< Pointer to Error Adjustment configuration uint8_t alarm_ipl; ///< Alarm interrupt priority IRQn_Type alarm_irq; ///< Alarm interrupt vector @@ -183,8 +198,6 @@ typedef struct st_rtc_cfg } rtc_cfg_t; /** RTC control block. Allocate an instance specific control block to pass into the RTC API calls. - * @par Implemented as - * - @ref rtc_instance_ctrl_t */ typedef void rtc_ctrl_t; @@ -192,8 +205,6 @@ typedef void rtc_ctrl_t; typedef struct st_rtc_api { /** Open the RTC driver. - * @par Implemented as - * - @ref R_RTC_Open() * * @param[in] p_ctrl Pointer to RTC device handle * @param[in] p_cfg Pointer to the configuration structure @@ -201,34 +212,25 @@ typedef struct st_rtc_api fsp_err_t (* open)(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); /** Close the RTC driver. - * @par Implemented as - * - @ref R_RTC_Close() * * @param[in] p_ctrl Pointer to RTC device handle. */ fsp_err_t (* close)(rtc_ctrl_t * const p_ctrl); /** Sets the RTC clock source. - * @par Implemented as - * - @ref R_RTC_ClockSourceSet() * * @param[in] p_ctrl Pointer to RTC device handle */ fsp_err_t (* clockSourceSet)(rtc_ctrl_t * const p_ctrl); - /** Set the calendar time and start the calender counter - * @par Implemented as - * - @ref R_RTC_CalendarTimeSet() + /** Set the calendar time and start the calendar counter * * @param[in] p_ctrl Pointer to RTC device handle * @param[in] p_time Pointer to a time structure that contains the time to set - * @param[in] clock_start Flag that starts the clock right after it is set */ fsp_err_t (* calendarTimeSet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); /** Get the calendar time. - * @par Implemented as - * - @ref R_RTC_CalendarTimeGet() * * @param[in] p_ctrl Pointer to RTC device handle * @param[out] p_time Pointer to a time structure that contains the time to get @@ -236,18 +238,13 @@ typedef struct st_rtc_api fsp_err_t (* calendarTimeGet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); /** Set the calendar alarm time and enable the alarm interrupt. - * @par Implemented as - * - @ref R_RTC_CalendarAlarmSet() * * @param[in] p_ctrl Pointer to RTC device handle * @param[in] p_alarm Pointer to an alarm structure that contains the alarm time to set - * @param[in] irq_enable_flag Enable the ALARM irq if set */ fsp_err_t (* calendarAlarmSet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); /** Get the calendar alarm time. - * @par Implemented as - * - @ref R_RTC_CalendarAlarmGet() * * @param[in] p_ctrl Pointer to RTC device handle * @param[out] p_alarm Pointer to an alarm structure to fill up with the alarm time @@ -255,8 +252,6 @@ typedef struct st_rtc_api fsp_err_t (* calendarAlarmGet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); /** Set the periodic irq rate - * @par Implemented as - * - @ref R_RTC_PeriodicIrqRateSet() * * @param[in] p_ctrl Pointer to RTC device handle * @param[in] rate Rate of periodic interrupts @@ -265,8 +260,6 @@ typedef struct st_rtc_api /** Set time error adjustment. * - * @par Implemented as - * - @ref R_RTC_ErrorAdjustmentSet() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] err_adj_cfg Pointer to the Error Adjustment Config @@ -275,8 +268,6 @@ typedef struct st_rtc_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_RTC_CallbackSet() * * @param[in] p_ctrl Pointer to the RTC control block. * @param[in] p_callback Callback function @@ -288,8 +279,6 @@ typedef struct st_rtc_api /** Return the currently configure clock source for the RTC * - * @par Implemented as - * - @ref R_RTC_InfoGet() * * @param[in] p_ctrl Pointer to control handle structure * @param[out] p_rtc_info Pointer to RTC information structure @@ -306,7 +295,7 @@ typedef struct st_rtc_instance } rtc_instance_t; /*******************************************************************************************************************//** - * @} (end addtogroup RTC_API) + * @} (end defgroup RTC_API) **********************************************************************************************************************/ /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_sce_key_injection_api.h b/ra/fsp/inc/api/r_sce_key_injection_api.h index c2c08c7c2..7c6795666 100644 --- a/ra/fsp/inc/api/r_sce_key_injection_api.h +++ b/ra/fsp/inc/api/r_sce_key_injection_api.h @@ -26,8 +26,6 @@ * @section SCE_API_Summary Summary * The SCE key injection interface provides SCE functionality. * - * The SCE key injection interface can be implemented by: - * - @ref SCE_KEY_INJECTION * * @{ **********************************************************************************************************************/ @@ -209,8 +207,6 @@ typedef struct sce_ecc_private_wrapped_key typedef struct st_sce_key_injection_api { /** This API outputs 128-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES128_InitialKeyWrap "R_SCE_AES128_InitialKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -224,8 +220,6 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_aes_wrapped_key_t * const wrapped_key); /** This API outputs 192-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES192_InitialKeyWrap "R_SCE_AES192_InitialKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -239,8 +233,6 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_aes_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES256_InitialKeyWrap "R_SCE_AES256_InitialKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -254,8 +246,6 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_aes_wrapped_key_t * const wrapped_key); /** This API outputs key update key. - * @par Implemented as - * - @ref R_SCE_KeyUpdateKeyWrap "R_SCE_KeyUpdateKeyWrap()" * * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server * @param[in] initial_vector Initialization vector when generating encrypted_key @@ -267,8 +257,6 @@ typedef struct st_sce_key_injection_api sce_key_update_key_t * const key_update_key); /** This API updates 128-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES128_EncryptedKeyWrap "R_SCE_AES128_EncryptedKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -280,8 +268,6 @@ typedef struct st_sce_key_injection_api sce_aes_wrapped_key_t * const wrapped_key); /** This API updates 192-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES192_EncryptedKeyWrap "R_SCE_AES192_EncryptedKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -293,8 +279,6 @@ typedef struct st_sce_key_injection_api sce_aes_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit AES wrapped key. - * @par Implemented as - * - @ref R_SCE_AES256_EncryptedKeyWrap "R_SCE_AES256_EncryptedKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -306,8 +290,6 @@ typedef struct st_sce_key_injection_api sce_aes_wrapped_key_t * const wrapped_key); /** This API outputs 2048-bit RSA public wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA2048_InitialPublicKeyWrap "R_SCE_RSA2048_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -323,8 +305,6 @@ typedef struct st_sce_key_injection_api sce_rsa2048_public_wrapped_key_t * const wrapped_key); /** This API outputs 3072-bit RSA public wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA3072_InitialPublicKeyWrap "R_SCE_RSA3072_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -340,8 +320,6 @@ typedef struct st_sce_key_injection_api sce_rsa3072_public_wrapped_key_t * const wrapped_key); /** This API outputs 4096-bit RSA public wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA4096_InitialPublicKeyWrap "R_SCE_RSA4096_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -357,8 +335,6 @@ typedef struct st_sce_key_injection_api sce_rsa4096_public_wrapped_key_t * const wrapped_key); /** This API outputs 2048-bit RSA private wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA2048_InitialPrivateKeyWrap "R_SCE_RSA2048_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -374,8 +350,6 @@ typedef struct st_sce_key_injection_api sce_rsa2048_private_wrapped_key_t * const wrapped_key); /** This API outputs 2048-bit RSA public wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA2048_EncryptedPublicKeyWrap "R_SCE_RSA2048_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -388,8 +362,6 @@ typedef struct st_sce_key_injection_api sce_rsa2048_public_wrapped_key_t * const wrapped_key); /** This API outputs 2048-bit RSA private wrapped key. - * @par Implemented as - * - @ref R_SCE_RSA2048_EncryptedPrivateKeyWrap "R_SCE_RSA2048_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -402,8 +374,6 @@ typedef struct st_sce_key_injection_api sce_rsa2048_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256r1_InitialPublicKeyWrap "R_SCE_ECC_secp256r1_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -419,8 +389,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256k1_InitialPublicKeyWrap "R_SCE_ECC_secp256k1_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -436,8 +404,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp384r1_InitialPublicKeyWrap "R_SCE_ECC_secp384r1_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -453,8 +419,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256r1_InitialPrivateKeyWrap "R_SCE_ECC_secp256r1_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -470,8 +434,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256k1_InitialPrivateKeyWrap "R_SCE_ECC_secp256k1_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -487,8 +449,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp384r1_InitialPrivateKeyWrap "R_SCE_ECC_secp384r1_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -504,8 +464,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap "R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -518,8 +476,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap "R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -532,8 +488,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap "R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -546,8 +500,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -560,8 +512,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -574,8 +524,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -588,8 +536,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit Brainpool ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap "R_SCE_ECC_brainpoolP256r1_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -605,8 +551,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit Brainpool ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap "R_SCE_ECC_brainpoolP256r1_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -622,8 +566,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit Brainpool ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap "R_SCE_ECC_brainpoolP384r1_InitialPublicKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -639,8 +581,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit Brainpool ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap "R_SCE_ECC_brainpoolP384r1_InitialPrivateKeyWrap()" * * @param[in] key_type Key type whether encrypted_key or plain key * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server @@ -656,8 +596,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP256r1_EncryptedPublicKeyWrap "R_SCE_ECC_brainpoolP256r1_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -670,8 +608,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 256-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP256r1_EncryptedPrivateKeyWrap "R_SCE_ECC_brainpoolP256r1_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -684,8 +620,6 @@ typedef struct st_sce_key_injection_api sce_ecc_private_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC public wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP384r1_EncryptedPublicKeyWrap "R_SCE_ECC_brainpoolP384r1_EncryptedPublicKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -698,8 +632,6 @@ typedef struct st_sce_key_injection_api sce_ecc_public_wrapped_key_t * const wrapped_key); /** This API outputs 384-bit ECC private wrapped key. - * @par Implemented as - * - @ref R_SCE_ECC_brainpoolP384r1_EncryptedPrivateKeyWrap "R_SCE_ECC_brainpoolP384r1_EncryptedPrivateKeyWrap()" * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended diff --git a/ra/fsp/inc/api/r_sdmmc_api.h b/ra/fsp/inc/api/r_sdmmc_api.h index 6ae7d933c..fdb192a59 100644 --- a/ra/fsp/inc/api/r_sdmmc_api.h +++ b/ra/fsp/inc/api/r_sdmmc_api.h @@ -40,8 +40,6 @@ FSP_HEADER * @section SDMMC_API_SUMMARY Summary * The r_sdhi interface provides standard SD and eMMC media functionality. This interface also supports SDIO. * - * The SD/MMC interface is implemented by: - * - @ref SDHI * * @{ **********************************************************************************************************************/ @@ -340,8 +338,6 @@ typedef struct st_sdmmc_cfg } sdmmc_cfg_t; /** SD/MMC control block. Allocate an instance specific control block to pass into the SD/MMC API calls. - * @par Implemented as - * - sdmmc_instance_ctrl_t */ typedef void sdmmc_ctrl_t; @@ -350,8 +346,6 @@ typedef struct st_sdmmc_api { /** Open the SD/MMC driver. * - * @par Implemented as - * - @ref R_SDHI_Open() * * @param[in] p_ctrl Pointer to SD/MMC instance control block. * @param[in] p_cfg Pointer to SD/MMC instance configuration structure. @@ -361,8 +355,6 @@ typedef struct st_sdmmc_api /** Initializes an SD/MMC device. If the device is a card, the card must be plugged in prior to calling this API. * This API blocks until the device initialization procedure is complete. * - * @par Implemented as - * - @ref R_SDHI_MediaInit() * * @param[in] p_ctrl Pointer to SD/MMC instance control block. * @param[out] p_device Pointer to store device information. @@ -372,8 +364,6 @@ typedef struct st_sdmmc_api /** Read data from an SD/MMC channel. * This API is not supported for SDIO devices. * - * @par Implemented as - * - @ref R_SDHI_Read() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[out] p_dest Pointer to data buffer to read data to. @@ -387,8 +377,6 @@ typedef struct st_sdmmc_api /** Write data to SD/MMC channel. * This API is not supported for SDIO devices. * - * @par Implemented as - * - @ref R_SDHI_Write() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[in] p_source Pointer to data buffer to write data from. @@ -402,8 +390,6 @@ typedef struct st_sdmmc_api /** Read one byte of I/O data from an SDIO device. * This API is not supported for SD or eMMC memory devices. * - * @par Implemented as - * - @ref R_SDHI_ReadIo() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[out] p_data Pointer to location to store data byte. @@ -416,8 +402,6 @@ typedef struct st_sdmmc_api /** Write one byte of I/O data to an SDIO device. * This API is not supported for SD or eMMC memory devices. * - * @par Implemented as - * - @ref R_SDHI_WriteIo() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[in,out] p_data Pointer to data byte to write. Read data is also provided here if @@ -432,8 +416,6 @@ typedef struct st_sdmmc_api /** Read multiple bytes or blocks of I/O data from an SDIO device. * This API is not supported for SD or eMMC memory devices. * - * @par Implemented as - * - @ref R_SDHI_ReadIoExt() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[out] p_dest Pointer to data buffer to read data to. @@ -450,8 +432,6 @@ typedef struct st_sdmmc_api /** Write multiple bytes or blocks of I/O data to an SDIO device. * This API is not supported for SD or eMMC memory devices. * - * @par Implemented as - * - @ref R_SDHI_WriteIoExt() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[in] p_source Pointer to data buffer to write data from. @@ -468,8 +448,6 @@ typedef struct st_sdmmc_api /** Enables SDIO interrupt for SD/MMC instance. * This API is not supported for SD or eMMC memory devices. * - * @par Implemented as - * - @ref R_SDHI_IoIntEnable * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[in] enable Interrupt enable = true, interrupt disable = false. @@ -478,8 +456,6 @@ typedef struct st_sdmmc_api /** Get SD/MMC device status. * - * @par Implemented as - * - @ref R_SDHI_StatusGet() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[out] p_status Pointer to current driver status. @@ -489,8 +465,6 @@ typedef struct st_sdmmc_api /** Erase SD/MMC sectors. The sector size for erase is fixed at 512 bytes. * This API is not supported for SDIO devices. * - * @par Implemented as - * - @ref R_SDHI_Erase * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. * @param[in] start_sector First sector to erase. Must be a multiple of sdmmc_device_t::erase_sector_count. @@ -500,8 +474,6 @@ typedef struct st_sdmmc_api fsp_err_t (* erase)(sdmmc_ctrl_t * const p_ctrl, uint32_t const start_sector, uint32_t const sector_count); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_SDHI_CallbackSet() * * @param[in] p_ctrl Control block set in @ref sdmmc_api_t::open call. * @param[in] p_callback Callback function to register @@ -509,13 +481,11 @@ typedef struct st_sdmmc_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(sdmmc_ctrl_t * const p_api_ctrl, void (* p_callback)(sdmmc_callback_args_t *), + fsp_err_t (* callbackSet)(sdmmc_ctrl_t * const p_ctrl, void (* p_callback)(sdmmc_callback_args_t *), void const * const p_context, sdmmc_callback_args_t * const p_callback_memory); /** Close open SD/MMC device. * - * @par Implemented as - * - @ref R_SDHI_Close() * * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. */ @@ -536,5 +506,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup SDMMC_API) + * @} (end defgroup SDMMC_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_slcdc_api.h b/ra/fsp/inc/api/r_slcdc_api.h index a57aa8430..bbd307e80 100644 --- a/ra/fsp/inc/api/r_slcdc_api.h +++ b/ra/fsp/inc/api/r_slcdc_api.h @@ -201,8 +201,6 @@ typedef struct st_slcdc_cfg } slcdc_cfg_t; /** SLCDC control block. Allocate an instance specific control block to pass into the SLCDC API calls. - * @par Implemented as - * - slcdc_instance_ctrl_t */ /** SLCDC control block */ @@ -212,8 +210,6 @@ typedef void slcdc_ctrl_t; typedef struct st_slcdc_api { /** Open SLCDC. - * @par Implemented as - * - @ref R_SLCDC_Open() * @param[in,out] p_ctrl Pointer to display interface control block. Must be declared by user. * @param[in] p_cfg Pointer to display configuration structure. All elements of this structure must be * set by the user. @@ -223,8 +219,6 @@ typedef struct st_slcdc_api /** Write data to the SLCDC segment data array. * Specifies the initial display data. Except when using 8-time slice mode, store values in the lower 4 bits when * writing to the A-pattern area and in the upper 4 bits when writing to the B-pattern area. - * @par Implemented as - * - @ref R_SLCDC_Write() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] start_segment Specify the start segment number to be written. * @param[in] p_data Pointer to the display data to be written to the specified segments. @@ -235,8 +229,6 @@ typedef struct st_slcdc_api /** Rewrite data in the SLCDC segment data array. * Rewrites the LCD display data in 1-bit units. If a bit is not specified for rewriting, the value stored in the bit is held as it is. - * @par Implemented as - * - @ref R_SLCDC_Modify() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] segment The segment to be written. * @param[in] data_mask Mask the data being displayed. Set 0 to the bit to be rewritten and set 1 to the other bits. Multiple bits can be rewritten. @@ -248,24 +240,18 @@ typedef struct st_slcdc_api /** Enable display signal output. * Displays the segment data on the LCD. - * @par Implemented as - * - @ref R_SLCDC_Start() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* start)(slcdc_ctrl_t * const p_ctrl); /** Disable display signal output. * Stops displaying data on the LCD. - * @par Implemented as - * - @ref R_SLCDC_Stop() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* stop)(slcdc_ctrl_t * const p_ctrl); /** Set the display contrast. * This function can be used only when the internal voltage boosting method is used for drive voltage generation. - * @par Implemented as - * - @ref R_SLCDC_SetContrast() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* setContrast)(slcdc_ctrl_t * const p_ctrl, slcdc_contrast_t const contrast); @@ -281,16 +267,12 @@ typedef struct st_slcdc_api * 4) Enable IRQ, RTC_EVENT_PERIODIC_IRQ * Refer to the User's Manual for the detailed procedure. * - * @par Implemented as - * - @ref R_SLCDC_SetDisplayArea() * @param[in] p_ctrl Pointer to display interface control block. * @param[in] display_area Display area to be used, A-pattern or B-pattern area. */ fsp_err_t (* setDisplayArea)(slcdc_ctrl_t * const p_ctrl, slcdc_display_area_t const display_area); /** Close SLCDC. - * @par Implemented as - * - @ref R_SLCDC_Close() * @param[in] p_ctrl Pointer to display interface control block. */ fsp_err_t (* close)(slcdc_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/api/r_smci_api.h b/ra/fsp/inc/api/r_smci_api.h index f5b420670..ffed4add8 100644 --- a/ra/fsp/inc/api/r_smci_api.h +++ b/ra/fsp/inc/api/r_smci_api.h @@ -30,8 +30,6 @@ * - Runtime baud-rate change (baud = 1/ETU) * - Hardware resource locking during a transaction * - * Implemented by: - * - @ref SCI_SMCI * * @{ **********************************************************************************************************************/ @@ -189,8 +187,6 @@ typedef struct st_smci_cfg } smci_cfg_t; /** Smart Card Interface control block. Allocate an instance specific control block to pass into the SMCI API calls. - * @par Implemented as - * - smci_instance_ctrl_t */ typedef void smci_ctrl_t; @@ -198,8 +194,6 @@ typedef void smci_ctrl_t; typedef struct st_smci_api { /** Open Smart Card Interface Mode (SMCI) - * @par Implemented as - * - @ref R_SCI_SMCI_Open() * * @param[in,out] p_ctrl Pointer to the SMCI control block. Must be declared by user. Value set here. * @param[in] smci_cfg_t Pointer to SMCI configuration structure. All elements of this structure must be set by @@ -210,8 +204,6 @@ typedef struct st_smci_api /** Read from Smart Card device. The read buffer is used until the read is complete. When a transfer is complete, * the callback is called with event SMCI_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received * in the callback function with event SMCI_EVENT_RX_CHAR. - * @par Implemented as - * - @ref R_SCI_SMCI_Read() * * @param[in] p_ctrl Pointer to the SMCI control block for the channel. * @param[in] p_dest Destination address to read data from. @@ -222,8 +214,6 @@ typedef struct st_smci_api /** Write to Smart Card device. The write buffer is used until write is complete. Do not overwrite write buffer * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), * the callback called with event SMCI_EVENT_TX_COMPLETE. - * @par Implemented as - * - @ref R_SCI_SMCI_Write() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[in] p_src Source address to write data to. @@ -232,8 +222,6 @@ typedef struct st_smci_api fsp_err_t (* write)(smci_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); /** Change the peripheral settings based on provided transfer mode and data convention type - * @par Implemented as - * - @ref R_SCI_SMCI_TransferModeSet() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[in] p_transfer_mode_params Pointer to SMCI setting like protocol, convention, and gsm_mode @@ -245,8 +233,6 @@ typedef struct st_smci_api * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud * settings have been applied. * - * @par Implemented as - * - @ref R_SCI_SMCI_BaudSet() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[in] p_baud_setting Pointer to module specific setting for configuring baud rate. @@ -254,8 +240,6 @@ typedef struct st_smci_api fsp_err_t (* baudSet)(smci_ctrl_t * const p_ctrl, void const * const p_baud_setting); /** Get the driver specific information. - * @par Implemented as - * - @ref R_SCI_SMCI_StatusGet() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[out] p_status State info for the driver. @@ -264,8 +248,6 @@ typedef struct st_smci_api /** * Enable or disable the SMCI clock to control the start of the activation or de-activation - * @par Implemented as - * - @ref R_SCI_SMCI_ClockControl() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[in] clock_enable True: enables clock output, False disables it @@ -274,8 +256,6 @@ typedef struct st_smci_api /** * Specify callback function and optional context pointer and callback memory pointer. - * @par Implemented as - * - SMCI_CallbackSet() * * @param[in] p_ctrl Pointer to the SMCI control block. * @param[in] p_callback Callback function @@ -283,12 +263,10 @@ typedef struct st_smci_api * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(smci_ctrl_t * const p_api_ctrl, void (* p_callback)(smci_callback_args_t *), + fsp_err_t (* callbackSet)(smci_ctrl_t * const p_ctrl, void (* p_callback)(smci_callback_args_t *), void const * const p_context, smci_callback_args_t * const p_callback_memory); /** Close SMCI device. - * @par Implemented as - * - @ref R_SCI_SMCI_Close() * * @param[in] p_ctrl Pointer to the SMCI control block. */ diff --git a/ra/fsp/inc/api/r_spi_api.h b/ra/fsp/inc/api/r_spi_api.h index 2078d9d0e..d06c70bd7 100644 --- a/ra/fsp/inc/api/r_spi_api.h +++ b/ra/fsp/inc/api/r_spi_api.h @@ -29,9 +29,6 @@ * @section SPI_API_SUMMARY Summary * Provides a common interface for communication using the SPI Protocol. * - * Implemented by: - * - @ref SPI - * - @ref SCI_SPI * * @{ ********************************************************************************************************************/ @@ -55,6 +52,8 @@ FSP_HEADER * Typedef definitions ********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_SPI_BIT_WIDTH_T + /** Data bit width */ typedef enum e_spi_bit_width { @@ -63,31 +62,34 @@ typedef enum e_spi_bit_width SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits (byte) SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits (byte) SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits (byte) - SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits (word) - SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits (word) - SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits (word) - SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits (word) - SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits (word) - SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits (word) - SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits (word) - SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits (word) + SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits (halfword) + SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits (halfword) + SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits (halfword) + SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits (halfword) + SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits (halfword) + SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits (halfword) + SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits (halfword) + SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits (halfword) SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits (word) SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits (word) SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits (word) - SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits (longword) + SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits (word) SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits (word) SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits (word) - SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits (longword) - SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits (longword) - SPI_BIT_WIDTH_25_BITS = (25), ///< Data bit width is 25 bits (longword) + SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits (word) + SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits (word) + SPI_BIT_WIDTH_25_BITS = (24), ///< Data bit width is 25 bits (word) SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits (word) SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits (word) SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits (word) SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits (word) - SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits (longword) - SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits (longword) - SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits (longword) + SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits (word) + SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits (word) + SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits (word) } spi_bit_width_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_MODE_T /** Master or slave operating mode */ typedef enum e_spi_mode @@ -95,6 +97,9 @@ typedef enum e_spi_mode SPI_MODE_MASTER, ///< Channel operates as SPI master SPI_MODE_SLAVE ///< Channel operates as SPI slave } spi_mode_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_PHASE_T /** Clock phase */ typedef enum e_spi_clk_phase @@ -102,6 +107,9 @@ typedef enum e_spi_clk_phase SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge } spi_clk_phase_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_POLARITY_T /** Clock polarity */ typedef enum e_spi_clk_polarity @@ -109,6 +117,7 @@ typedef enum e_spi_clk_polarity SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle } spi_clk_polarity_t; +#endif /** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be * controlled by the master. This usually happens when the connecting device is also acting as master. @@ -119,12 +128,15 @@ typedef enum e_spi_mode_fault SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off } spi_mode_fault_t; +#ifndef BSP_OVERRIDE_SPI_BIT_ORDER_T + /** Bit order */ typedef enum e_spi_bit_order { SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission } spi_bit_order_t; +#endif /** SPI events */ typedef enum e_spi_event @@ -174,18 +186,14 @@ typedef struct st_spi_cfg spi_clk_polarity_t clk_polarity; ///< Clock level when idle spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first - transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here. Set to NULL if unused. - transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMAC write transfer, link a transfer instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMAC read transfer, link a transfer instance here. Set to NULL if unused. void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function void const * p_context; ///< User defined context passed to callback function void const * p_extend; ///< Extended SPI hardware dependent configuration } spi_cfg_t; /** SPI control block. Allocate an instance specific control block to pass into the SPI API calls. - * @par Implemented as - * - spi_instance_ctrl_t - * - spi_b_instance_ctrl_t - * - sci_spi_instance_ctrl_t */ typedef void spi_ctrl_t; @@ -193,10 +201,6 @@ typedef void spi_ctrl_t; typedef struct st_spi_api { /** Initialize a channel for SPI communication mode. - * @par Implemented as - * - @ref R_SPI_Open() - * - @ref R_SPI_B_Open() - * - @ref R_SCI_SPI_Open() * * @param[in, out] p_ctrl Pointer to user-provided storage for the control block. * @param[in] p_cfg Pointer to SPI configuration structure. @@ -204,27 +208,19 @@ typedef struct st_spi_api fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg); /** Receive data from a SPI device. - * @par Implemented as - * - @ref R_SPI_Read() - * - @ref R_SPI_B_Read() - * - @ref R_SCI_SPI_Read() * * @param[in] p_ctrl Pointer to the control block for the channel. - * @param[in] length Number of units of data to be transferred (unit size specified by the - * bit_width). - * @param[in] bit_width Data bit width to be transferred. * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI * device. It is the responsibility of the caller to ensure that adequate space is available * to hold the requested data count. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. */ fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, spi_bit_width_t const bit_width); /** Transmit data to a SPI device. - * @par Implemented as - * - @ref R_SPI_Write() - * - @ref R_SPI_B_Write() - * - @ref R_SCI_SPI_Write() * * @param[in] p_ctrl Pointer to the control block for the channel. * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. @@ -237,10 +233,6 @@ typedef struct st_spi_api spi_bit_width_t const bit_width); /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex). - * @par Implemented as - * - @ref R_SPI_WriteRead() - * - @ref R_SPI_B_WriteRead() - * - @ref R_SCI_SPI_WriteRead() * * @param[in] p_ctrl Pointer to the control block for the channel. * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. @@ -256,10 +248,6 @@ typedef struct st_spi_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_SPI_CallbackSet() - * - @ref R_SPI_B_CallbackSet() - * - @ref R_SCI_SPI_CallbackSet() * * @param[in] p_ctrl Pointer to the SPI control block. * @param[in] p_callback Callback function @@ -267,14 +255,10 @@ typedef struct st_spi_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *), + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_ctrl, void (* p_callback)(spi_callback_args_t *), void const * const p_context, spi_callback_args_t * const p_callback_memory); /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. - * @par Implemented as - * - @ref R_SPI_Close() - * - @ref R_SPI_B_Close() - * - @ref R_SCI_SPI_Close() * * @param[in] p_ctrl Pointer to the control block for the channel. */ diff --git a/ra/fsp/inc/api/r_spi_flash_api.h b/ra/fsp/inc/api/r_spi_flash_api.h index 20be993f3..e45ccf9df 100644 --- a/ra/fsp/inc/api/r_spi_flash_api.h +++ b/ra/fsp/inc/api/r_spi_flash_api.h @@ -65,7 +65,7 @@ typedef enum e_spi_flash_read_mode /** SPI protocol. */ typedef enum e_spi_flash_protocol { - /** Extended SPI mode (commands on 1 line) or 1S-1S-1S protocol mode on OSPI_B. */ + /** Extended SPI mode (commands on 1 line) */ SPI_FLASH_PROTOCOL_EXTENDED_SPI = 0x000, /** QPI mode (commands on 4 lines). Note that the application must ensure the device is in QPI mode. */ @@ -77,22 +77,25 @@ typedef enum e_spi_flash_protocol /** DOPI mode (command and data on 8 lines, dual data rate). Note that the application must ensure the device is in DOPI mode. */ SPI_FLASH_PROTOCOL_DOPI = 0x004, - /** 4S-4D-4D protocol mode on OSPI_B. */ + /** 1S-1S-1S protocol mode */ + SPI_FLASH_PROTOCOL_1S_1S_1S = 0x000, + + /** 4S-4D-4D protocol mode */ SPI_FLASH_PROTOCOL_4S_4D_4D = 0x3B2, - /** 8D-8D-8D protocol mode on OSPI_B. */ + /** 8D-8D-8D protocol mode */ SPI_FLASH_PROTOCOL_8D_8D_8D = 0x3FF, - /** 1S-2S-2S protocol mode on OSPI_B. */ + /** 1S-2S-2S protocol mode */ SPI_FLASH_PROTOCOL_1S_2S_2S = 0x048, - /** 2S-2S-2S protocol mode on OSPI_B. */ + /** 2S-2S-2S protocol mode */ SPI_FLASH_PROTOCOL_2S_2S_2S = 0x049, - /** 1S-4S-4S protocol mode on OSPI_B. */ + /** 1S-4S-4S protocol mode */ SPI_FLASH_PROTOCOL_1S_4S_4S = 0x090, - /** 4S-4S-4S protocol mode on OSPI_B. */ + /** 4S-4S-4S protocol mode */ SPI_FLASH_PROTOCOL_4S_4S_4S = 0x092 } spi_flash_protocol_t; @@ -120,9 +123,9 @@ typedef enum e_spi_flash_data_lines /** Number of dummy cycles for fast read operations. */ typedef enum e_spi_flash_dummy_clocks { - /** Default is 6 clocks for Fast Read Quad I/O, 4 clocks for Fast Read Dual I/O, and 8 clocks for other - * fast read instructions including Fast Read Quad Output, Fast Read Dual Output, and Fast Read. */ - SPI_FLASH_DUMMY_CLOCKS_DEFAULT, + SPI_FLASH_DUMMY_CLOCKS_0 = 0, ///< 0 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_1, ///< 1 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_2, ///< 2 dummy clocks SPI_FLASH_DUMMY_CLOCKS_3, ///< 3 dummy clocks SPI_FLASH_DUMMY_CLOCKS_4, ///< 4 dummy clocks SPI_FLASH_DUMMY_CLOCKS_5, ///< 5 dummy clocks @@ -138,6 +141,21 @@ typedef enum e_spi_flash_dummy_clocks SPI_FLASH_DUMMY_CLOCKS_15, ///< 15 dummy clocks SPI_FLASH_DUMMY_CLOCKS_16, ///< 16 dummy clocks SPI_FLASH_DUMMY_CLOCKS_17, ///< 17 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_18, ///< 18 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_19, ///< 19 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_20, ///< 20 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_21, ///< 21 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_22, ///< 22 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_23, ///< 23 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_24, ///< 24 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_25, ///< 25 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_26, ///< 26 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_27, ///< 27 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_28, ///< 28 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_29, ///< 29 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_30, ///< 30 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_31, ///< 31 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_DEFAULT = 0xFF, } spi_flash_dummy_clocks_t; /** Direct Read and Write direction */ @@ -326,5 +344,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup SPI_FLASH_API) + * @} (end defgroup SPI_FLASH_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_three_phase_api.h b/ra/fsp/inc/api/r_three_phase_api.h index af0b422d0..f0f7219b7 100644 --- a/ra/fsp/inc/api/r_three_phase_api.h +++ b/ra/fsp/inc/api/r_three_phase_api.h @@ -30,8 +30,6 @@ * The Three-Phase interface provides functionality for synchronous start/stop/reset control of three timer channels for * use in 3-phase motor control applications. * - * Implemented by: - * - @ref GPT_THREE_PHASE * * @{ **********************************************************************************************************************/ @@ -91,8 +89,6 @@ typedef struct st_three_phase_duty_cycle } three_phase_duty_cycle_t; /** Three-Phase control block. Allocate an instance specific control block to pass into the timer API calls. - * @par Implemented as - * - gpt_three_phase_instance_ctrl_t */ typedef void three_phase_ctrl_t; @@ -116,8 +112,6 @@ typedef struct st_three_phase_cfg typedef struct st_three_phase_api { /** Initial configuration. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -125,24 +119,18 @@ typedef struct st_three_phase_api fsp_err_t (* open)(three_phase_ctrl_t * const p_ctrl, three_phase_cfg_t const * const p_cfg); /** Start all three timers synchronously. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_Start() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. */ fsp_err_t (* start)(three_phase_ctrl_t * const p_ctrl); /** Stop all three timers synchronously. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_Stop() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. */ fsp_err_t (* stop)(three_phase_ctrl_t * const p_ctrl); /** Reset all three timers synchronously. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_Reset() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. */ @@ -151,8 +139,6 @@ typedef struct st_three_phase_api /** Sets the duty cycle match values. If the timer is counting, the updated duty cycle is * reflected after the next timer expiration. * - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_DutyCycleSet() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. * @param[in] p_duty_cycle Duty cycle values for all three timer channels. @@ -160,8 +146,6 @@ typedef struct st_three_phase_api fsp_err_t (* dutyCycleSet)(three_phase_ctrl_t * const p_ctrl, three_phase_duty_cycle_t * const p_duty_cycle); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_CallbackSet() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call. * @param[in] p_callback Callback function to register with GPT U-channel @@ -169,12 +153,10 @@ typedef struct st_three_phase_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(three_phase_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *), + fsp_err_t (* callbackSet)(three_phase_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *), void const * const p_context, timer_callback_args_t * const p_callback_memory); /** Allows driver to be reconfigured and may reduce power consumption. - * @par Implemented as - * - @ref R_GPT_THREE_PHASE_Close() * * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. */ diff --git a/ra/fsp/inc/api/r_timer_api.h b/ra/fsp/inc/api/r_timer_api.h index f53db2c8b..af04a13bf 100644 --- a/ra/fsp/inc/api/r_timer_api.h +++ b/ra/fsp/inc/api/r_timer_api.h @@ -33,9 +33,6 @@ * If an instance supports output compare mode, it is provided in the extension configuration * timer_on__cfg_t defined in r_.h. * - * Implemented by: - * - @ref GPT - * - @ref AGT * * @{ **********************************************************************************************************************/ @@ -54,8 +51,6 @@ FSP_HEADER * Macro definitions **********************************************************************************************************************/ -/* Leading zeroes removed to avoid coding standard violation. */ - /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -68,6 +63,13 @@ typedef enum e_timer_event TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only + TIMER_EVENT_COMPARE_A, ///< A compare has occurred on signal A + TIMER_EVENT_COMPARE_B, ///< A compare has occurred on signal B + TIMER_EVENT_COMPARE_C, ///< A compare has occurred on signal C + TIMER_EVENT_COMPARE_D, ///< A compare has occurred on signal D + TIMER_EVENT_COMPARE_E, ///< A compare has occurred on signal E + TIMER_EVENT_COMPARE_F, ///< A compare has occurred on signal F + TIMER_EVENT_DEAD_TIME ///< Dead time event } timer_event_t; /** Timer variant types. */ @@ -89,9 +91,6 @@ typedef struct st_timer_callback_args } timer_callback_args_t; /** Timer control block. Allocate an instance specific control block to pass into the timer API calls. - * @par Implemented as - * - gpt_instance_ctrl_t - * - agt_instance_ctrl_t */ typedef void timer_ctrl_t; @@ -99,8 +98,9 @@ typedef void timer_ctrl_t; typedef enum e_timer_state { TIMER_STATE_STOPPED = 0, ///< Timer is stopped - TIMER_STATE_COUNTING = 1, ///< Timer is running + TIMER_STATE_COUNTING = 1 ///< Timer is running } timer_state_t; +#ifndef BSP_OVERRIDE_TIMER_MODE_T /** Timer operational modes */ typedef enum e_timer_mode @@ -117,9 +117,11 @@ typedef enum e_timer_mode * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be * set once and only need to be updated when the application needs to change the duty cycle. */ - TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U, + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U } timer_mode_t; +#endif + /** Direction of timer count */ typedef enum e_timer_direction { @@ -127,7 +129,9 @@ typedef enum e_timer_direction TIMER_DIRECTION_UP = 1 ///< Timer count goes down } timer_direction_t; -/** PCLK divisors */ +#ifndef BSP_OVERRIDE_TIMER_SOURCE_DIV_T + +/** Clock source divisors */ typedef enum e_timer_source_div { TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 @@ -142,6 +146,7 @@ typedef enum e_timer_source_div TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512 TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024 } timer_source_div_t; +#endif /** Timer information structure to store various information for a timer resource */ typedef struct st_timer_info @@ -191,9 +196,6 @@ typedef struct st_timer_cfg typedef struct st_timer_api { /** Initial configuration. - * @par Implemented as - * - @ref R_GPT_Open() - * - @ref R_AGT_Open() * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -201,45 +203,30 @@ typedef struct st_timer_api fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); /** Start the counter. - * @par Implemented as - * - @ref R_GPT_Start() - * - @ref R_AGT_Start() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ fsp_err_t (* start)(timer_ctrl_t * const p_ctrl); /** Stop the counter. - * @par Implemented as - * - @ref R_GPT_Stop() - * - @ref R_AGT_Stop() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl); /** Reset the counter to the initial value. - * @par Implemented as - * - @ref R_GPT_Reset() - * - @ref R_AGT_Reset() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl); /** Enables input capture. - * @par Implemented as - * - @ref R_GPT_Enable() - * - @ref R_AGT_Enable() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl); /** Disables input capture. - * @par Implemented as - * - @ref R_GPT_Disable() - * - @ref R_AGT_Disable() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ @@ -247,23 +234,17 @@ typedef struct st_timer_api /** Set the time until the timer expires. See implementation for details of period update timing. * - * @par Implemented as - * - @ref R_GPT_PeriodSet() - * - @ref R_AGT_PeriodSet() * * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in * @ref timer_api_t::open. * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. - * @param[in] p_period Time until timer should expire. + * @param[in] period Time until timer should expire. */ fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period); /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is * reflected after the next timer expiration. * - * @par Implemented as - * - @ref R_GPT_DutyCycleSet() - * - @ref R_AGT_DutyCycleSet() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. * @param[in] duty_cycle_counts Time until duty cycle should expire. @@ -272,9 +253,6 @@ typedef struct st_timer_api fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); /** Stores timer information in p_info. - * @par Implemented as - * - @ref R_GPT_InfoGet() - * - @ref R_AGT_InfoGet() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. * @param[out] p_info Collection of information for this timer. @@ -282,9 +260,6 @@ typedef struct st_timer_api fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); /** Get the current counter value and timer state and store it in p_status. - * @par Implemented as - * - @ref R_GPT_StatusGet() - * - @ref R_AGT_StatusGet() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. * @param[out] p_status Current status of this timer. @@ -292,9 +267,6 @@ typedef struct st_timer_api fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_GPT_CallbackSet() - * - @ref R_AGT_CallbackSet() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. * @param[in] p_callback Callback function to register @@ -302,13 +274,10 @@ typedef struct st_timer_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *), + fsp_err_t (* callbackSet)(timer_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *), void const * const p_context, timer_callback_args_t * const p_callback_memory); /** Allows driver to be reconfigured and may reduce power consumption. - * @par Implemented as - * - @ref R_GPT_Close() - * - @ref R_AGT_Close() * * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. */ diff --git a/ra/fsp/inc/api/r_transfer_api.h b/ra/fsp/inc/api/r_transfer_api.h index 383b828d4..020d0a3d6 100644 --- a/ra/fsp/inc/api/r_transfer_api.h +++ b/ra/fsp/inc/api/r_transfer_api.h @@ -27,9 +27,6 @@ * @section TRANSFER_API_SUMMARY Summary * The transfer interface supports background data transfer (no CPU intervention). * - * Implemented by: - * - @ref DTC - * - @ref DMAC * * @{ **********************************************************************************************************************/ @@ -64,12 +61,11 @@ FSP_HEADER **********************************************************************************************************************/ /** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. - * @par Implemented as - * - dtc_instance_ctrl_t - * - dmac_instance_ctrl_t */ typedef void transfer_ctrl_t; +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + /** Transfer mode describes what will happen when a transfer request occurs. */ typedef enum e_transfer_mode { @@ -98,6 +94,10 @@ typedef enum e_transfer_mode TRANSFER_MODE_REPEAT_BLOCK = 3 } transfer_mode_t; +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + /** Transfer size specifies the size of each individual transfer. * Total transfer length = transfer_size_t * transfer_length_t */ @@ -108,6 +108,10 @@ typedef enum e_transfer_size TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value } transfer_size_t; +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + /** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ typedef enum e_transfer_addr_mode { @@ -124,6 +128,10 @@ typedef enum e_transfer_addr_mode TRANSFER_ADDR_MODE_DECREMENTED = 3 } transfer_addr_mode_t; +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + /** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, * the selected pointer returns to its original value after each transfer. */ @@ -136,6 +144,10 @@ typedef enum e_transfer_repeat_area TRANSFER_REPEAT_AREA_SOURCE = 1 } transfer_repeat_area_t; +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + /** Chain transfer mode options. * @note Only applies for DTC. */ typedef enum e_transfer_chain_mode @@ -150,6 +162,10 @@ typedef enum e_transfer_chain_mode TRANSFER_CHAIN_MODE_END = 3 } transfer_chain_mode_t; +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + /** Interrupt options. */ typedef enum e_transfer_irq { @@ -164,6 +180,8 @@ typedef enum e_transfer_irq TRANSFER_IRQ_EACH = 1 } transfer_irq_t; +#endif + /** Driver specific information. */ typedef struct st_transfer_properties { @@ -173,6 +191,8 @@ typedef struct st_transfer_properties uint32_t transfer_length_remaining; ///< Number of transfers remaining } transfer_properties_t; +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + /** This structure specifies the properties of the transfer. * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. @@ -232,6 +252,8 @@ typedef struct st_transfer_info volatile uint16_t length; } transfer_info_t; +#endif + /** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be * initialized. */ typedef struct st_transfer_cfg @@ -254,9 +276,6 @@ typedef enum e_transfer_start_mode typedef struct st_transfer_api { /** Initial configuration. - * @par Implemented as - * - @ref R_DTC_Open() - * - @ref R_DMAC_Open() * * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure @@ -266,9 +285,6 @@ typedef struct st_transfer_api /** Reconfigure the transfer. * Enable the transfer if p_info is valid. - * @par Implemented as - * - @ref R_DTC_Reconfigure() - * - @ref R_DMAC_Reconfigure() * * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_info Pointer to a new transfer info structure. @@ -277,9 +293,6 @@ typedef struct st_transfer_api /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. * Enable the transfer if p_src, p_dest, and length are valid. - * @par Implemented as - * - @ref R_DTC_Reset() - * - @ref R_DMAC_Reset() * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. @@ -292,32 +305,24 @@ typedef struct st_transfer_api uint16_t const num_transfers); /** Enable transfer. Transfers occur after the activation source event (or when - * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source). - * @par Implemented as - * - @ref R_DTC_Enable() - * - @ref R_DMAC_Enable() + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. */ fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); /** Disable transfer. Transfers do not occur after the activation source event (or when - * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source). + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a * transfer. - * @par Implemented as - * - @ref R_DTC_Disable() - * - @ref R_DMAC_Disable() * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. */ fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); /** Start transfer in software. - * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. * @note Not supported for DTC. - * @par Implemented as - * - @ref R_DMAC_SoftwareStart() * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. * @param[in] mode Select mode from @ref transfer_start_mode_t. @@ -327,18 +332,13 @@ typedef struct st_transfer_api /** Stop transfer in software. The transfer will stop after completion of the current transfer. * @note Not supported for DTC. * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. - * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. - * @par Implemented as - * - @ref R_DMAC_SoftwareStop() + * @warning Only works if no peripheral event is chosen as the DMAC activation source. * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. */ fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); /** Provides information about this transfer. - * @par Implemented as - * - @ref R_DTC_InfoGet() - * - @ref R_DMAC_InfoGet() * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. * @param[out] p_properties Driver specific information. @@ -346,12 +346,21 @@ typedef struct st_transfer_api fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. - * @par Implemented as - * - @ref R_DTC_Close() - * - @ref R_DMAC_Close() + * * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. */ fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); } transfer_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/api/r_uart_api.h b/ra/fsp/inc/api/r_uart_api.h index 779af1e80..818d99f7f 100644 --- a/ra/fsp/inc/api/r_uart_api.h +++ b/ra/fsp/inc/api/r_uart_api.h @@ -32,9 +32,6 @@ * - Hardware resource locking during a transaction * - CTS/RTS hardware flow control support (with an associated IOPORT pin) * - * Implemented by: - * - @ref SCI_UART - * - @ref SCI_B_UART * * @{ **********************************************************************************************************************/ @@ -62,6 +59,7 @@ FSP_HEADER **********************************************************************************************************************/ /** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T typedef enum e_sf_event { UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event @@ -73,6 +71,8 @@ typedef enum e_sf_event UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data } uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T /** UART Data bit length definition */ typedef enum e_uart_data_bits @@ -81,6 +81,8 @@ typedef enum e_uart_data_bits UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit } uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T /** UART Parity definition */ typedef enum e_uart_parity @@ -89,6 +91,7 @@ typedef enum e_uart_parity UART_PARITY_EVEN = 2U, ///< Even parity UART_PARITY_ODD = 3U, ///< Odd parity } uart_parity_t; +#endif /** UART Stop bits definition */ typedef enum e_uart_stop_bits @@ -161,8 +164,6 @@ typedef struct st_uart_cfg } uart_cfg_t; /** UART control block. Allocate an instance specific control block to pass into the UART API calls. - * @par Implemented as - * - sci_uart_instance_ctrl_t */ typedef void uart_ctrl_t; @@ -170,9 +171,6 @@ typedef void uart_ctrl_t; typedef struct st_uart_api { /** Open UART device. - * @par Implemented as - * - @ref R_SCI_UART_Open() - * - @ref R_SCI_B_UART_Open() * * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by @@ -184,9 +182,6 @@ typedef struct st_uart_api * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in * the callback function with event UART_EVENT_RX_CHAR. * The maximum transfer size is reported by infoGet(). - * @par Implemented as - * - @ref R_SCI_UART_Read() - * - @ref R_SCI_B_UART_Read() * * @param[in] p_ctrl Pointer to the UART control block for the channel. * @param[in] p_dest Destination address to read data from. @@ -198,9 +193,6 @@ typedef struct st_uart_api * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), * the callback called with event UART_EVENT_TX_COMPLETE. * The maximum transfer size is reported by infoGet(). - * @par Implemented as - * - @ref R_SCI_UART_Write() - * - @ref R_SCI_B_UART_Write() * * @param[in] p_ctrl Pointer to the UART control block. * @param[in] p_src Source address to write data to. @@ -212,9 +204,6 @@ typedef struct st_uart_api * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud * settings have been applied. * - * @par Implemented as - * - @ref R_SCI_UART_BaudSet() - * - @ref R_SCI_B_UART_BaudSet() * * @param[in] p_ctrl Pointer to the UART control block. * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. @@ -222,9 +211,6 @@ typedef struct st_uart_api fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); /** Get the driver specific information. - * @par Implemented as - * - @ref R_SCI_UART_InfoGet() - * - @ref R_SCI_B_UART_InfoGet() * * @param[in] p_ctrl Pointer to the UART control block. * @param[in] baudrate Baud rate in bps. @@ -233,9 +219,6 @@ typedef struct st_uart_api /** * Abort ongoing transfer. - * @par Implemented as - * - @ref R_SCI_UART_Abort() - * - @ref R_SCI_B_UART_Abort() * * @param[in] p_ctrl Pointer to the UART control block. * @param[in] communication_to_abort Type of abort request. @@ -244,9 +227,6 @@ typedef struct st_uart_api /** * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_SCI_Uart_CallbackSet() - * - R_SCI_B_Uart_CallbackSet() * * @param[in] p_ctrl Pointer to the UART control block. * @param[in] p_callback Callback function @@ -254,25 +234,19 @@ typedef struct st_uart_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *), + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), void const * const p_context, uart_callback_args_t * const p_callback_memory); /** Close UART device. - * @par Implemented as - * - @ref R_SCI_UART_Close() - * - @ref R_SCI_B_UART_Close() * * @param[in] p_ctrl Pointer to the UART control block. */ fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); /** Stop ongoing read and return the number of bytes remaining in the read. - * @par Implemented as - * - @ref R_SCI_UART_ReadStop() - * - @ref R_SCI_B_UART_ReadStop() * - * @param[in] p_ctrl Pointer to the UART control block. - * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. */ fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); } uart_api_t; diff --git a/ra/fsp/inc/api/r_usb_basic_api.h b/ra/fsp/inc/api/r_usb_basic_api.h index c11aa65b2..696aca312 100644 --- a/ra/fsp/inc/api/r_usb_basic_api.h +++ b/ra/fsp/inc/api/r_usb_basic_api.h @@ -26,8 +26,6 @@ * @section USB_API_Summary Summary * The USB interface provides USB functionality. * - * The USB interface can be implemented by: - * - @ref USB * * @{ **********************************************************************************************************************/ @@ -40,7 +38,11 @@ ******************************************************************************/ #include "bsp_api.h" #include "r_transfer_api.h" -#include "../../src/r_usb_basic/src/driver/inc/r_usb_basic_define.h" +#ifndef BSP_OVERRIDE_USB_BASIC_INCLUDE + #include "../../src/r_usb_basic/src/driver/inc/r_usb_basic_define.h" +#else + #include "../../src/r_usb_basic_usod/src/driver/inc/r_usb_basic_define.h" +#endif #if (BSP_CFG_RTOS == 2) #include "FreeRTOS.h" @@ -245,7 +247,8 @@ typedef enum e_usb_class USB_CLASS_HPRN, ///< HPRN Class USB_CLASS_HUVC, ///< HUVC Class USB_CLASS_REQUEST, ///< USB Class Request - USB_CLASS_END ///< USB Class End Code + USB_CLASS_HUB, ///< HUB Class + USB_CLASS_END, ///< USB Class End Code } usb_class_t; /** USB battery charging type */ @@ -307,8 +310,6 @@ typedef enum e_usb_address } usb_address_t; /** USB control block. Allocate an instance specific control block to pass into the USB API calls. - * @par Implemented as - * - usb_instance_ctrl_t */ typedef void usb_ctrl_t; typedef void (usb_compliance_cb_t)(void *); @@ -414,300 +415,239 @@ typedef struct st_usb_cfg void const * p_context; ///< Other Context const transfer_instance_t * p_transfer_tx; ///< Send context const transfer_instance_t * p_transfer_rx; ///< Receive context + void const * p_extend; ///< Pointer to extended configuration by instance of interface. } usb_cfg_t; /** Functions implemented at the HAL layer will follow this API. */ typedef struct st_usb_api { /** Start the USB module - * @par Implemented as - * - @ref R_USB_Open() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. */ - fsp_err_t (* open)(usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_cfg); + fsp_err_t (* open)(usb_ctrl_t * const p_ctrl, usb_cfg_t const * const p_cfg); /** Stop the USB module - * @par Implemented as - * - @ref R_USB_Close() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* close)(usb_ctrl_t * const p_api_ctrl); + fsp_err_t (* close)(usb_ctrl_t * const p_ctrl); /** Request USB data read - * @par Implemented as - * - @ref R_USB_Read() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buf Pointer to area that stores read data. * @param[in] size Read request size. * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. */ - fsp_err_t (* read)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); + fsp_err_t (* read)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); /** Request USB data write - * @par Implemented as - * - @ref R_USB_Write() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buf Pointer to area that stores write data. * @param[in] size Read request size. * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. */ - fsp_err_t (* write)(usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); + fsp_err_t (* write)(usb_ctrl_t * const p_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); /** Stop USB data read/write processing - * @par Implemented as - * - @ref R_USB_Stop() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] direction Receive (USB_TRANSFER_READ) or send (USB_TRANSFER_WRITE). * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. */ - fsp_err_t (* stop)(usb_ctrl_t * const p_api_ctrl, usb_transfer_t direction, uint8_t destination); + fsp_err_t (* stop)(usb_ctrl_t * const p_ctrl, usb_transfer_t direction, uint8_t destination); /** Request suspend - * @par Implemented as - * - @ref R_USB_Suspend() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* suspend)(usb_ctrl_t * const p_api_ctrl); + fsp_err_t (* suspend)(usb_ctrl_t * const p_ctrl); /** Request resume - * @par Implemented as - * - @ref R_USB_Resume() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* resume)(usb_ctrl_t * const p_api_ctrl); + fsp_err_t (* resume)(usb_ctrl_t * const p_ctrl); /** Sets VBUS supply start/stop. - * @par Implemented as - * - @ref R_USB_VbusSet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] state VBUS supply start/stop specification */ - fsp_err_t (* vbusSet)(usb_ctrl_t * const p_api_ctrl, uint16_t state); + fsp_err_t (* vbusSet)(usb_ctrl_t * const p_ctrl, uint16_t state); /** Get information on USB device. - * @par Implemented as - * - @ref R_USB_InfoGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_info Pointer to usb_info_t structure area. * @param[in] destination Device address for Host. */ - fsp_err_t (* infoGet)(usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uint8_t destination); + fsp_err_t (* infoGet)(usb_ctrl_t * const p_ctrl, usb_info_t * p_info, uint8_t destination); /** Request data read from specified pipe - * @par Implemented as - * - @ref R_USB_PipeRead() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buf Pointer to area that stores read data. * @param[in] size Read request size. - * @param[in] pipe_number Pipe Number. + * @param[in] pipe_number Pipe Number. */ - fsp_err_t (* pipeRead)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + fsp_err_t (* pipeRead)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); /** Request data write to specified pipe - * @par Implemented as - * - @ref R_USB_PipeWrite() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buf Pointer to area that stores write data. * @param[in] size Read request size. - * @param[in] pipe_number Pipe Number. + * @param[in] pipe_number Pipe Number. */ - fsp_err_t (* pipeWrite)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + fsp_err_t (* pipeWrite)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); /** Stop USB data read/write processing to specified pipe - * @par Implemented as - * - @ref R_USB_PipeStop() * - * @param[in] p_api_ctrl Pointer to control structure. - * @param[in] pipe_number Pipe Number. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pipe_number Pipe Number. */ - fsp_err_t (* pipeStop)(usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number); + fsp_err_t (* pipeStop)(usb_ctrl_t * const p_ctrl, uint8_t pipe_number); /** Get pipe number - * @par Implemented as - * - @ref R_USB_UsedPipesGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_pipe Pointer to area that stores the selected pipe number (bit map information). * @param[in] destination Device address for Host. */ - fsp_err_t (* usedPipesGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * p_pipe, uint8_t destination); + fsp_err_t (* usedPipesGet)(usb_ctrl_t * const p_ctrl, uint16_t * p_pipe, uint8_t destination); /** Get pipe information - * @par Implemented as - * - @ref R_USB_PipeInfoGet() * - * @param[in] p_api_ctrl Pointer to control structure. - * @param[in] p_info Pointer to usb_pipe_t structure area. - * @param[in] pipe_number Pipe Number. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_pipe_t structure area. + * @param[in] pipe_number Pipe Number. */ - fsp_err_t (* pipeInfoGet)(usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); + fsp_err_t (* pipeInfoGet)(usb_ctrl_t * const p_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); /** Return USB-related completed events (OS less only) - * @par Implemented as - * - @ref R_USB_EventGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[out] event Pointer to event. */ - fsp_err_t (* eventGet)(usb_ctrl_t * const p_api_ctrl, usb_status_t * event); + fsp_err_t (* eventGet)(usb_ctrl_t * const p_ctrl, usb_status_t * event); /** Register a callback function to be called upon completion of a USB related event. (RTOS only) - * @par Implemented as - * - @ref R_USB_Callback() * * @param[in] p_callback Pointer to Callback function. */ fsp_err_t (* callback)(usb_callback_t * p_callback); /** Pull-up enable/disable setting of D+/D- line. - * @par Implemented as - * - @ref R_USB_PullUp() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] state Pull-up enable/disable setting. */ - fsp_err_t (* pullUp)(usb_ctrl_t * const p_api_ctrl, uint8_t state); + fsp_err_t (* pullUp)(usb_ctrl_t * const p_ctrl, uint8_t state); /** Performs settings and transmission processing when transmitting a setup packet. - * @par Implemented as - * - @ref R_USB_HostControlTransfer() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[in] p_setup Setup packet information. * @param[in] p_buf Transfer area information. * @param[in] device_address Device address information. */ - fsp_err_t (* hostControlTransfer)(usb_ctrl_t * const p_api_ctrl, usb_setup_t * p_setup, uint8_t * p_buf, + fsp_err_t (* hostControlTransfer)(usb_ctrl_t * const p_ctrl, usb_setup_t * p_setup, uint8_t * p_buf, uint8_t device_address); /** Receives data sent by control transfer. - * @par Implemented as - * - @ref R_USB_PeriControlDataGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[in] p_buf Data reception area information. * @param[in] size Data reception size information. */ - fsp_err_t (* periControlDataGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + fsp_err_t (* periControlDataGet)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size); /** Performs transfer processing for control transfer. - * @par Implemented as - * - @ref R_USB_PeriControlDataSet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[in] p_buf Area information for data transfer. * @param[in] size Transfer size information. */ - fsp_err_t (* periControlDataSet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + fsp_err_t (* periControlDataSet)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size); /** Set the response to the setup packet. - * @par Implemented as - * - @ref R_USB_PeriControlStatusSet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[in] status USB port startup information. */ - fsp_err_t (* periControlStatusSet)(usb_ctrl_t * const p_api_ctrl, usb_setup_status_t status); + fsp_err_t (* periControlStatusSet)(usb_ctrl_t * const p_ctrl, usb_setup_status_t status); /** Sends a remote wake-up signal to the connected Host. - * @par Implemented as - * - @ref R_USB_RemoteWakeup() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. */ - fsp_err_t (* remoteWakeup)(usb_ctrl_t * const p_api_ctrl); + fsp_err_t (* remoteWakeup)(usb_ctrl_t * const p_ctrl); /** This API gets the module number. - * @par Implemented as - * - @ref R_USB_ModuleNumberGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] module_number Module number to get. */ - fsp_err_t (* moduleNumberGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * module_number); + fsp_err_t (* moduleNumberGet)(usb_ctrl_t * const p_ctrl, uint8_t * module_number); /** This API gets the module number. - * @par Implemented as - * - @ref R_USB_ClassTypeGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] class_type Class type to get. */ - fsp_err_t (* classTypeGet)(usb_ctrl_t * const p_api_ctrl, usb_class_t * class_type); + fsp_err_t (* classTypeGet)(usb_ctrl_t * const p_ctrl, usb_class_t * class_type); /** This API gets the device address. - * @par Implemented as - * - @ref R_USB_DeviceAddressGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] device_address Device address to get. */ - fsp_err_t (* deviceAddressGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * device_address); + fsp_err_t (* deviceAddressGet)(usb_ctrl_t * const p_ctrl, uint8_t * device_address); /** This API gets the pipe number. - * @par Implemented as - * - @ref R_USB_PipeNumberGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] pipe_number Pipe number to get. */ - fsp_err_t (* pipeNumberGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * pipe_number); + fsp_err_t (* pipeNumberGet)(usb_ctrl_t * const p_ctrl, uint8_t * pipe_number); /** This API gets the state of the device. - * @par Implemented as - * - @ref R_USB_DeviceStateGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] state Device state to get. */ - fsp_err_t (* deviceStateGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * state); + fsp_err_t (* deviceStateGet)(usb_ctrl_t * const p_ctrl, uint16_t * state); /** This API gets the data size. - * @par Implemented as - * - @ref R_USB_DataSizeGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] data_size Data size to get. */ - fsp_err_t (* dataSizeGet)(usb_ctrl_t * const p_api_ctrl, uint32_t * data_size); + fsp_err_t (* dataSizeGet)(usb_ctrl_t * const p_ctrl, uint32_t * data_size); /** This API gets the setup type. - * @par Implemented as - * - @ref R_USB_SetupGet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[out] setup Setup type to get. */ - fsp_err_t (* setupGet)(usb_ctrl_t * const p_api_ctrl, usb_setup_t * setup); + fsp_err_t (* setupGet)(usb_ctrl_t * const p_ctrl, usb_setup_t * setup); /** This API sets the callback function for OTG. - * @par Implemented as - * - @ref R_USB_OtgCallbackSet() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. * @param[in] p_callback Pointer to the callback function for OTG. */ - fsp_err_t (* otgCallbackSet)(usb_ctrl_t * const p_api_ctrl, usb_otg_callback_t * p_callback); + fsp_err_t (* otgCallbackSet)(usb_ctrl_t * const p_ctrl, usb_otg_callback_t * p_callback); /** This API starts SRP processing for OTG. - * @par Implemented as - * - @ref R_USB_OtgSRP() * - * @param[in] p_api_ctrl USB control structure. + * @param[in] p_ctrl USB control structure. */ - fsp_err_t (* otgSRP)(usb_ctrl_t * const p_api_ctrl); + fsp_err_t (* otgSRP)(usb_ctrl_t * const p_ctrl); } usb_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ @@ -724,5 +664,5 @@ FSP_FOOTER #endif /* R_USB_API_H */ /*******************************************************************************************************************//** - * @} (end addtogroup USB_API) + * @} (end defgroup USB_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_hcdc_api.h b/ra/fsp/inc/api/r_usb_hcdc_api.h index ce9655a03..b578a56d8 100644 --- a/ra/fsp/inc/api/r_usb_hcdc_api.h +++ b/ra/fsp/inc/api/r_usb_hcdc_api.h @@ -26,8 +26,6 @@ * @section USB_HCDC_API_Summary Summary * The USB HCDC interface provides USB HCDC functionality. * - * The USB HCDC interface can be implemented by: - * - @ref USB_HCDC * * @{ **********************************************************************************************************************/ @@ -38,11 +36,12 @@ /****************************************************************************** * Includes , "Project Includes" ******************************************************************************/ - #include "r_usb_hcdc_cfg.h" +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_usb_hcdc_cfg.h" - #ifdef __cplusplus -extern "C" { - #endif +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER /****************************************************************************** * Macro definitions @@ -192,9 +191,57 @@ typedef struct uint16_t wtime_ms; ///< Duration of Break } usb_hcdc_breakduration_t; - #ifdef __cplusplus -} - #endif +/** Break duration data */ +typedef struct +{ + uint16_t vendor_id; ///< Vendor ID + uint16_t product_id; ///< Product ID + uint8_t subclass; ///< Subclass code +} usb_hcdc_device_info_t; + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** USB HCDC functions implemented at the HAL layer will follow this API. */ +typedef struct st_usb_hcdc_api +{ + /** Read Control Data (CDC Interrupt IN data) + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores read data. + * @param[in] size Read request size. + * @param[in] device_address Device address. + */ + fsp_err_t (* controlDataRead)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t device_address); + + /** Register the specified vendor class device in the device table. + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] vendor_id Vendor ID. + * @param[in] product_id Product ID. + */ + fsp_err_t (* deviceRegister)(usb_ctrl_t * const p_api_ctrl, uint16_t vendor_id, uint16_t product_id); + + /** Get connected device information. + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_info Pointer to store CDC device information. + * @param[in] device_address Device address. + */ + fsp_err_t (* infoGet)(usb_ctrl_t * const p_api_ctrl, usb_hcdc_device_info_t * p_info, uint8_t device_address); +} usb_hcdc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_usb_hcdc_instance +{ + usb_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + usb_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + usb_hcdc_api_t const * p_api; ///< Pointer to the API structure for this instance +} usb_hcdc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER #endif /* R_USB_HCDC_API_H */ diff --git a/ra/fsp/inc/api/r_usb_hhid_api.h b/ra/fsp/inc/api/r_usb_hhid_api.h index 0dacb197e..39a133ea4 100644 --- a/ra/fsp/inc/api/r_usb_hhid_api.h +++ b/ra/fsp/inc/api/r_usb_hhid_api.h @@ -26,8 +26,6 @@ * @section USB_HHID_API_Summary Summary * The USB HHID interface provides USB HHID functionality. * - * The USB HHID interface can be implemented by: - * - @ref USB_HHID * * @{ **********************************************************************************************************************/ @@ -79,27 +77,23 @@ FSP_HEADER typedef struct st_usb_hhid_api { /** Get HID protocol.(USB Mouse/USB Keyboard/Other Type.) - * @par Implemented as - * - @ref R_USB_HHID_TypeGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_type Pointer to store HID protocol value. * @param[in] device_address Device Address. */ - fsp_err_t (* typeGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_type, uint8_t device_address); + fsp_err_t (* typeGet)(usb_ctrl_t * const p_ctrl, uint8_t * p_type, uint8_t device_address); /** Obtains max packet size for the connected HID device. * The max packet size is set to the area. * Set the direction (USB_HID_IN/USB_HID_OUT). - * @par Implemented as - * - @ref R_USB_HHID_MaxPacketSizeGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_size Pointer to the area to store the max package size. * @param[in] direction Transfer direction. * @param[in] device_address Device Address. */ - fsp_err_t (* maxPacketSizeGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * p_size, uint8_t direction, + fsp_err_t (* maxPacketSizeGet)(usb_ctrl_t * const p_ctrl, uint16_t * p_size, uint8_t direction, uint8_t device_address); } usb_hhid_api_t; @@ -117,5 +111,5 @@ FSP_FOOTER #endif /* USB_HHID_API_H */ /*******************************************************************************************************************//** - * @} (end addtogroup USB_HHID_API) + * @} (end defgroup USB_HHID_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_hmsc_api.h b/ra/fsp/inc/api/r_usb_hmsc_api.h index 2b3c22ab5..13e35d466 100644 --- a/ra/fsp/inc/api/r_usb_hmsc_api.h +++ b/ra/fsp/inc/api/r_usb_hmsc_api.h @@ -26,8 +26,6 @@ * @section USB_HMSC_API_Summary Summary * The USB HMSC interface provides USB HMSC functionality. * - * The USB HMSC interface can be implemented by: - * - @ref USB_HMSC * * @{ **********************************************************************************************************************/ @@ -86,29 +84,23 @@ typedef enum e_usb_csw_result typedef struct st_usb_hmsc_api { /** Processing for MassStorage(ATAPI) command. - * @par Implemented as - * - @ref R_USB_HMSC_StorageCommand() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] *buf Pointer to the buffer area to store the transfer data. * @param[in] command ATAPI command. * @param[in] destination Represents a device address. */ - fsp_err_t (* storageCommand)(usb_ctrl_t * const p_api_ctrl, uint8_t * buf, uint8_t command, uint8_t destination); + fsp_err_t (* storageCommand)(usb_ctrl_t * const p_ctrl, uint8_t * buf, uint8_t command, uint8_t destination); /** Get number of Storage drive. - * @par Implemented as - * - @ref R_USB_HMSC_DriveNumberGet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[out] p_drive Store address for Drive No. * @param[in] destination Represents a device address. */ - fsp_err_t (* driveNumberGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_drive, uint8_t destination); + fsp_err_t (* driveNumberGet)(usb_ctrl_t * const p_ctrl, uint8_t * p_drive, uint8_t destination); /** Read sector information. - * @par Implemented as - * - @ref R_USB_HMSC_StorageReadSector() * * @param[in] drive_number Drive number. * @param[out] *buff Pointer to the buffer area to store the transfer data. @@ -119,8 +111,6 @@ typedef struct st_usb_hmsc_api uint16_t sector_count); /** Write sector information. - * @par Implemented as - * - @ref R_USB_HMSC_StorageWriteSector() * * @param[in] drive_number Drive number. * @param[in] *buff Pointer to the buffer area to store the transfer data. @@ -131,15 +121,11 @@ typedef struct st_usb_hmsc_api uint16_t sector_count); /** Get Semaphore. - * @par Implemented as - * - @ref R_USB_HMSC_SemaphoreGet() * */ fsp_err_t (* semaphoreGet)(void); /** Release Semaphore. - * @par Implemented as - * - @ref R_USB_HMSC_SemaphoreRelease() * */ fsp_err_t (* semaphoreRelease)(void); @@ -151,5 +137,5 @@ FSP_FOOTER #endif /* R_USB_HMSC_API_H */ /*******************************************************************************************************************//** - * @} (end addtogroup USB_HMSC_API) + * @} (end defgroup USB_HMSC_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_pcdc_api.h b/ra/fsp/inc/api/r_usb_pcdc_api.h index c70ec1104..92e7312cd 100644 --- a/ra/fsp/inc/api/r_usb_pcdc_api.h +++ b/ra/fsp/inc/api/r_usb_pcdc_api.h @@ -26,8 +26,6 @@ * @section USB_PCDC_API_Summary Summary * The USB PCDC interface provides USB PCDC functionality. * - * The USB PCDC interface can be implemented by: - * - @ref USB_PCDC * * @{ **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_phid_api.h b/ra/fsp/inc/api/r_usb_phid_api.h index 6f99bf594..40a04f585 100644 --- a/ra/fsp/inc/api/r_usb_phid_api.h +++ b/ra/fsp/inc/api/r_usb_phid_api.h @@ -26,8 +26,6 @@ * @section USB_PHID_API_Summary Summary * The USB interface provides USB functionality. * - * The USB PHID interface can be implemented by: - * - @ref USB_PHID * * @{ **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_pmsc_api.h b/ra/fsp/inc/api/r_usb_pmsc_api.h index e95fd1f78..1bd2012d5 100644 --- a/ra/fsp/inc/api/r_usb_pmsc_api.h +++ b/ra/fsp/inc/api/r_usb_pmsc_api.h @@ -26,8 +26,6 @@ * @section USB_PMSC_API_Summary Summary * The USB PMSC interface provides USB PMSC functionality. * - * The USB PMSC interface can be implemented by: - * - @ref USB_PMSC * * @{ **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_usb_pprn_api.h b/ra/fsp/inc/api/r_usb_pprn_api.h index 705e0285d..4158c9a64 100644 --- a/ra/fsp/inc/api/r_usb_pprn_api.h +++ b/ra/fsp/inc/api/r_usb_pprn_api.h @@ -26,8 +26,6 @@ * @section USB_PPRN_API_Summary Summary * The USB PPRN interface provides USB PPRN functionality. * - * The USB PPRN interface can be implemented by: - * - @ref USBX * * @{ **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/r_wdt_api.h b/ra/fsp/inc/api/r_wdt_api.h index 0b8b58af1..bf4cd8bd4 100644 --- a/ra/fsp/inc/api/r_wdt_api.h +++ b/ra/fsp/inc/api/r_wdt_api.h @@ -27,9 +27,6 @@ * The WDT interface for the Watchdog Timer (WDT) peripheral provides watchdog functionality including resetting the * device or generating an interrupt. * - * The watchdog timer interface can be implemented by: - * - @ref WDT - * - @ref IWDT * * @{ **********************************************************************************************************************/ @@ -54,6 +51,7 @@ FSP_HEADER /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_WDT_TIMEOUT_T /** WDT time-out periods. */ typedef enum e_wdt_timeout @@ -66,6 +64,9 @@ typedef enum e_wdt_timeout WDT_TIMEOUT_8192, ///< 8192 clock cycles WDT_TIMEOUT_16384, ///< 16384 clock cycles } wdt_timeout_t; +#endif + +#ifndef BSP_OVERRIDE_WDT_CLOCK_DIVISION_T /** WDT clock division ratio. */ typedef enum e_wdt_clock_division @@ -81,6 +82,7 @@ typedef enum e_wdt_clock_division WDT_CLOCK_DIVISION_2048 = 7, ///< CLK/2048 WDT_CLOCK_DIVISION_8192 = 8, ///< CLK/8192 } wdt_clock_division_t; +#endif /** WDT refresh permitted period window start position. */ typedef enum e_wdt_window_start @@ -103,7 +105,7 @@ typedef enum e_wdt_window_end /** WDT Counter underflow and refresh error control. */ typedef enum e_wdt_reset_control { - WDT_RESET_CONTROL_NMI = 0, ///< NMI request when counter underflows. + WDT_RESET_CONTROL_NMI = 0, ///< NMI/IRQ request when counter underflows. WDT_RESET_CONTROL_RESET = 1, ///< Reset request when counter underflows. } wdt_reset_control_t; @@ -118,9 +120,10 @@ typedef enum e_wdt_stop_control typedef enum e_wdt_status { WDT_STATUS_NO_ERROR = 0, ///< No status flags set. - WDT_STATUS_UNDERFLOW_ERROR = 1, ///< Underflow flag set. + WDT_STATUS_UNDERFLOW = 1, ///< Underflow flag set. WDT_STATUS_REFRESH_ERROR = 2, ///< Refresh error flag set. Refresh outside of permitted window. WDT_STATUS_UNDERFLOW_AND_REFRESH_ERROR = 3, ///< Underflow and refresh error flags set. + WDT_STATUS_OVERFLOW = 4, ///< Overflow flag set. } wdt_status_t; /** Callback function parameter data */ @@ -137,9 +140,6 @@ typedef struct st_wdt_timeout_values } wdt_timeout_values_t; /** WDT control block. Allocate an instance specific control block to pass into the WDT API calls. - * @par Implemented as - * - wdt_instance_ctrl_t - * - iwdt_instance_ctrl_t */ typedef void wdt_ctrl_t; @@ -150,9 +150,9 @@ typedef struct st_wdt_cfg wdt_clock_division_t clock_division; ///< Clock divider. wdt_window_start_t window_start; ///< Refresh permitted window start position. wdt_window_end_t window_end; ///< Refresh permitted window end position. - wdt_reset_control_t reset_control; ///< Select NMI or reset generated on underflow. + wdt_reset_control_t reset_control; ///< Select NMI/IRQ or reset generated on underflow. wdt_stop_control_t stop_control; ///< Select whether counter operates in sleep mode. - void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT NMI ISR occurs. + void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT ISR occurs. /** Placeholder for user data. Passed to the user callback in wdt_callback_args_t. */ void const * p_context; @@ -162,10 +162,8 @@ typedef struct st_wdt_cfg /** WDT functions implemented at the HAL layer will follow this API. */ typedef struct st_wdt_api { - /** Initialize the WDT in register start mode. In auto-start mode with NMI output it registers the NMI callback. - * @par Implemented as - * - @ref R_WDT_Open() - * - @ref R_IWDT_Open() + /** Initialize the WDT in register start mode. In auto-start mode (Supported devices only) with NMI output it + * registers the NMI callback. * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -173,18 +171,12 @@ typedef struct st_wdt_api fsp_err_t (* open)(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); /** Refresh the watchdog timer. - * @par Implemented as - * - @ref R_WDT_Refresh() - * - @ref R_IWDT_Refresh() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* refresh)(wdt_ctrl_t * const p_ctrl); /** Read the status of the WDT. - * @par Implemented as - * - @ref R_WDT_StatusGet() - * - @ref R_IWDT_StatusGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_status Pointer to variable to return status information through. @@ -192,9 +184,6 @@ typedef struct st_wdt_api fsp_err_t (* statusGet)(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); /** Clear the status flags of the WDT. - * @par Implemented as - * - @ref R_WDT_StatusClear() - * - @ref R_IWDT_StatusClear() * * @param[in] p_ctrl Pointer to control structure. * @param[in] status Status condition(s) to clear. @@ -202,9 +191,6 @@ typedef struct st_wdt_api fsp_err_t (* statusClear)(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); /** Read the current WDT counter value. - * @par Implemented as - * - @ref R_WDT_CounterGet() - * - @ref R_IWDT_CounterGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_count Pointer to variable to return current WDT counter value. @@ -212,9 +198,6 @@ typedef struct st_wdt_api fsp_err_t (* counterGet)(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); /** Read the watchdog timeout values. - * @par Implemented as - * - @ref R_WDT_TimeoutGet() - * - @ref R_IWDT_TimeoutGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_timeout Pointer to structure to return timeout values. @@ -222,16 +205,14 @@ typedef struct st_wdt_api fsp_err_t (* timeoutGet)(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref R_WDT_CallbackSet() * * @param[in] p_ctrl Pointer to the WDT control block. * @param[in] p_callback Callback function * @param[in] p_context Pointer to send to callback function - * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_api_ctrl, void (* p_callback)(wdt_callback_args_t *), + fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_ctrl, void (* p_callback)(wdt_callback_args_t *), void const * const p_context, wdt_callback_args_t * const p_callback_memory); } wdt_api_t; @@ -249,5 +230,5 @@ FSP_FOOTER #endif /*******************************************************************************************************************//** - * @} (end addtogroup WDT_API) + * @} (end defgroup WDT_API) **********************************************************************************************************************/ diff --git a/ra/fsp/inc/api/rm_adpcm_decoder_api.h b/ra/fsp/inc/api/rm_adpcm_decoder_api.h index 898be313b..235999935 100644 --- a/ra/fsp/inc/api/rm_adpcm_decoder_api.h +++ b/ra/fsp/inc/api/rm_adpcm_decoder_api.h @@ -29,8 +29,6 @@ * @section RM_ADPCM_DECODER_API_SUMMARY Summary * The ADPCM decoder interface provides functionality to decode the 4bit ADPCM data to 16bit PCM output. * - * Implemented by: - * @ref RM_ADPCM_DECODER * * @{ **********************************************************************************************************************/ @@ -60,8 +58,6 @@ typedef struct st_adpcm_decoder_cfg } adpcm_decoder_cfg_t; /** Audio Decoder control block. Allocate an instance specific control block to pass into the Audio Decoder API calls. - * @par Implemented as - * - @ref adpcm_decoder_instance_ctrl_t */ typedef void adpcm_decoder_ctrl_t; @@ -69,8 +65,6 @@ typedef void adpcm_decoder_ctrl_t; typedef struct st_adpcm_decoder_api { /** Initialize Audio Decoder device. - * @par Implemented as - * - @ref RM_ADPCM_DECODER_Open() * * @note To reconfigure after calling this function, call @ref adpcm_decoder_api_t::close first. * @param[in] p_ctrl Pointer to control handle structure @@ -79,8 +73,6 @@ typedef struct st_adpcm_decoder_api fsp_err_t (* open)(adpcm_decoder_ctrl_t * const p_ctrl, adpcm_decoder_cfg_t const * const p_cfg); /** Decodes the compressed data and stores it in output buffer. - * @par Implemented as - * - @ref RM_ADPCM_DECODER_Decode() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] p_src Pointer to a source data buffer from which data will be picked up for decode operation. @@ -93,8 +85,6 @@ typedef struct st_adpcm_decoder_api uint32_t src_len_bytes); /** Resets the ADPCM driver. - * @par Implemented as - * - @ref RM_ADPCM_DECODER_Reset() * * @param[in] p_ctrl Pointer to control handle structure * @@ -102,8 +92,6 @@ typedef struct st_adpcm_decoder_api fsp_err_t (* reset)(adpcm_decoder_ctrl_t * const p_ctrl); /** Close the specified Audio decoder modules. - * @par Implemented as - * - @ref RM_ADPCM_DECODER_Close() * * @param[in] p_ctrl Pointer to control handle structure */ diff --git a/ra/fsp/inc/api/rm_audio_playback_api.h b/ra/fsp/inc/api/rm_audio_playback_api.h index 736695dfa..0c2cccc53 100644 --- a/ra/fsp/inc/api/rm_audio_playback_api.h +++ b/ra/fsp/inc/api/rm_audio_playback_api.h @@ -29,8 +29,6 @@ * @section AUDIO_PLAYBACK_API_SUMMARY Summary * @brief This module provides common interface for Audio Playback. * - * Implemented by: - * @ref RM_AUDIO_PLAYBACK_PWM * * @{ **********************************************************************************************************************/ @@ -74,8 +72,6 @@ typedef struct st_audio_playback_callback_args } audio_playback_callback_args_t; /** Audio Playback control block. Allocate an instance specific control block to pass into the AUDIO_PLAYBACK API calls. - * @par Implemented as - * - audio_playback_pwm_instance_ctrl_t */ typedef void audio_playback_ctrl_t; @@ -95,8 +91,6 @@ typedef struct st_audio_playback_cfg typedef struct st_audio_playback_api { /** Open a audio playback module. - * @par Implemented as - * - RM_AUDIO_PLAYBACK_PWM_Open() * * @param[in] p_ctrl Pointer to memory allocated for control block. * @param[in] p_cfg Pointer to the hardware configurations. @@ -104,24 +98,18 @@ typedef struct st_audio_playback_api fsp_err_t (* open)(audio_playback_ctrl_t * const p_ctrl, audio_playback_cfg_t const * const p_cfg); /** Start audio playback hardware. - * @par Implemented as - * - RM_AUDIO_PLAYBACK_PWM_Start() * * @param[in] p_ctrl Pointer to control block. */ fsp_err_t (* start)(audio_playback_ctrl_t * const p_ctrl); /** Stop audio playback hardware. - * @par Implemented as - * - RM_AUDIO_PLAYBACK_PWM_Stop() * * @param[in] p_ctrl Pointer to control block. */ fsp_err_t (* stop)(audio_playback_ctrl_t * const p_ctrl); /** Play audio buffer. - * @par Implemented as - * - RM_AUDIO_PLAYBACK_PWM_Play() * * @param[in] p_ctrl Pointer to control block. * @param[in] p_buffer Pointer to buffer with PCM samples to play. Data must be scaled for audio @@ -131,8 +119,6 @@ typedef struct st_audio_playback_api fsp_err_t (* play)(audio_playback_ctrl_t * const p_ctrl, void const * const p_buffer, uint32_t length); /** Close the audio driver. - * @par Implemented as - * - RM_AUDIO_PLAYBACK_PWM_Close() * * @param[in] p_ctrl Pointer to control block initialized in audio_playback_api_t::open. */ diff --git a/ra/fsp/inc/api/rm_ble_abs_api.h b/ra/fsp/inc/api/rm_ble_abs_api.h index 17bc04394..23ecf4c4c 100644 --- a/ra/fsp/inc/api/rm_ble_abs_api.h +++ b/ra/fsp/inc/api/rm_ble_abs_api.h @@ -29,8 +29,6 @@ * @section BLE_ABS_API_Summary Summary * The BLE ABS interface for the Bluetooth Low Energy Abstraction (BLE ABS) peripheral provides Bluetooth Low Energy Abstraction functionality. * - * The Bluetooth Low Energy Abstraction interface can be implemented by: - * - @ref BLE_ABS * * @{ **********************************************************************************************************************/ @@ -42,14 +40,18 @@ /* Register definitions, common services and error codes. */ #include "bsp_api.h" #include "r_ble_api.h" - -#if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE) - #include "r_uart_api.h" - #include "r_spi_api.h" - #include "r_external_irq_api.h" +#ifndef BSP_OVERRIDE_BLE_ABS_INCLUDE + #if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE) + #include "r_uart_api.h" + #include "r_spi_api.h" + #include "r_external_irq_api.h" + #else + #include "r_flash_api.h" + #include "r_timer_api.h" + #endif #else - #include "r_flash_api.h" #include "r_timer_api.h" + #include "r_spi_flash_api.h" #endif #include "fsp_common_api.h" @@ -168,8 +170,6 @@ typedef struct st_ble_abs_callback_args } ble_abs_callback_args_t; /** BLE ABS control block. Allocate an instance specific control block to pass into the BLE ABS API calls. - * @par Implemented as - * - ble_abs_instance_ctrl_t */ typedef void ble_abs_ctrl_t; @@ -785,14 +785,18 @@ typedef struct st_ble_abs_cfg ble_abs_gatt_client_callback_set_t * p_gatt_client_callback_list; ///< GATT Client callback set. uint8_t gatt_client_callback_list_number; ///< The number of GATT Client callback functions. ble_abs_pairing_parameter_t * p_pairing_parameter; ///< Pairing parameters. - -#if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE) +#ifndef BSP_OVERRIDE_BLE_ABS_INCLUDE + #if defined(BLE_CFG_RYZ012_DEVICE) || defined(BLE_CFG_DA14xxx_DEVICE) const uart_instance_t * p_uart_instance; ///< SCI UART instance const spi_instance_t * p_spi_instance; ///< SPI instance const external_irq_instance_t * p_irq_instance; ///< IRQ instance -#else + #else flash_instance_t const * p_flash_instance; ///< Pointer to flash instance. timer_instance_t const * p_timer_instance; ///< Pointer to timer instance. + #endif +#else + spi_flash_instance_t const * p_flash_instance; ///< Pointer to flash instance. + timer_instance_t const * p_timer_instance; ///< Pointer to timer instance. #endif void (* p_callback)(ble_abs_callback_args_t * p_args); ///< Callback provided when a BLE ISR occurs. @@ -804,8 +808,6 @@ typedef struct st_ble_abs_cfg typedef struct st_ble_abs_api { /** Initialize the BLE ABS in register start mode. - * @par Implemented as - * - RM_BLE_ABS_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -813,16 +815,12 @@ typedef struct st_ble_abs_api fsp_err_t (* open)(ble_abs_ctrl_t * const p_ctrl, ble_abs_cfg_t const * const p_cfg); /** Close the BLE ABS. - * @par Implemented as - * - RM_BLE_ABS_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(ble_abs_ctrl_t * const p_ctrl); /** Close the BLE ABS. - * @par Implemented as - * - RM_BLE_ABS_Reset() * * @param[in] p_ctrl Pointer to control structure. * @param[in] init_callback callback function to initialize Host Stack. @@ -830,8 +828,6 @@ typedef struct st_ble_abs_api fsp_err_t (* reset)(ble_abs_ctrl_t * const p_ctrl, ble_event_cb_t init_callback); /** Start Legacy Connectable Advertising. - * @par Implemented as - * - RM_BLE_ABS_StartLegacyAdvertising() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_advertising_parameter Pointer to Advertising parameters for Legacy Advertising. */ @@ -839,8 +835,6 @@ typedef struct st_ble_abs_api ble_abs_legacy_advertising_parameter_t const * const p_advertising_parameter); /** Start Extended Connectable Advertising. - * @par Implemented as - * - RM_BLE_ABS_StartExtendedAdvertising() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_advertising_parameter Pointer to Advertising parameters for extend Advertising. */ @@ -848,8 +842,6 @@ typedef struct st_ble_abs_api ble_abs_extend_advertising_parameter_t const * const p_advertising_parameter); /** Start Non-Connectable Advertising. - * @par Implemented as - * - RM_BLE_ABS_StartNonConnectableAdvertising() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_advertising_parameter Pointer to Advertising parameters for non-connectable Advertising. */ @@ -858,8 +850,6 @@ typedef struct st_ble_abs_api p_advertising_parameter); /** Start Periodic Advertising. - * @par Implemented as - * - RM_BLE_ABS_StartPeriodicAdvertising() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_advertising_parameter Pointer to Advertising parameters for periodic Advertising. */ @@ -868,16 +858,12 @@ typedef struct st_ble_abs_api p_advertising_parameter); /** Start scanning. - * @par Implemented as - * - RM_BLE_ABS_StartScanning() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_scan_parameter Pointer to scan parameter. */ fsp_err_t (* startScanning)(ble_abs_ctrl_t * const p_ctrl, ble_abs_scan_parameter_t const * const p_scan_parameter); /** Request create connection. - * @par Implemented as - * - RM_BLE_ABS_CreateConnection() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_connection_parameter Pointer to connection parameter. */ @@ -885,8 +871,6 @@ typedef struct st_ble_abs_api ble_abs_connection_parameter_t const * const p_connection_parameter); /** Configure local device privacy. - * @par Implemented as - * - RM_BLE_ABS_SetLocalPrivacy() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_lc_irk Pointer to IRK (Identity Resolving Key) to be registered in the resolving list. * @param[in] privacy_mode privacy_mode privacy mode. @@ -894,16 +878,12 @@ typedef struct st_ble_abs_api fsp_err_t (* setLocalPrivacy)(ble_abs_ctrl_t * const p_ctrl, uint8_t const * const p_lc_irk, uint8_t privacy_mode); /** Start pairing or encryption. - * @par Implemented as - * - RM_BLE_ABS_StartAuthentication() * @param[in] p_ctrl Pointer to control structure. * @param[in] connection_handle Connection handle identifying the remote device. */ fsp_err_t (* startAuthentication)(ble_abs_ctrl_t * const p_ctrl, uint16_t connection_handle); /** Delete bond information. - * @par Implemented as - * - RM_BLE_ABS_DeleteBondInformation() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_bond_information_parameter Pointer to bond information parameter. */ @@ -911,8 +891,6 @@ typedef struct st_ble_abs_api ble_abs_bond_information_parameter_t const * const p_bond_information_parameter); /** Import local identity address, keys information to local storage. - * @par Implemented as - * - RM_BLE_ABS_ImportKeyInformation() * @param[in] p_ctrl Pointer to control structure. * @param[in] p_local_identity_address Pointer to local identiry address. * @param[in] uint8_t p_local_irk Pointer to local IRK (Identity Resolving Key) @@ -922,8 +900,6 @@ typedef struct st_ble_abs_api uint8_t * p_local_irk, uint8_t * p_local_csrk); /** Export local identity address, keys information from local storage. - * @par Implemented as - * - RM_BLE_ABS_ExportKeyInformation() * @param[in] p_ctrl Pointer to control structure. * @param[out] p_local_identity_address Pointer to local identiry address. * @param[out] uint8_t p_local_irk Pointer to local IRK (Identity Resolving Key) diff --git a/ra/fsp/inc/api/rm_ble_mesh_access_api.h b/ra/fsp/inc/api/rm_ble_mesh_access_api.h index 1e9943be7..9293e7f8e 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_access_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_access_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_ACCESS_API_Summary Summary * The BLE Mesh Access interface for the Bluetooth Low Energy Mesh Network Access (BLE MESH ACCESS) peripheral provides Bluetooth Low Energy Mesh Network Access functionality. * - * The Bluetooth Low Energy Mesh Network Access interface can be implemented by: - * - @ref RM_BLE_MESH_ACCESS * * @{ **********************************************************************************************************************/ @@ -1497,8 +1495,6 @@ typedef struct st_rm_ble_mesh_access_friend_security_credential_info } rm_ble_mesh_access_friend_security_credential_info_t; /** BLE MESH ACCESS control block. Allocate an instance specific control block to pass into the BLE MESH ACCESS API calls. - * @par Implemented as - * - rm_ble_mesh_access_instance_ctrl_t */ typedef void rm_ble_mesh_access_ctrl_t; @@ -1520,8 +1516,6 @@ typedef struct st_rm_ble_mesh_access_cfg typedef struct st_rm_ble_mesh_access_api { /** Open access middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -1529,16 +1523,12 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* open)(rm_ble_mesh_access_ctrl_t * const p_ctrl, rm_ble_mesh_access_cfg_t const * const p_cfg); /** Close access middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_access_ctrl_t * const p_ctrl); /** Register a model with the access layer. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_RegisterModel() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_model Pointer to model structure. @@ -1549,8 +1539,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_model_handle_t * const p_model_handle); /** Get element handle. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetElementHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] elem_addr Address of the corresponding element. @@ -1560,8 +1548,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_element_handle_t * const p_handle); /** Get element handle for a given model handle - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetElementHandleForModelHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Model handle. @@ -1572,8 +1558,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_element_handle_t * const p_elem_handle); /** Get model handle. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetModelHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] elem_handle Element identifier associated with the Model. @@ -1586,8 +1570,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_model_handle_t * const p_handle); /** API to publish access layer message. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_Publish() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_handl Pointer to model handle. @@ -1599,8 +1581,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_req_msg_raw_t const * const p_publish_message, uint8_t reliable); /** API to reliably publish access layer message. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_ReliablePublish() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_handl Pointer to model handle. @@ -1613,8 +1593,6 @@ typedef struct st_rm_ble_mesh_access_api uint32_t rsp_opcode); /** API to reply to access layer message. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_Reply() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_req_msg_context Pointer to context of received message structure. @@ -1626,8 +1604,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_req_msg_raw_t const * const p_req_msg_raw); /** API to reply to access layer message and optionally also to publish. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_ReplyAndPublish() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_req_msg_context Pointer to context of received message structure. @@ -1640,8 +1616,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_publish_setting_t const * const p_publish_setting); /** API to send access PDUs. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SendPdu() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_pdu Pointer to PDU structure. @@ -1651,8 +1625,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t reliable); /** Get composition data. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetCompositionData() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_buffer Pointer to buffer structure. @@ -1660,16 +1632,12 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getCompositionData)(rm_ble_mesh_access_ctrl_t * const p_ctrl, rm_ble_mesh_buffer_t * const p_buffer); /** To reset a node. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(rm_ble_mesh_access_ctrl_t * const p_ctrl); /** To get the number of elements in local node. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetElementCount() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_count Pointer to number of elements. @@ -1677,8 +1645,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getElementCount)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t * const p_count); /** To set primary unicast address. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetPrimaryUnicastAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr Primary Unicast address to be set. @@ -1687,8 +1653,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_address_t addr); /** To get primary unicast address. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetPrimaryUnicastAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_addr Pointer to address. @@ -1697,8 +1661,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_address_t * const p_addr); /** To set default TTL. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetDefaultTtl() * * @param[in] p_ctrl Pointer to control structure. * @param[in] ttl Default TTL to be set. @@ -1706,8 +1668,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* setDefaultTtl)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t ttl); /** To get default TTL. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetDefaultTtl() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_ttl Pointer to TTL. @@ -1715,8 +1675,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getDefaultTtl)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t const * const p_ttl); /** To set IV Index. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetIvIndex() * * @param[in] p_ctrl Pointer to control structure. * @param[in] iv_index IV index to be set. @@ -1725,8 +1683,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* setIvIndex)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint32_t iv_index, uint8_t iv_update_flag); /** To get IV Index. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetIvIndex() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_iv_index Pointer to index. @@ -1736,8 +1692,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t * const p_iv_update_flag); /** To get IV Index by IVI. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetIvIndexByIvi() * * @param[in] p_ctrl Pointer to control structure. * @param[in] ivi Least significant bit of the IV index used in the once to authenticate and encrypt the network PDU. @@ -1746,8 +1700,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getIvIndexByIvi)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t ivi, uint32_t * const p_iv_index); /** To enable/disable a feature. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetFeaturesField() * * @param[in] p_ctrl Pointer to control structure. * @param[in] enable Enable or Disable. @@ -1756,8 +1708,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* setFeaturesField)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t enable, uint8_t feature); /** To get state of a feature. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetFeaturesField() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_enable Pointer to enable. @@ -1766,8 +1716,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getFeaturesField)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t * const p_enable, uint8_t feature); /** To get state of all features. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetFeatures() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_features Pointer to features. @@ -1775,8 +1723,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getFeatures)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t * const p_features); /** To get friendship role of the node. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetFriendshipRole() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_friend_role Pointer to friend role. @@ -1784,8 +1730,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* getFriendshipRole)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t * const p_friend_role); /** To set friendship role of the node. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetFriendshipRole() * * @param[in] p_ctrl Pointer to control structure. * @param[out] friend_role Friend role. @@ -1793,8 +1737,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* setFriendshipRole)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t friend_role); /** To add Device Key. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_AddDeviceKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_dev_key Pointer to device Key. @@ -1805,8 +1747,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_address_t uaddr, uint8_t num_elements); /** To get Device Key. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetDeviceKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] dev_key_index Device key index. @@ -1816,16 +1756,12 @@ typedef struct st_rm_ble_mesh_access_api uint8_t ** const p_dev_key); /** To remove all Device Keys. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_RemoveAllDeviceKeys() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* removeAllDeviceKeys)(rm_ble_mesh_access_ctrl_t * const p_ctrl); /** To get list of Provisioned Device List. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetProvisionedDeviceList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_prov_dev_list Pointer to provisioned device list structure. @@ -1836,8 +1772,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_num_entries); /** To get Device Key Handle. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetDeviceKeyHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] prim_elem_uaddr Primary element address to be searched. @@ -1848,8 +1782,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_device_key_handle_t * const p_handle); /** To get AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] appkey_handle AppKey Handle. @@ -1860,8 +1792,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t ** const p_app_key, uint8_t * const p_aid); /** To add/update NetKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_AddUpdateNetkey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] netkey_index Identifies global index of NetKey. A 12bits value. @@ -1872,8 +1802,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t const * const p_net_key); /** To add Security Credential of a LPN or the Friend. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_AddFriendSecurityCredential() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Identifies associated subnet. @@ -1885,8 +1813,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_friend_security_credential_info_t info); /** To delete the Security Credential of a LPN or the Friend. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_DeleteFriendSecurityCredential() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Identifies associated subnet. @@ -1897,8 +1823,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t friend_index); /** To find a Subnet associated with the NetKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_FindSubnet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] netkey_index Identifies global Index of NetKey, corresponding Subnet to be returned. @@ -1908,8 +1832,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t * const p_subnet_handle); /** To find the Master Subnet associated with the friend security credential, identified by Friend Subnet Handle. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_FindMasterSubnet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] friend_subnet_handle Identifies the friend subnet handle, corresponding to friend subnet handle. @@ -1920,8 +1842,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t * const p_master_subnet_handle); /** To delete NetKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_DeleteNetKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the subnet for which NetKey to be deleted. @@ -1930,8 +1850,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t subnet_handle); /** To get NetKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetNetKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Target subnet handle to get net key. @@ -1941,8 +1859,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t * const p_net_key); /** To get list of all known NetKeys. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetNetKeyIndexList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_netkey_count Pointer to NetKey count. @@ -1952,8 +1868,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_netkey_index_list); /** To search for NID. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_LookUpNid() * * @param[in] p_ctrl Pointer to control structure. * @param[in] nid NID to be searched in all known subnets for match. @@ -1965,8 +1879,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_associated_keys_t * const p_key_set); /** To search for Network ID. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_LookUpNetworkId() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_network_id Pointer to network ID to be searched in all known subnets for match. @@ -1978,8 +1890,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_associated_keys_t * const p_key_set); /** To search for AID. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_LookUpAid() * * @param[in] p_ctrl Pointer to control structure. * @param[in] aid AID to be searched in all known AppKeys for match. @@ -1990,8 +1900,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_appkey_handle_t * const p_appkey_handle, uint8_t * const p_app_key); /** Set Provisioning Data. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetProvisioningData() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_prov_data Pointer to provisioning data structure. @@ -2000,8 +1908,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_provision_data_t const * const p_prov_data); /** To get NID associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetNid() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2011,8 +1917,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t * const p_nid); /** To get privacy Key associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetPrivacyKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2022,8 +1926,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t handle, uint8_t * const p_privacy_key); /** To get Network ID associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetNetworkId() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2033,8 +1935,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t handle, uint8_t * const p_network_id); /** To get Beacon Key associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetBeaconKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2044,8 +1944,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t handle, uint8_t * const p_beacon_key); /** To get Identity Key associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetIdentityKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2055,8 +1953,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t handle, uint8_t * const p_identity_key); /** To get Encryption Key associated with a subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetSubnetEncryptionKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Handle identifying the subnet. @@ -2066,8 +1962,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t handle, uint8_t * const p_encrypt_key); /** To get Node Identity. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetNodeIdentity() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle identifying the subnet. @@ -2077,8 +1971,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t subnet_handle, uint8_t * const p_id_state); /** To set Node Identity. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetNodeIdentity() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle identifying the subnet. @@ -2088,8 +1980,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_subnet_handle_t subnet_handle, uint8_t * const p_id_state); /** To get Key refresh phase. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetKeyRefreshPhase() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle identifying the subnet. @@ -2100,8 +1990,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t * const p_key_refresh_state); /** To set Key refresh phase. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetKeyRefreshPhase() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle identifying the subnet. @@ -2112,8 +2000,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t const * const p_key_refresh_state); /** To set Network/Relay Transmit state. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetTransmitState() * * @param[in] p_ctrl Pointer to control structure. * @param[in] tx_state_type Transmit state type (Network or Relay). @@ -2122,8 +2008,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* setTransmitState)(rm_ble_mesh_access_ctrl_t * const p_ctrl, uint8_t tx_state_type, uint8_t tx_state); /** To get Network/Relay Transmit state. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetTransmitState() * * @param[in] p_ctrl Pointer to control structure. * @param[in] tx_state_type Transmit State Type (Network or Relay). @@ -2133,8 +2017,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t * const p_tx_state); /** To add AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_AddAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the subnet for which AppKey to be added. @@ -2145,8 +2027,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t appkey_index, uint8_t const * const p_app_key); /** To update/delete AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_UpdateAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the Subnet for which AppKey to be updated/deleted. @@ -2158,8 +2038,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t const * const p_app_key); /** To update/delete AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_DeleteAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the Subnet for which AppKey to be updated/deleted. @@ -2171,8 +2049,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t const * const p_app_key); /** To get AppKey Handle for a given AppKey Index. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetAppKeyHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the Subnet for which AppKey to be gotten. @@ -2186,8 +2062,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_appkey_handle_t * const p_appkey_handle); /** To get list of all known AppKeys. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetAppKeyIndexList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle of the Subnet for which AppKey to be returned. @@ -2199,8 +2073,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_appkey_index_list); /** To bind a model with an AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_BindModelWithAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Model handle identifying the model. @@ -2210,8 +2082,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_model_handle_t model_handle, uint16_t appkey_index); /** To unbind a model with an AppKey. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_UnbindModelWithAppKey() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Model handle identifying the model. @@ -2221,8 +2091,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_model_handle_t model_handle, uint16_t appkey_index); /** To get list of all AppKeys associated with a model. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetModelAppKeyList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which AppKey to be returned. @@ -2234,8 +2102,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_appkey_index_list); /** To set Publication information associated with a model. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetModelPublication() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which Publication info to be set. @@ -2246,8 +2112,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_publish_info_t * const p_publish_info); /** To set Publication Fast Period Divisor information associated with a model. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_SetModelPublicationPeriodDivisor() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which Publication info to be set. @@ -2258,8 +2122,6 @@ typedef struct st_rm_ble_mesh_access_api uint8_t period_divisor); /** To get Publication information associated with a model. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetModelPublication() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which Publication info to be returned. @@ -2270,8 +2132,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_publish_info_t * const p_publish_info); /** To add an address to a model subscription list. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_AddModelSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which address to be added in the subscription list. @@ -2282,8 +2142,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_address_t const * const p_sub_addr); /** To delete an address to a model subscription list. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_DeleteModelSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which address to be deleted in the subscription list. @@ -2294,8 +2152,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_address_t const * const p_sub_addr); /** To discard a model subscription list. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_DeleteAllModelSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which the subscription list to be discarded. @@ -2304,8 +2160,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_access_model_handle_t model_handle); /** To get list of subscription addresses of a model. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetModelSubscriptionList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] model_handle Handle of the Model for which the subscription addresses to be returned. @@ -2318,8 +2172,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_sub_addr_list); /** To get list of subscription addresses of all the models. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_GetAllModelSubscriptionList() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_sub_addr_count Pointer to maximum number of subscription address. @@ -2329,8 +2181,6 @@ typedef struct st_rm_ble_mesh_access_api uint16_t * const p_sub_addr_count, uint16_t * const p_sub_addr_list); /** To check if valid element address to receive a packet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_IsValidElementAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr A valid element address, to be checked. @@ -2338,8 +2188,6 @@ typedef struct st_rm_ble_mesh_access_api fsp_err_t (* isValidElementAddress)(rm_ble_mesh_access_ctrl_t * const p_ctrl, rm_ble_mesh_network_address_t addr); /** To check if Fixed Group Address in receive packet to be processed. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_IsFixedGroupAddressToBeProcessed() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr A valid fixed group address, to be checked. @@ -2348,8 +2196,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_address_t addr); /** To check if valid subscription address to receive a packet. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_IsValidSubscriptionAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr A valid subscription address, to be checked. @@ -2358,8 +2204,6 @@ typedef struct st_rm_ble_mesh_access_api rm_ble_mesh_network_address_t addr); /** To set the IV Update Test Mode feature. - * @par Implemented as - * - @ref RM_BLE_MESH_ACCESS_EnableIvUpdateTestMode() * * @param[in] p_ctrl Pointer to control structure. * @param[in] mode This flag is used to either enable or disable the IV update test mode feature. diff --git a/ra/fsp/inc/api/rm_ble_mesh_api.h b/ra/fsp/inc/api/rm_ble_mesh_api.h index 55107fb9a..124864f6a 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh (BLE MESH) peripheral provides Bluetooth Low Energy Mesh functionality. * - * The Bluetooth Low Energy Mesh interface can be implemented by: - * - @ref RM_BLE_MESH * * @{ **********************************************************************************************************************/ @@ -647,8 +645,6 @@ typedef struct st_rm_ble_mesh_access_state_transition } rm_ble_mesh_access_state_transition_t; /** BLE MESH control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_instance_ctrl_t */ typedef void rm_ble_mesh_ctrl_t; @@ -825,8 +821,6 @@ typedef struct st_rm_ble_mesh_cfg typedef struct st_rm_ble_mesh_api { /** Open BLE mesh middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -834,16 +828,12 @@ typedef struct st_rm_ble_mesh_api fsp_err_t (* open)(rm_ble_mesh_ctrl_t * const p_ctrl, rm_ble_mesh_cfg_t const * const p_cfg); /** Close BLE mesh middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_ctrl_t * const p_ctrl); /** To start transition timer. - * @par Implemented as - * - @ref RM_BLE_MESH_StartTransitionTimer() * * @param[in] p_ctrl * Pointer to control structure. @@ -861,8 +851,6 @@ typedef struct st_rm_ble_mesh_api uint16_t * const p_transition_time_handle); /** To stop transition timer. - * @par Implemented as - * - @ref RM_BLE_MESH_StopTransitionTimer() * * @param[in] p_ctrl * Pointer to control structure. @@ -874,8 +862,6 @@ typedef struct st_rm_ble_mesh_api fsp_err_t (* stopTransitionTimer)(rm_ble_mesh_ctrl_t * const p_ctrl, uint16_t transition_time_handle); /** To get remaining Transition Time. - * @par Implemented as - * - @ref RM_BLE_MESH_GetRemainingTransitionTime() * * @param[in] p_ctrl * Pointer to control structure. @@ -891,8 +877,6 @@ typedef struct st_rm_ble_mesh_api uint8_t * const p_remaining_transition_time); /** To get remaining Transition Time, with offset. - * @par Implemented as - * - @ref RM_BLE_MESH_GetRemainingTransitionTimeWithOffset() * * @param[in] p_ctrl * Pointer to control structure. @@ -912,8 +896,6 @@ typedef struct st_rm_ble_mesh_api uint8_t * const p_remaining_transition_time); /** To convert transition time from millisecond. - * @par Implemented as - * - @ref RM_BLE_MESH_ConvertTransitionTimeFromMs() * * @param[in] p_ctrl * Pointer to control structure. @@ -928,8 +910,6 @@ typedef struct st_rm_ble_mesh_api uint8_t * const p_transition_time); /** To convert transition time to millisecond. - * @par Implemented as - * - @ref RM_BLE_MESH_ConvertTransitionTimeToMs() * * @param [in] p_ctrl * Pointer to control structure. diff --git a/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h b/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h index 313a63e5f..6d791d1a4 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_bearer_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_BEARER_API_Summary Summary * The BLE Mesh Bearer interface for the Bluetooth Low Energy Mesh Bearer (BLE MESH BEARER) peripheral provides Bluetooth Low Energy Mesh Bearer functionality. * - * The Bluetooth Low Energy Mesh Bearer interface can be implemented by: - * - @ref RM_BLE_MESH_BEARER * * @{ **********************************************************************************************************************/ @@ -285,8 +283,6 @@ typedef struct st_rm_ble_mesh_bearer_beacon_callback_args } rm_ble_mesh_bearer_beacon_callback_args_t; /** BLE MESH BEARER control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_bearer_instance_ctrl_t */ typedef void rm_ble_mesh_bearer_ctrl_t; @@ -304,8 +300,6 @@ typedef struct st_rm_ble_mesh_bearer_cfg typedef struct st_rm_ble_mesh_bearer_api { /** Open bearer middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -313,8 +307,6 @@ typedef struct st_rm_ble_mesh_bearer_api fsp_err_t (* open)(rm_ble_mesh_bearer_ctrl_t * const p_ctrl, rm_ble_mesh_bearer_cfg_t const * const p_cfg); /** Close bearer middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_Close() * * @param[in] p_ctrl * Pointer to control structure. @@ -322,8 +314,6 @@ typedef struct st_rm_ble_mesh_bearer_api fsp_err_t (* close)(rm_ble_mesh_bearer_ctrl_t * const p_ctrl); /** Register Interface with Bearer Layer - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_RegisterInterface() * * @param[in] p_ctrl * Pointer to control structure. @@ -339,8 +329,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_bearer_ntf_callback_args_t * p_args)); /** Register Beacon Interface with Bearer Layer - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_RegisterBeaconHandler() * * @param[in] p_ctrl * Pointer to control structure. @@ -357,8 +345,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_bearer_beacon_callback_args_t * p_args)); /** Add a bearer to Bearer Layer - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_AddBearer() * * @param[in] p_ctrl * Pointer to control structure. @@ -377,8 +363,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_bearer_handle_t * const p_brr_handle); /** Remove a bearer from Bearer Layer - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_RemoveBearer() * * @param[in] p_ctrl * Pointer to control structure. @@ -393,8 +377,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_bearer_handle_t const * const p_brr_handle); /** Observe ON/OFF for the beacon type - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_ObserveBeacon() * * @param[in] p_ctrl * Pointer to control structure. @@ -408,8 +390,6 @@ typedef struct st_rm_ble_mesh_bearer_api fsp_err_t (* observeBeacon)(rm_ble_mesh_bearer_ctrl_t * const p_ctrl, uint8_t bcon_type, uint8_t enable); /** API to send Unprovisioned Device Beacon - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_BcastUnprovisionedBeacon() * * @param[in] p_ctrl * Pointer to control structure. @@ -433,8 +413,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_buffer_t const * const p_uri); /** API to broadcast a beacon - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_BroadcastBeacon() * * @param[in] p_ctrl * Pointer to control structure. @@ -452,8 +430,6 @@ typedef struct st_rm_ble_mesh_bearer_api uint8_t const * const p_packet, uint16_t length); /** API to send Proxy Device ADV - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_StartProxyAdv() * * @param[in] p_ctrl * Pointer to control structure. @@ -479,8 +455,6 @@ typedef struct st_rm_ble_mesh_bearer_api uint16_t datalen); /** Send a bearer PDU - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_SendPdu() * * @param[in] p_ctrl * Pointer to control structure. @@ -499,8 +473,6 @@ typedef struct st_rm_ble_mesh_bearer_api rm_ble_mesh_buffer_t const * const p_buffer); /** Get the RSSI of current received packet being processed. - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_GetPacketRssi() * * @param[in] p_ctrl * Pointer to control structure. @@ -514,8 +486,6 @@ typedef struct st_rm_ble_mesh_bearer_api fsp_err_t (* getPacketRssi)(rm_ble_mesh_bearer_ctrl_t * const p_ctrl, uint8_t * p_rssi_value); /** Put the bearer to sleep. - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_Sleep() * * @param[in] p_ctrl * Pointer to control structure. @@ -523,8 +493,6 @@ typedef struct st_rm_ble_mesh_bearer_api fsp_err_t (* sleep)(rm_ble_mesh_bearer_ctrl_t * const p_ctrl); /** Wakeup the bearer. - * @par Implemented as - * - @ref RM_BLE_MESH_BEARER_Wakeup() * * @param[in] p_ctrl * Pointer to control structure. diff --git a/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h b/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h index e225c93c0..d8dc69a1d 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_config_client_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_CONFIG_CLIENT_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Model Configuration Client (BLE MESH MODEL CONFIG CLIENT) middleware provides Bluetooth Low Energy Mesh Model Configuration Client functionality. * - * The Bluetooth Low Energy Mesh Model Configuration Client interface can be implemented by: - * - @ref RM_MESH_CONFIG_CLT * * @{ **********************************************************************************************************************/ @@ -63,8 +61,6 @@ typedef struct st_rm_ble_mesh_config_client_callback_args } rm_ble_mesh_config_client_callback_args_t; /** BLE MESH CONFIG CLIENT control block. Allocate an instance specific control block to pass into the BLE mesh model health client API calls. - * @par Implemented as - * - rm_ble_mesh_health_client_instance_ctrl_t */ typedef void rm_ble_mesh_config_client_ctrl_t; @@ -84,8 +80,6 @@ typedef struct st_rm_ble_mesh_config_client_cfg typedef struct st_rm_ble_mesh_config_client_api { /** API to open configuration client model. - * @par Implemented as - * - @ref RM_MESH_CONFIG_CLT_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -94,16 +88,12 @@ typedef struct st_rm_ble_mesh_config_client_api rm_ble_mesh_config_client_cfg_t const * const p_cfg); /** API to close configuration client model. - * @par Implemented as - * - @ref RM_MESH_CONFIG_CLT_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_config_client_ctrl_t * const p_ctrl); /** API to set configuration server. - * @par Implemented as - * - @ref RM_MESH_CONFIG_CLT_SetServer() * * @param[in] p_ctrl Pointer to control structure. * @param[in] server_addr Address of Configuration Server. @@ -113,8 +103,6 @@ typedef struct st_rm_ble_mesh_config_client_api uint8_t * p_dev_key); /** API to send acknowledged commands. - * @par Implemented as - * - @ref RM_MESH_CONFIG_CLT_SendReliablePdu() * * @param[in] p_ctrl Pointer to control structure. * @param[in] req_opcode Request Opcode. diff --git a/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h index 7015c7658..034650cf0 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_health_server_api.h @@ -40,8 +40,6 @@ FSP_HEADER * @section RM_BLE_MESH_HEALTH_SERVER_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Model Health Server (BLE MESH HEALTH SERVER) middleware provides Bluetooth Low Energy Mesh Model Health Server functionality. * - * The Bluetooth Low Energy Mesh Model Health Server interface can be implemented by: - * - @ref RM_MESH_HEALTH_SRV * * @{ **********************************************************************************************************************/ @@ -97,8 +95,6 @@ typedef struct st_rm_ble_mesh_health_server_self_test } rm_ble_mesh_health_server_self_test_t; /** BLE MESH HEALTH SERVER control block. Allocate an instance specific control block to pass into the BLE mesh model health server API calls. - * @par Implemented as - * - rm_ble_mesh_health_server_instance_ctrl_t */ typedef void rm_ble_mesh_health_server_ctrl_t; @@ -120,8 +116,6 @@ typedef struct st_rm_ble_mesh_health_server_cfg typedef struct st_rm_ble_mesh_health_server_api { /** API to open health server model. - * @par Implemented as - * - @ref RM_MESH_HEALTH_SERVER_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -130,16 +124,12 @@ typedef struct st_rm_ble_mesh_health_server_api rm_ble_mesh_health_server_cfg_t const * const p_cfg); /** API to close health server model. - * @par Implemented as - * - @ref RM_MESH_HEALTH_SERVER_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_health_server_ctrl_t * const p_ctrl); /** API to report self-test fault. - * @par Implemented as - * - @ref RM_MESH_HEALTH_SERVER_ReportFault() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_model_handle Pointer to model handle identifying the health server model instance. @@ -153,8 +143,6 @@ typedef struct st_rm_ble_mesh_health_server_api uint8_t fault_code); /** API to publish current status. - * @par Implemented as - * - @ref RM_MESH_HEALTH_SERVER_PublishCurrentStatus() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_status Pointer to current status. diff --git a/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h b/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h index b2339d894..1f7f2a248 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_lower_trans_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_LOWER_TRANS_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Lower Trans peripheral provides Bluetooth Low Energy Abstraction functionality. * - * The Bluetooth Low Energy Mesh interface can be implemented by: - * - @ref RM_BLE_MESH_LOWER_TRANS * * @{ **********************************************************************************************************************/ @@ -118,8 +116,6 @@ typedef struct st_rm_ble_mesh_lower_trans_callback_args } rm_ble_mesh_lower_trans_callback_args_t; /** BLE MESH control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_lower_trans_instance_ctrl_t */ typedef void rm_ble_mesh_lower_trans_ctrl_t; @@ -140,8 +136,6 @@ typedef struct st_rm_ble_mesh_lower_trans_cfg typedef struct st_rm_ble_mesh_lower_trans_api { /** Register Interface with Lower Transport Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -150,16 +144,12 @@ typedef struct st_rm_ble_mesh_lower_trans_api rm_ble_mesh_lower_trans_cfg_t const * const p_cfg); /** Unregister Interface with Lower Transport Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_lower_trans_ctrl_t * const p_ctrl); /** API to send transport PDUs. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_SendPdu() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_transmit_setting Pointer to transmit setting structure. @@ -171,16 +161,12 @@ typedef struct st_rm_ble_mesh_lower_trans_api rm_ble_mesh_buffer_t const * const p_buffer, rm_ble_mesh_lower_trans_reliable_t reliable); /** To clear all segmentation and reassembly contexts. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_ClearSarContexts() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* clearSarContexts)(rm_ble_mesh_lower_trans_ctrl_t * const p_ctrl); /** To clear all segmentation and reassembly contexts for a given subnet. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_ClearSubnetSarContexts() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Subnet Handle whose respective SAR Contexts are to be cleared. @@ -189,16 +175,12 @@ typedef struct st_rm_ble_mesh_lower_trans_api rm_ble_mesh_network_subnet_handle_t subnet_handle); /** To reinitialize all Lower Transport replay cache entries. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_ReinitReplayCache() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reinitReplayCache)(rm_ble_mesh_lower_trans_ctrl_t * const p_ctrl); /** To trigger any Lower Transport pending transmissions. - * @par Implemented as - * - @ref RM_BLE_MESH_LOWER_TRANS_TriggerPendingTransmits() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h b/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h index eebd00085..a42a4a7c0 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_model_client_api.h @@ -40,25 +40,6 @@ FSP_HEADER * @section RM_BLE_MESH_MODEL_CLIENT_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Model Client (BLE MESH MODEL CLIENT) middleware provides Bluetooth Low Energy Mesh Model Client functionality. * - * The Bluetooth Low Energy Mesh Model Client interface can be implemented by: - * - @ref RM_MESH_GENERIC_BATTERY_CLT - * - @ref RM_MESH_GENERIC_DTT_CLT - * - @ref RM_MESH_GENERIC_LEVEL_CLT - * - @ref RM_MESH_GENERIC_LOC_CLT - * - @ref RM_MESH_GENERIC_ON_OFF_CLT - * - @ref RM_MESH_GENERIC_PL_CLT - * - @ref RM_MESH_GENERIC_POO_CLT - * - @ref RM_MESH_GENERIC_PROP_CLT - * - @ref RM_MESH_HEALTH_CLT - * - @ref RM_MESH_LIGHT_CTL_CLT - * - @ref RM_MESH_LIGHT_HSL_CLT - * - @ref RM_MESH_LIGHT_LC_CLT - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT - * - @ref RM_MESH_LIGHT_XYL_CLT - * - @ref RM_MESH_SCENE_CLT - * - @ref RM_MESH_SCHEDULER_CLT - * - @ref RM_MESH_TIME_CLT - * - @ref RM_MESH_SENSOR_CLT * * @{ **********************************************************************************************************************/ @@ -80,8 +61,6 @@ typedef struct st_rm_ble_mesh_model_client_callback_args } rm_ble_mesh_model_client_callback_args_t; /** BLE MESH MODEL CLIENT control block. Allocate an instance specific control block to pass into the BLE mesh model health client API calls. - * @par Implemented as - * - rm_ble_mesh_health_client_instance_ctrl_t */ typedef void rm_ble_mesh_model_client_ctrl_t; @@ -101,25 +80,6 @@ typedef struct st_rm_ble_mesh_model_client_cfg typedef struct st_rm_ble_mesh_model_client_api { /** API to open client model. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_CLT_Open() - * - @ref RM_MESH_GENERIC_DTT_CLT_Open() - * - @ref RM_MESH_GENERIC_LEVEL_CLT_Open() - * - @ref RM_MESH_GENERIC_LOC_CLT_Open() - * - @ref RM_MESH_GENERIC_ON_OFF_CLT_Open() - * - @ref RM_MESH_GENERIC_PL_CLT_Open() - * - @ref RM_MESH_GENERIC_POO_CLT_Open() - * - @ref RM_MESH_GENERIC_PROP_CLT_Open() - * - @ref RM_MESH_LIGHT_CTL_CLT_Open() - * - @ref RM_MESH_LIGHT_HSL_CLT_Open() - * - @ref RM_MESH_LIGHT_LC_CLT_Open() - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT_Open() - * - @ref RM_MESH_LIGHT_XYL_CLT_Open() - * - @ref RM_MESH_SCENE_CLT_Open() - * - @ref RM_MESH_SCHEDULER_CLT_Open() - * - @ref RM_MESH_TIME_CLT_Open() - * - @ref RM_MESH_SENSOR_CLT_Open() - * - @ref RM_MESH_HEALTH_CLIENT_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -128,77 +88,12 @@ typedef struct st_rm_ble_mesh_model_client_api rm_ble_mesh_model_client_cfg_t const * const p_cfg); /** API to close client model. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_CLT_Close() - * - @ref RM_MESH_GENERIC_DTT_CLT_Close() - * - @ref RM_MESH_GENERIC_LEVEL_CLT_Close() - * - @ref RM_MESH_GENERIC_LOC_CLT_Close() - * - @ref RM_MESH_GENERIC_ON_OFF_CLT_Close() - * - @ref RM_MESH_GENERIC_PL_CLT_Close() - * - @ref RM_MESH_GENERIC_POO_CLT_Close() - * - @ref RM_MESH_GENERIC_PROP_CLT_Close() - * - @ref RM_MESH_LIGHT_CTL_CLT_Close() - * - @ref RM_MESH_LIGHT_HSL_CLT_Close() - * - @ref RM_MESH_LIGHT_LC_CLT_Close() - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT_Close() - * - @ref RM_MESH_LIGHT_XYL_CLT_Close() - * - @ref RM_MESH_SCENE_CLT_Close() - * - @ref RM_MESH_SCHEDULER_CLT_Close() - * - @ref RM_MESH_TIME_CLT_Close() - * - @ref RM_MESH_SENSOR_CLT_Close() - * - @ref RM_MESH_HEALTH_CLIENT_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); - /** DEPRECATED - API to set Model client model handle. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_DTT_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_LEVEL_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_LOC_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_ON_OFF_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_PL_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_POO_CLT_SetModelHandle() - * - @ref RM_MESH_GENERIC_PROP_CLT_SetModelHandle() - * - @ref RM_MESH_LIGHT_CTL_CLT_SetModelHandle() - * - @ref RM_MESH_LIGHT_HSL_CLT_SetModelHandle() - * - @ref RM_MESH_LIGHT_LC_CLT_SetModelHandle() - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT_SetModelHandle() - * - @ref RM_MESH_LIGHT_XYL_CLT_SetModelHandle() - * - @ref RM_MESH_SCENE_CLT_SetModelHandle() - * - @ref RM_MESH_SCHEDULER_CLT_SetModelHandle() - * - @ref RM_MESH_TIME_CLT_SetModelHandle() - * - @ref RM_MESH_SENSOR_CLT_SetModelHandle() - * - @ref RM_MESH_HEALTH_CLIENT_SetModelHandle() - * - * @param[in] p_ctrl Pointer to control structure. - * @param[in] model_handle Model handle to be assigned. - */ - fsp_err_t (* setModelHandle)(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - /** API to get Model client model handle. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_DTT_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_LEVEL_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_LOC_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_ON_OFF_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_PL_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_POO_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_PROP_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_CTL_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_HSL_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_LC_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_XYL_CLT_GetModelHandle() - * - @ref RM_MESH_SCENE_CLT_GetModelHandle() - * - @ref RM_MESH_SCHEDULER_CLT_GetModelHandle() - * - @ref RM_MESH_TIME_CLT_GetModelHandle() - * - @ref RM_MESH_SENSOR_CLT_GetModelHandle() - * - @ref RM_MESH_HEALTH_CLIENT_GetModelHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_model_handle Pointer to model handle to be filled/returned. @@ -207,25 +102,6 @@ typedef struct st_rm_ble_mesh_model_client_api rm_ble_mesh_access_model_handle_t * const p_model_handle); /** API to send acknowledged commands. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_DTT_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_LEVEL_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_LOC_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_ON_OFF_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_PL_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_POO_CLT_GetModelHandle() - * - @ref RM_MESH_GENERIC_PROP_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_CTL_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_HSL_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_LC_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_LIGHTNESS_CLT_GetModelHandle() - * - @ref RM_MESH_LIGHT_XYL_CLT_GetModelHandle() - * - @ref RM_MESH_SCENE_CLT_GetModelHandle() - * - @ref RM_MESH_SCHEDULER_CLT_GetModelHandle() - * - @ref RM_MESH_TIME_CLT_GetModelHandle() - * - @ref RM_MESH_SENSOR_CLT_GetModelHandle() - * - @ref RM_MESH_HEALTH_CLIENT_GetModelHandle() * * @param[in] p_ctrl Pointer to control structure. * @param[in] req_opcode Request Opcode. diff --git a/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h index abf905b1b..8137a7678 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_model_server_api.h @@ -40,27 +40,6 @@ FSP_HEADER * @section RM_BLE_MESH_MODEL_SERVER_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Model Server (BLE MESH MODEL SERVER) middleware provides Bluetooth Low Energy Mesh Model Server functionality. * - * The Bluetooth Low Energy Mesh Model Server interface can be implemented by: - * - @ref RM_MESH_CONFIG_SRV - * - @ref RM_MESH_GENERIC_BATTERY_SRV - * - @ref RM_MESH_GENERIC_DTT_SRV - * - @ref RM_MESH_GENERIC_LEVEL_SRV - * - @ref RM_MESH_GENERIC_LOC_SRV - * - @ref RM_MESH_GENERIC_ON_OFF_SRV - * - @ref RM_MESH_GENERIC_PL_SRV - * - @ref RM_MESH_GENERIC_POO_SRV - * - @ref RM_MESH_GENERIC_ADMIN_PROP_SRV - * - @ref RM_MESH_GENERIC_MFR_PROP_SRV - * - @ref RM_MESH_GENERIC_USER_PROP_SRV - * - @ref RM_MESH_GENERIC_CLIENT_PROP_SRV - * - @ref RM_MESH_LIGHT_CTL_SRV - * - @ref RM_MESH_LIGHT_HSL_SRV - * - @ref RM_MESH_LIGHT_LC_SRV - * - @ref RM_MESH_LIGHT_LIGHTNESS_SRV - * - @ref RM_MESH_LIGHT_XYL_SRV - * - @ref RM_MESH_SCHEDULER_SRV - * - @ref RM_MESH_TIME_SRV - * - @ref RM_MESH_SENSOR_SRV * * @{ **********************************************************************************************************************/ @@ -345,8 +324,6 @@ typedef struct st_rm_ble_mesh_model_server_timeout_callback_args } rm_ble_mesh_model_server_timeout_callback_args_t; /** BLE MESH MODEL SERVER control block. Allocate an instance specific control block to pass into the BLE mesh model server API calls. - * @par Implemented as - * - rm_ble_mesh_model_server_instance_ctrl_t */ typedef void rm_ble_mesh_model_server_ctrl_t; @@ -367,27 +344,6 @@ typedef struct st_rm_ble_mesh_model_server_cfg typedef struct st_rm_ble_mesh_model_server_api { /** API to open server model. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_SRV_Open() - * - @ref RM_MESH_GENERIC_DTT_SRV_Open() - * - @ref RM_MESH_GENERIC_LEVEL_SRV_Open() - * - @ref RM_MESH_GENERIC_LOC_SRV_Open() - * - @ref RM_MESH_GENERIC_ON_OFF_SRV_Open() - * - @ref RM_MESH_GENERIC_PL_SRV_Open() - * - @ref RM_MESH_GENERIC_POO_SRV_Open() - * - @ref RM_MESH_GENERIC_ADMIN_PROP_SRV_Open() - * - @ref RM_MESH_GENERIC_CLIENT_PROP_SRV_Open() - * - @ref RM_MESH_GENERIC_MFR_PROP_SRV_Open() - * - @ref RM_MESH_GENERIC_USER_PROP_SRV_Open() - * - @ref RM_MESH_LIGHT_CTL_SRV_Open() - * - @ref RM_MESH_LIGHT_HSL_SRV_Open() - * - @ref RM_MESH_LIGHT_LC_SRV_Open() - * - @ref RM_MESH_LIGHT_LIGHTNESS_SRV_Open() - * - @ref RM_MESH_LIGHT_XYL_SRV_Open() - * - @ref RM_MESH_SCHEDULER_SRV_Open() - * - @ref RM_MESH_TIME_SRV_Open() - * - @ref RM_MESH_SENSOR_SRV_Open() - * - @ref RM_MESH_CONFIG_SRV_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -396,53 +352,12 @@ typedef struct st_rm_ble_mesh_model_server_api rm_ble_mesh_model_server_cfg_t const * const p_cfg); /** API to close server model. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_SRV_Close() - * - @ref RM_MESH_GENERIC_DTT_SRV_Close() - * - @ref RM_MESH_GENERIC_LEVEL_SRV_Close() - * - @ref RM_MESH_GENERIC_LOC_SRV_Close() - * - @ref RM_MESH_GENERIC_ON_OFF_SRV_Close() - * - @ref RM_MESH_GENERIC_PL_SRV_Close() - * - @ref RM_MESH_GENERIC_POO_SRV_Close() - * - @ref RM_MESH_GENERIC_ADMIN_PROP_SRV_Close() - * - @ref RM_MESH_GENERIC_CLIENT_PROP_SRV_Close() - * - @ref RM_MESH_GENERIC_MFR_PROP_SRV_Close() - * - @ref RM_MESH_GENERIC_USER_PROP_SRV_Close() - * - @ref RM_MESH_LIGHT_CTL_SRV_Close() - * - @ref RM_MESH_LIGHT_HSL_SRV_Close() - * - @ref RM_MESH_LIGHT_LC_SRV_Close() - * - @ref RM_MESH_LIGHT_LIGHTNESS_SRV_Close() - * - @ref RM_MESH_LIGHT_XYL_SRV_Close() - * - @ref RM_MESH_SCHEDULER_SRV_Close() - * - @ref RM_MESH_TIME_SRV_Close() - * - @ref RM_MESH_SENSOR_SRV_Close() - * - @ref RM_MESH_CONFIG_SRV_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_model_server_ctrl_t * const p_ctrl); /** API to send reply or to update state change. - * @par Implemented as - * - @ref RM_MESH_GENERIC_BATTERY_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_LEVEL_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_LOC_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_ON_OFF_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_PL_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_POO_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_ADMIN_PROP_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_CLIENT_PROP_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_MFR_PROP_SRV_StateUpdate() - * - @ref RM_MESH_GENERIC_USER_PROP_SRV_StateUpdate() - * - @ref RM_MESH_LIGHT_CTL_SRV_StateUpdate() - * - @ref RM_MESH_LIGHT_HSL_SRV_StateUpdate() - * - @ref RM_MESH_LIGHT_LC_SRV_StateUpdate() - * - @ref RM_MESH_LIGHT_LIGHTNESS_SRV_StateUpdate() - * - @ref RM_MESH_LIGHT_XYL_SRV_StateUpdate() - * - @ref RM_MESH_SCHEDULER_SRV_StateUpdate() - * - @ref RM_MESH_TIME_SRV_StateUpdate() - * - @ref RM_MESH_SENSOR_SRV_StateUpdate() - * - @ref RM_MESH_CONFIG_SRV_StateUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_state Pointer to model specific current/target state parameters. diff --git a/ra/fsp/inc/api/rm_ble_mesh_network_api.h b/ra/fsp/inc/api/rm_ble_mesh_network_api.h index b0a65a98d..126ca47c1 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_network_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_network_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_NETWORK_API_Summary Summary * The BLE Mesh Network interface for the Bluetooth Low Energy Mesh Network (BLE MESH NETWORK) peripheral provides Bluetooth Low Energy Mesh Network functionality. * - * The Bluetooth Low Energy Mesh interface can be implemented by: - * - @ref RM_BLE_MESH_NETWORK * * @{ **********************************************************************************************************************/ @@ -284,8 +282,6 @@ typedef struct st_rm_ble_mesh_network_callback_args } rm_ble_mesh_network_callback_args_t; /** BLE MESH NETWORK control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_network_instance_ctrl_t */ typedef void rm_ble_mesh_network_ctrl_t; @@ -308,8 +304,6 @@ typedef struct st_rm_ble_mesh_network_cfg typedef struct st_rm_ble_mesh_network_api { /** Register Interface with Network Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -317,16 +311,12 @@ typedef struct st_rm_ble_mesh_network_api fsp_err_t (* open)(rm_ble_mesh_network_ctrl_t * const p_ctrl, rm_ble_mesh_network_cfg_t const * const p_cfg); /** Unregister Interface with Network Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_network_ctrl_t * const p_ctrl); /** API to send Secure Network Beacon. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_BroadcastSecureBeacon() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Subnet handle of the network to be broadcasted. @@ -335,8 +325,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_subnet_handle_t subnet_handle); /** Extension API to send network PDUs on selected network interfaces. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_SendPduOnInterface() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_route_info Pointer to network configuration information. @@ -349,8 +337,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_buffer_t const * const p_buffer); /** To get address type. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_GetAddressType() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr Input network address. @@ -363,8 +349,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_address_type_t * const p_type); /** Check if the proxy module is ready to handle proxy messages/events. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_FetchProxyState() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_proxy_state Returns the current state of the proxy. @@ -373,8 +357,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_gatt_proxy_state_t * const p_proxy_state); /** Set proxy server's filter type. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_SetProxyFilter() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_route_info Pointer to network configuration information. @@ -387,8 +369,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_proxy_filter_type_t type); /** Add or Delete/Remove addresses to/from proxy filter list. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_ConfigProxyFilter() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_route_info Pointer to network configuration information. @@ -404,8 +384,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_proxy_address_list_t * const p_addr_list); /** Start connectable advertisements for a proxy server. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_StartProxyServerAdv() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Subnet handle which the proxy server is part of network. @@ -418,16 +396,12 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_gatt_proxy_adv_mode_t proxy_adv_mode); /** Stop connectable advertisements for a proxy server. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_StopProxyServerAdv() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stopProxyServerAdv)(rm_ble_mesh_network_ctrl_t * const p_ctrl); /** To allocate sequence number. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_AllocateSeqNumber() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_seq_num Location where sequence number to be filled. @@ -435,8 +409,6 @@ typedef struct st_rm_ble_mesh_network_api fsp_err_t (* allocateSeqNumber)(rm_ble_mesh_network_ctrl_t * const p_ctrl, uint32_t * const p_seq_num); /** To get current sequence number state. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_GetSeqNumberState() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_seq_num_state Location where sequence number state to be filled. @@ -445,8 +417,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_seq_number_state_t * const p_seq_num_state); /** To set current sequence number state. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_SetSeqNumberState() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_seq_num_state Location from where sequence number state to be taken. @@ -455,8 +425,6 @@ typedef struct st_rm_ble_mesh_network_api rm_ble_mesh_network_seq_number_state_t const * const p_seq_num_state); /** To reinitialize all Network Layer cache entries. - * @par Implemented as - * - @ref RM_BLE_MESH_NETWORK_ResetNetCache() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_ble_mesh_provision_api.h b/ra/fsp/inc/api/rm_ble_mesh_provision_api.h index 704f1f03b..52bcfda96 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_provision_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_provision_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_PROVISION_API_Summary Summary * The BLE Mesh Provision interface for the Bluetooth Low Energy Mesh Provision (BLE MESH PROVISION) peripheral provides Bluetooth Low Energy Mesh Provision functionality. * - * The Bluetooth Low Energy Mesh interface can be implemented by: - * - @ref RM_BLE_MESH_PROVISION * * @{ **********************************************************************************************************************/ @@ -443,8 +441,6 @@ typedef struct st_rm_ble_mesh_provision_callback_args } rm_ble_mesh_provision_callback_args_t; /** BLE MESH PROVISION control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_provision_instance_ctrl_t */ typedef void rm_ble_mesh_provision_ctrl_t; @@ -464,8 +460,6 @@ typedef struct st_rm_ble_mesh_provision_cfg typedef struct st_rm_ble_mesh_provision_api { /** Open access middleware. - * @par Implemented as - * - RM_BLE_MESH_PROVISION_Open() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_cfg Pointer to pin configuration structure. @@ -473,16 +467,12 @@ typedef struct st_rm_ble_mesh_provision_api fsp_err_t (* open)(rm_ble_mesh_provision_ctrl_t * const p_ctrl, rm_ble_mesh_provision_cfg_t const * const p_cfg); /** Close access middleware. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_Close() * * @param [in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_provision_ctrl_t * const p_ctrl); /** Setup the device for provisioning. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_Setup() * * @param [in] p_ctrl Pointer to control structure. * @param [in] role Provisioning role to be setup - Device or Provisioner. @@ -493,8 +483,6 @@ typedef struct st_rm_ble_mesh_provision_api rm_ble_mesh_provision_device_info_t info, uint16_t timeout); /** Bind to the peer device for provisioning - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_Bind() * * @param [in] p_ctrl Pointer to control structure. * @param [in] info Device information. @@ -508,8 +496,6 @@ typedef struct st_rm_ble_mesh_provision_api uint8_t attention, rm_ble_mesh_provision_handle_t * const p_handle); /** Send provisioning PDUs to the peer. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_SendPdu() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_handle Pointer to provisioning context to be used. @@ -524,8 +510,6 @@ typedef struct st_rm_ble_mesh_provision_api rm_ble_mesh_buffer_t pdu_data); /** Set the display Auth-Value. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_SetAuthVal() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_handle Pointer to provisioning context to be used. @@ -535,8 +519,6 @@ typedef struct st_rm_ble_mesh_provision_api rm_ble_mesh_provision_handle_t const * const p_handle, rm_ble_mesh_buffer_t auth_value); /** Abort the provisioning procedure - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_Abort() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_handle Pointer to provisioning context to be used. @@ -547,8 +529,6 @@ typedef struct st_rm_ble_mesh_provision_api rm_ble_mesh_provision_link_close_reason_t reason); /** Utility API to get current ECDH Public Key to be used for Provisioning - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_GetLocalPublicKey() * * @param [in] p_ctrl Pointer to control structure. * @param [out] public_key To a pointer of uint8_t array of length @@ -557,8 +537,6 @@ typedef struct st_rm_ble_mesh_provision_api fsp_err_t (* getLocalPublicKey)(rm_ble_mesh_provision_ctrl_t * const p_ctrl, uint8_t * const public_key); /** Utility API to set current ECDH Public Key to be used for Provisioning - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_SetLocalPublicKey() * * @param [in] p_ctrl Pointer to control structure. * @param [out] public_key To a pointer of uint8_t array of length @@ -567,8 +545,6 @@ typedef struct st_rm_ble_mesh_provision_api fsp_err_t (* setLocalPublicKey)(rm_ble_mesh_provision_ctrl_t * const p_ctrl, uint8_t const * const public_key); /** Utility API to generate 128bits (16 bytes) randomized number to be used for provisioning. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_GenerateRandomizedNumber() * * @param [in] p_ctrl Pointer to control structure. * @param [out] p_key Pointer to buffer to store random number. @@ -576,8 +552,6 @@ typedef struct st_rm_ble_mesh_provision_api fsp_err_t (* generateRandomizedNumber)(rm_ble_mesh_provision_ctrl_t * const p_ctrl, uint8_t * const p_key); /** Utility API to set device out of band public key for provisioning. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_SetOobPublicKey() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_key Pointer to public key. @@ -587,8 +561,6 @@ typedef struct st_rm_ble_mesh_provision_api uint8_t size); /** Utility API to set device out of band authentication information for provisioning. - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_SetOobAuthInfo() * * @param [in] p_ctrl Pointer to control structure. * @param [in] p_auth_info Pointer to authentication information. @@ -598,8 +570,6 @@ typedef struct st_rm_ble_mesh_provision_api uint8_t size); /** Utility API to generate ECDH Public Key to be used for Provisioning - * @par Implemented as - * - @ref RM_BLE_MESH_PROVISION_GenerateEcdhKey() * * @param [in] p_ctrl Pointer to control structure. * @param [out] p_public_key Pointer to public key. Size of public key is @ref RM_BLE_MESH_PROVISION_ECDH_KEY_SIZE. diff --git a/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h b/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h index 8968d5d25..5a664ded2 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_scene_server_api.h @@ -40,8 +40,6 @@ FSP_HEADER * @section RM_BLE_MESH_SCENE_SERVER_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Model Scene Server (BLE MESH HEALTH SERVER) middleware provides Bluetooth Low Energy Mesh Model Scene Server functionality. * - * The Bluetooth Low Energy Mesh Model Scene Server interface can be implemented by: - * - @ref RM_MESH_SCENE_SRV * * @{ **********************************************************************************************************************/ @@ -101,8 +99,6 @@ typedef struct st_rm_ble_mesh_scene_server_timeout_callback_args } rm_ble_mesh_scene_server_timeout_callback_args_t; /** BLE MESH SCENE SERVER control block. Allocate an instance specific control block to pass into the BLE mesh model scene server API calls. - * @par Implemented as - * - rm_ble_mesh_scene_server_instance_ctrl_t */ typedef void rm_ble_mesh_scene_server_ctrl_t; @@ -115,7 +111,7 @@ typedef struct st_rm_ble_mesh_scene_server_cfg rm_ble_mesh_access_model_handle_t setup_server_handle; ///< Access Model handle for setup server. /* Pointer to callback and optional working memory */ - void * (*p_callback)(rm_ble_mesh_scene_server_callback_args_t * p_args); ///< Mesh model scene server callback. + void (* p_callback)(rm_ble_mesh_scene_server_callback_args_t * p_args); ///< Mesh model scene server callback. void (* p_timeout_callback)(rm_ble_mesh_scene_server_timeout_callback_args_t * p_args); ///< Mesh model scene server publication timeout callback. void const * p_context; ///< Placeholder for user data. void const * p_extend; ///< Placeholder for user extension. @@ -125,8 +121,6 @@ typedef struct st_rm_ble_mesh_scene_server_cfg typedef struct st_rm_ble_mesh_scene_server_api { /** API to open scene server model. - * @par Implemented as - * - @ref RM_MESH_SCENE_SRV_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -135,16 +129,12 @@ typedef struct st_rm_ble_mesh_scene_server_api rm_ble_mesh_scene_server_cfg_t const * const p_cfg); /** API to close scene server model. - * @par Implemented as - * - @ref RM_MESH_SCENE_SRV_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_scene_server_ctrl_t * const p_ctrl); /** API to send reply or to update state change. - * @par Implemented as - * - @ref RM_MESH_SCENE_SRV_StateUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_state Pointer to model specific current/target state parameters. diff --git a/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h b/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h index 70bdf7850..16ca55c72 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_upper_trans_api.h @@ -29,8 +29,6 @@ * @section RM_BLE_MESH_UPPER_TRANS_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Upper Trans peripheral provides Bluetooth Low Energy Mesh Upper Trans functionality. * - * The Bluetooth Low Energy Mesh interface can be implemented by: - * - @ref RM_BLE_MESH_UPPER_TRANS * * @{ **********************************************************************************************************************/ @@ -292,8 +290,6 @@ typedef struct st_rm_ble_mesh_upper_trans_callback_args } rm_ble_mesh_upper_trans_callback_args_t; /** BLE MESH control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_ble_mesh_upper_trans_instance_ctrl_t */ typedef void rm_ble_mesh_upper_trans_ctrl_t; @@ -314,8 +310,6 @@ typedef struct st_rm_ble_mesh_upper_trans_cfg typedef struct st_rm_ble_mesh_upper_trans_api { /** Register interface with Transport Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -324,16 +318,12 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_cfg_t const * const p_cfg); /** Unregister interface with Transport Layer. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_ble_mesh_upper_trans_ctrl_t * const p_ctrl); /** API to send Access Layer PDUs. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_SendAccessPdu() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_access_layer_pdu Pointer to Access Layer PDUs. @@ -344,8 +334,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_lower_trans_reliable_t reliable); /** API to send transport Control PDUs. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_SendControlPdu() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_control_pdu Pointer to control PDUs. @@ -354,8 +342,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_control_pdu_t const * const p_control_pdu); /** API to setup Friendship. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_LpnSetupFriendship() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_setting Pointer to friendship settings. @@ -364,16 +350,12 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_friendship_setting_t const * const p_setting); /** API to terminate friendship. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_LpnClearFriendship() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* lpnClearFriendship)(rm_ble_mesh_upper_trans_ctrl_t * const p_ctrl); /** API to manage friend subscription list. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_LpnManageSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[in] action Will be one of @ref RM_BLE_MESH_UPPER_TRANS_CONTROL_OPCODE_FRIEND_SUBSCRN_LIST_ADD or @ref RM_BLE_MESH_UPPER_TRANS_CONTROL_OPCODE_FRIEND_SUBSCRN_LIST_REMOVE. @@ -385,16 +367,12 @@ typedef struct st_rm_ble_mesh_upper_trans_api uint16_t const * const p_addr_list, uint16_t count); /** To trigger Friend Poll from application. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_LpnPoll() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* lpnPoll)(rm_ble_mesh_upper_trans_ctrl_t * const p_ctrl); /** To check if address matches with any of the LPN. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_IsValidLpnElementAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr Unicast address to search. @@ -405,8 +383,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_lower_trans_lpn_handle_t * const p_lpn_handle); /** To check if valid subscription address of an LPN to receive a packet. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_IsValidLpnSubscriptionAddress() * * @param[in] p_ctrl Pointer to control structure. * @param[in] addr Address to search. @@ -417,8 +393,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_lower_trans_lpn_handle_t * const p_lpn_handle); /** To get Poll Timeout of an LPN. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_GetLpnPolltimeout() * * @param[in] p_ctrl Pointer to control structure. * @param[in] lpn_addr LPN address to search. @@ -428,8 +402,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_network_address_t lpn_addr, uint32_t * const p_poll_timeout); /** To get the LPN node information. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_GetFriendshipInfo() * * @param[in] p_ctrl Pointer to control structure. * @param[in] role Local friendship role. @@ -441,8 +413,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_friendship_info_t * const p_node); /** To add the security update information. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_LpnRegisterSecurityUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] subnet_handle Handle to identify the network. @@ -454,16 +424,12 @@ typedef struct st_rm_ble_mesh_upper_trans_api uint32_t ivindex); /** To clear information related to all LPNs. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_ClearAllLpn() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* clearAllLpn)(rm_ble_mesh_upper_trans_ctrl_t * const p_ctrl); /** To set the heartbeat publication data. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_SetHeartbeatPublication() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Heartbeat Publication information data as in \ref rm_ble_mesh_upper_trans_heartbeat_publication_info_t. @@ -472,8 +438,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_heartbeat_publication_info_t * const p_info); /** To get the heartbeat publication data. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_GetHeartbeatPublication() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Heartbeat Publication information data as in \ref rm_ble_mesh_upper_trans_heartbeat_publication_info_t. @@ -482,8 +446,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_heartbeat_publication_info_t * const p_info); /** To set the heartbeat subscription data. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_SetHeartbeatSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Heartbeat Publication information data as in \ref rm_ble_mesh_upper_trans_heartbeat_subscription_info_t. @@ -492,8 +454,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_heartbeat_subscription_info_t * const p_info); /** To get the heartbeat subscription data. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_GetHeartbeatSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Heartbeat Publication information data as in \ref rm_ble_mesh_upper_trans_heartbeat_subscription_info_t. @@ -502,8 +462,6 @@ typedef struct st_rm_ble_mesh_upper_trans_api rm_ble_mesh_upper_trans_heartbeat_subscription_info_t * const p_info); /** To trigger heartbeat send on change in feature. - * @par Implemented as - * - @ref RM_BLE_MESH_UPPER_TRANS_GetHeartbeatSubscription() * * @param[in] p_ctrl Pointer to control structure. * @param[in] change_in_feature_bit Bit mask of the changed feature field. diff --git a/ra/fsp/inc/api/rm_block_media_api.h b/ra/fsp/inc/api/rm_block_media_api.h index 677e3d821..01084d1b0 100644 --- a/ra/fsp/inc/api/rm_block_media_api.h +++ b/ra/fsp/inc/api/rm_block_media_api.h @@ -30,11 +30,6 @@ * The block media interface supports reading, writing, and erasing media devices. All functions are non-blocking if * possible. The callback is used to determine when an operation completes. * - * Implemented by: - * - @ref RM_BLOCK_MEDIA_SDMMC - * - @ref RM_BLOCK_MEDIA_SPI - * - @ref RM_BLOCK_MEDIA_USB - * - @ref RM_BLOCK_MEDIA_RAM * * @{ **********************************************************************************************************************/ @@ -105,11 +100,6 @@ typedef struct st_rm_block_media_status } rm_block_media_status_t; /** Block media API control block. Allocate an instance specific control block to pass into the block media API calls. - * @par Implemented as - * - @ref rm_block_media_sdmmc_instance_ctrl_t - * - @ref rm_block_media_spi_instance_ctrl_t - * - @ref rm_block_media_usb_instance_ctrl_t - * - @ref rm_block_media_ram_instance_ctrl_t */ typedef void rm_block_media_ctrl_t; @@ -118,11 +108,6 @@ typedef struct st_rm_block_media_api { /** Initialize block media device. @ref rm_block_media_api_t::mediaInit must be called to complete the * initialization procedure. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_Open - * - @ref RM_BLOCK_MEDIA_SPI_Open - * - @ref RM_BLOCK_MEDIA_USB_Open - * - @ref RM_BLOCK_MEDIA_RAM_Open * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -131,22 +116,12 @@ typedef struct st_rm_block_media_api /** Initializes a media device. If the device is removable, it must be plugged in prior to calling this API. * This function blocks until media initialization is complete. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_MediaInit - * - @ref RM_BLOCK_MEDIA_SPI_MediaInit - * - @ref RM_BLOCK_MEDIA_USB_MediaInit - * - @ref RM_BLOCK_MEDIA_RAM_MediaInit * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. */ fsp_err_t (* mediaInit)(rm_block_media_ctrl_t * const p_ctrl); /** Reads blocks of data from the specified memory device address to the location specified by the caller. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_Read - * - @ref RM_BLOCK_MEDIA_SPI_Read - * - @ref RM_BLOCK_MEDIA_USB_Read - * - @ref RM_BLOCK_MEDIA_RAM_Read * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_dest_address Destination to read the data into. @@ -157,11 +132,6 @@ typedef struct st_rm_block_media_api uint32_t const block_address, uint32_t const num_blocks); /** Writes blocks of data to the specified device memory address. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_Write - * - @ref RM_BLOCK_MEDIA_SPI_Write - * - @ref RM_BLOCK_MEDIA_USB_Write - * - @ref RM_BLOCK_MEDIA_RAM_Write * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[in] p_src_address Address to read the data to be written. @@ -172,11 +142,6 @@ typedef struct st_rm_block_media_api uint32_t const block_address, uint32_t const num_blocks); /** Erases blocks of data from the memory device. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_Erase - * - @ref RM_BLOCK_MEDIA_SPI_Erase - * - @ref RM_BLOCK_MEDIA_USB_Erase - * - @ref RM_BLOCK_MEDIA_RAM_Erase * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[in] block_address Block address to start the erase process at. @@ -185,8 +150,6 @@ typedef struct st_rm_block_media_api fsp_err_t (* erase)(rm_block_media_ctrl_t * const p_ctrl, uint32_t const block_address, uint32_t const num_blocks); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_CallbackSet() * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[in] p_callback Callback function to register @@ -200,12 +163,6 @@ typedef struct st_rm_block_media_api rm_block_media_callback_args_t * const p_callback_memory); /** Get status of connected device. - * - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_StatusGet - * - @ref RM_BLOCK_MEDIA_SPI_StatusGet - * - @ref RM_BLOCK_MEDIA_USB_StatusGet - * - @ref RM_BLOCK_MEDIA_RAM_StatusGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_status Pointer to store current status. @@ -213,11 +170,6 @@ typedef struct st_rm_block_media_api fsp_err_t (* statusGet)(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_status_t * const p_status); /** Returns information about the block media device. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_InfoGet - * - @ref RM_BLOCK_MEDIA_SPI_InfoGet - * - @ref RM_BLOCK_MEDIA_USB_InfoGet - * - @ref RM_BLOCK_MEDIA_RAM_InfoGet * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. * @param[out] p_info Pointer to information structure. All elements of this structure will be set by the @@ -226,11 +178,6 @@ typedef struct st_rm_block_media_api fsp_err_t (* infoGet)(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info); /** Closes the module. - * @par Implemented as - * - @ref RM_BLOCK_MEDIA_SDMMC_Close - * - @ref RM_BLOCK_MEDIA_SPI_Close - * - @ref RM_BLOCK_MEDIA_USB_Close - * - @ref RM_BLOCK_MEDIA_RAM_Close * * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. */ diff --git a/ra/fsp/inc/api/rm_comms_api.h b/ra/fsp/inc/api/rm_comms_api.h index 1fbf718cc..4b33207ab 100644 --- a/ra/fsp/inc/api/rm_comms_api.h +++ b/ra/fsp/inc/api/rm_comms_api.h @@ -26,8 +26,6 @@ * @section RM_COMMS_API_Summary Summary * The Communications interface provides multiple communications functionality. * - * The Communications interface can be implemented by: - * - @ref RM_COMMS_I2C * * @{ **********************************************************************************************************************/ @@ -103,8 +101,6 @@ typedef struct st_rm_comms_cfg } rm_comms_cfg_t; /** Communications control block. Allocate an instance specific control block to pass into the Communications API calls. - * @par Implemented as - * - rm_comms_i2c_instance_ctrl_t */ typedef void rm_comms_ctrl_t; @@ -112,9 +108,6 @@ typedef void rm_comms_ctrl_t; typedef struct st_rm_comms_api { /** Open driver. - * @par Implemented as - * - @ref RM_COMMS_I2C_Open() - * - @ref RM_COMMS_UART_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -122,18 +115,12 @@ typedef struct st_rm_comms_api fsp_err_t (* open)(rm_comms_ctrl_t * const p_ctrl, rm_comms_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref RM_COMMS_I2C_Close() - * - @ref RM_COMMS_UART_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_comms_ctrl_t * const p_ctrl); /** Read data. - * @par Implemented as - * - @ref RM_COMMS_I2C_Read() - * - @ref RM_COMMS_UART_Read() * * @param[in] p_ctrl Pointer to control structure. * @param[in] 　p_dest Pointer to the location to store read data. @@ -142,9 +129,6 @@ typedef struct st_rm_comms_api fsp_err_t (* read)(rm_comms_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); /** Write data. - * @par Implemented as - * - @ref RM_COMMS_I2C_Write() - * - @ref RM_COMMS_UART_Write() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_src Pointer to the location to get write data from. @@ -153,9 +137,6 @@ typedef struct st_rm_comms_api fsp_err_t (* write)(rm_comms_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes); /** Write bytes over comms followed by a read, will have a struct for params. - * @par Implemented as - * - @ref RM_COMMS_I2C_WriteRead() - * - @ref RM_COMMS_UART_WriteRead() * * @param[in] p_ctrl Pointer to control structure. * @param[in] write_read_params Parameters structure. @@ -164,14 +145,12 @@ typedef struct st_rm_comms_api /** * Specify callback function and optional context pointer. - * @par Implemented as - * - RM_COMMS_UART_CallbackSet() * * @param[in] p_ctrl Pointer to the control block. * @param[in] p_callback Callback function * @param[in] p_context Pointer to send to callback function */ - fsp_err_t (* callbackSet)(rm_comms_ctrl_t * const p_api_ctrl, void (* p_callback)(rm_comms_callback_args_t *), + fsp_err_t (* callbackSet)(rm_comms_ctrl_t * const p_ctrl, void (* p_callback)(rm_comms_callback_args_t *), void const * const p_context); } rm_comms_api_t; diff --git a/ra/fsp/inc/api/rm_filex_block_media_api.h b/ra/fsp/inc/api/rm_filex_block_media_api.h index 20add1e43..fb56c1dce 100644 --- a/ra/fsp/inc/api/rm_filex_block_media_api.h +++ b/ra/fsp/inc/api/rm_filex_block_media_api.h @@ -30,8 +30,6 @@ * The FileX block media port provides notifications for insertion and removal of removable media and provides * initialization functions required by FileX. * - * The FileX Block media interface can be implemented by: - * @ref RM_FILEX_BLOCK_MEDIA * * @{ **********************************************************************************************************************/ @@ -82,8 +80,6 @@ typedef void rm_filex_block_media_ctrl_t; typedef struct st_rm_filex_block_media_api { /** Open media device. - * @par Implemented as - * - @ref RM_FILEX_BLOCK_MEDIA_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -91,8 +87,6 @@ typedef struct st_rm_filex_block_media_api fsp_err_t (* open)(rm_filex_block_media_ctrl_t * const p_ctrl, rm_filex_block_media_cfg_t const * const p_cfg); /** Close media device. - * @par Implemented as - * - @ref RM_FILEX_BLOCK_MEDIA_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h index c7657504a..6aad76884 100644 --- a/ra/fsp/inc/api/rm_freertos_plus_fat_api.h +++ b/ra/fsp/inc/api/rm_freertos_plus_fat_api.h @@ -30,8 +30,6 @@ * The FreeRTOS+FAT port provides notifications for insertion and removal of removable media and provides * initialization functions required by FreeRTOS+FAT. * - * The FreeRTOS+FAT interface can be implemented by: - * @ref RM_FREERTOS_PLUS_FAT * * @{ **********************************************************************************************************************/ @@ -127,8 +125,6 @@ typedef void rm_freertos_plus_fat_ctrl_t; typedef struct st_rm_freertos_plus_fat_api { /** Open media device. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -137,8 +133,6 @@ typedef struct st_rm_freertos_plus_fat_api /** Initializes a media device. If the device is removable, it must be plugged in prior to calling this API. * This function blocks until media initialization is complete. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_MediaInit * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_device Pointer to store device information. @@ -146,8 +140,6 @@ typedef struct st_rm_freertos_plus_fat_api fsp_err_t (* mediaInit)(rm_freertos_plus_fat_ctrl_t * const p_ctrl, rm_freertos_plus_fat_device_t * const p_device); /** Initializes a FreeRTOS+FAT FF_Disk_t structure. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_DiskInit * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_disk_cfg Pointer to disk configurations @@ -157,8 +149,6 @@ typedef struct st_rm_freertos_plus_fat_api rm_freertos_plus_fat_disk_cfg_t const * const p_disk_cfg, FF_Disk_t * const p_disk); /** Deinitializes a FreeRTOS+FAT FF_Disk_t structure. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_DiskDeinit * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_disk_cfg Pointer to disk configurations @@ -167,8 +157,6 @@ typedef struct st_rm_freertos_plus_fat_api fsp_err_t (* diskDeinit)(rm_freertos_plus_fat_ctrl_t * const p_ctrl, FF_Disk_t * const p_disk); /** Returns information about the media device. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_InfoGet * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Pointer to information structure. All elements of this structure will be set by the @@ -178,8 +166,6 @@ typedef struct st_rm_freertos_plus_fat_api rm_freertos_plus_fat_info_t * const p_info); /** Close media device. - * @par Implemented as - * - @ref RM_FREERTOS_PLUS_FAT_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_fsxxxx_api.h b/ra/fsp/inc/api/rm_fsxxxx_api.h index e2e957a00..c76db22db 100644 --- a/ra/fsp/inc/api/rm_fsxxxx_api.h +++ b/ra/fsp/inc/api/rm_fsxxxx_api.h @@ -26,8 +26,6 @@ * @section RM_FSXXXX_API_Summary Summary * The FSXXXX interface provides FSXXXX functionality. * - * The FSXXXX interface can be implemented by: - * - @ref RM_FS2012 * * @{ **********************************************************************************************************************/ @@ -111,8 +109,6 @@ typedef struct st_rm_fsxxxx_cfg } rm_fsxxxx_cfg_t; /** FSXXXX control block. Allocate an instance specific control block to pass into the FSXXXX API calls. - * @par Implemented as - * - rm_fsxxxx_instance_ctrl_t */ typedef void rm_fsxxxx_ctrl_t; @@ -120,8 +116,6 @@ typedef void rm_fsxxxx_ctrl_t; typedef struct st_rm_fsxxxx_api { /** Open sensor. - * @par Implemented as - * - @ref RM_FS2012_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -129,8 +123,6 @@ typedef struct st_rm_fsxxxx_api fsp_err_t (* open)(rm_fsxxxx_ctrl_t * const p_ctrl, rm_fsxxxx_cfg_t const * const p_cfg); /** Read ADC data from FSXXXX. - * @par Implemented as - * - @ref RM_FS2012_Read() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -138,8 +130,6 @@ typedef struct st_rm_fsxxxx_api fsp_err_t (* read)(rm_fsxxxx_ctrl_t * const p_ctrl, rm_fsxxxx_raw_data_t * const p_raw_data); /** Calculate flow values from ADC data. - * @par Implemented as - * - @ref RM_FS2012_DataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. @@ -149,8 +139,6 @@ typedef struct st_rm_fsxxxx_api rm_fsxxxx_data_t * const p_fsxxxx_data); /** Close FSXXXX. - * @par Implemented as - * - @ref RM_FS2012_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_hs300x_api.h b/ra/fsp/inc/api/rm_hs300x_api.h index 027fc8721..f0896fa8c 100644 --- a/ra/fsp/inc/api/rm_hs300x_api.h +++ b/ra/fsp/inc/api/rm_hs300x_api.h @@ -26,8 +26,6 @@ * @section RM_HS300X_API_Summary Summary * The HS300X interface provides HS300X functionality. * - * The HS300X interface can be implemented by: - * - @ref RM_HS300X * * @{ **********************************************************************************************************************/ @@ -128,8 +126,6 @@ typedef struct st_rm_hs300x_cfg } rm_hs300x_cfg_t; /** HS300X control block. Allocate an instance specific control block to pass into the HS300X API calls. - * @par Implemented as - * - rm_hs300x_instance_ctrl_t */ typedef void rm_hs300x_ctrl_t; @@ -137,8 +133,6 @@ typedef void rm_hs300x_ctrl_t; typedef struct st_rm_hs300x_api { /** Open sensor. - * @par Implemented as - * - @ref RM_HS300X_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -146,16 +140,12 @@ typedef struct st_rm_hs300x_api fsp_err_t (* open)(rm_hs300x_ctrl_t * const p_ctrl, rm_hs300x_cfg_t const * const p_cfg); /** Start a measurement. - * @par Implemented as - * - @ref RM_HS300X_MeasurementStart() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* measurementStart)(rm_hs300x_ctrl_t * const p_ctrl); /** Read ADC data from HS300X. - * @par Implemented as - * - @ref RM_HS300X_Read() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -163,8 +153,6 @@ typedef struct st_rm_hs300x_api fsp_err_t (* read)(rm_hs300x_ctrl_t * const p_ctrl, rm_hs300x_raw_data_t * const p_raw_data); /** Calculate humidity and temperature values from ADC data. - * @par Implemented as - * - @ref RM_HS300X_DataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. @@ -174,16 +162,12 @@ typedef struct st_rm_hs300x_api rm_hs300x_data_t * const p_hs300x_data); /** Enter the programming mode. - * @par Implemented as - * - @ref RM_HS300X_ProgrammingModeEnter() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* programmingModeEnter)(rm_hs300x_ctrl_t * const p_ctrl); /** Change the sensor resolution. - * @par Implemented as - * - @ref RM_HS300X_ResolutionChange() * * @param[in] p_ctrl Pointer to control structure. * @param[in] data_type Data type of HS300X. @@ -193,8 +177,6 @@ typedef struct st_rm_hs300x_api rm_hs300x_resolution_t const resolution); /** Get the sensor ID. - * @par Implemented as - * - @ref RM_HS300X_SensorIdGet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_sensor_id Pointer to sensor ID of HS300X. @@ -202,16 +184,12 @@ typedef struct st_rm_hs300x_api fsp_err_t (* sensorIdGet)(rm_hs300x_ctrl_t * const p_ctrl, uint32_t * const p_sensor_id); /** Exit the programming mode. - * @par Implemented as - * - @ref RM_HS300X_ProgrammingModeExit() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* programmingModeExit)(rm_hs300x_ctrl_t * const p_ctrl); /** Close HS300X. - * @par Implemented as - * - @ref RM_HS300X_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_hs400x_api.h b/ra/fsp/inc/api/rm_hs400x_api.h index c7d67a5b3..31ee1a887 100644 --- a/ra/fsp/inc/api/rm_hs400x_api.h +++ b/ra/fsp/inc/api/rm_hs400x_api.h @@ -26,8 +26,6 @@ * @section RM_HS400X_API_Summary Summary * The HS400X interface provides HS400X functionality. * - * The HS400X interface can be implemented by: - * - @ref RM_HS400X * * @{ **********************************************************************************************************************/ @@ -152,8 +150,6 @@ typedef struct st_rm_hs400x_cfg } rm_hs400x_cfg_t; /** HS400X control block. Allocate an instance specific control block to pass into the HS400X API calls. - * @par Implemented as - * - rm_hs400x_instance_ctrl_t */ typedef void rm_hs400x_ctrl_t; @@ -161,8 +157,6 @@ typedef void rm_hs400x_ctrl_t; typedef struct st_rm_hs400x_api { /** Open sensor. - * @par Implemented as - * - @ref RM_HS400X_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -170,24 +164,18 @@ typedef struct st_rm_hs400x_api fsp_err_t (* open)(rm_hs400x_ctrl_t * const p_ctrl, rm_hs400x_cfg_t const * const p_cfg); /** Start one shot measurement. - * @par Implemented as - * - @ref RM_HS400X_MeasurementStart() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* measurementStart)(rm_hs400x_ctrl_t * const p_ctrl); /** Stop a period measurement. - * @par Implemented as - * - @ref RM_HS400X_MeasurementStop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* measurementStop)(rm_hs400x_ctrl_t * const p_ctrl); /** Read ADC data from HS400X. - * @par Implemented as - * - @ref RM_HS400X_Read() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -195,8 +183,6 @@ typedef struct st_rm_hs400x_api fsp_err_t (* read)(rm_hs400x_ctrl_t * const p_ctrl, rm_hs400x_raw_data_t * const p_raw_data); /** Calculate humidity and temperature values from ADC data. - * @par Implemented as - * - @ref RM_HS400X_DataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. @@ -206,8 +192,6 @@ typedef struct st_rm_hs400x_api rm_hs400x_data_t * const p_hs400x_data); /** Close HS400X. - * @par Implemented as - * - @ref RM_HS400X_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_littlefs_api.h b/ra/fsp/inc/api/rm_littlefs_api.h index ea4696a95..72373c739 100644 --- a/ra/fsp/inc/api/rm_littlefs_api.h +++ b/ra/fsp/inc/api/rm_littlefs_api.h @@ -30,8 +30,6 @@ * The LittleFS Port configures a fail-safe filesystem designed for microcontrollers on top of a lower level storage * device. * - * Implemented by: - * @ref RM_LITTLEFS_FLASH * * @{ **********************************************************************************************************************/ @@ -64,8 +62,6 @@ typedef struct st_rm_littlefs_cfg } rm_littlefs_cfg_t; /** LittleFS Port API control block. Allocate an instance specific control block to pass into the LittleFS Port API calls. - * @par Implemented as - * - @ref rm_littlefs_flash_instance_ctrl_t */ typedef void rm_littlefs_ctrl_t; @@ -73,8 +69,6 @@ typedef void rm_littlefs_ctrl_t; typedef struct st_rm_littlefs_api { /** Initialize The lower level storage device. - * @par Implemented as - * - @ref RM_LITTLEFS_FLASH_Open * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -82,8 +76,6 @@ typedef struct st_rm_littlefs_api fsp_err_t (* open)(rm_littlefs_ctrl_t * const p_ctrl, rm_littlefs_cfg_t const * const p_cfg); /** Closes the module and lower level storage device. - * @par Implemented as - * - @ref RM_LITTLEFS_FLASH_Close * * @param[in] p_ctrl Control block set in @ref rm_littlefs_api_t::open call. */ diff --git a/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h b/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h index e285fef2a..b0cf700b6 100644 --- a/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h +++ b/ra/fsp/inc/api/rm_mesh_bearer_platform_api.h @@ -29,8 +29,6 @@ * @section RM_MESH_BEARER_PLATFORM_API_Summary Summary * The BLE Mesh interface for the Bluetooth Low Energy Mesh Bearer Platform (BLE MESH BEARER PLATFORM) peripheral provides Bluetooth Low Energy Mesh Bearer Platform functionality. * - * The Bluetooth Low Energy Mesh Bearer Platform interface can be implemented by: - * - @ref RM_MESH_BEARER_PLATFORM * * @{ **********************************************************************************************************************/ @@ -85,8 +83,6 @@ typedef enum e_rm_mesh_bearer_platform_gatt_mode } rm_mesh_bearer_platform_gatt_mode_t; /** MESH BEARER PLATFORM control block. Allocate an instance specific control block to pass into the BLE MESH API calls. - * @par Implemented as - * - rm_mesh_bearer_platform_instance_ctrl_t */ typedef void rm_mesh_bearer_platform_ctrl_t; @@ -105,8 +101,6 @@ typedef struct st_rm_mesh_bearer_platform_cfg_t typedef struct st_rm_mesh_bearer_platform_api { /** Open Bearer Platform middleware. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -115,16 +109,12 @@ typedef struct st_rm_mesh_bearer_platform_api rm_mesh_bearer_platform_cfg_t const * const p_cfg); /** Close Bearer Platform middleware. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(rm_mesh_bearer_platform_ctrl_t * const p_ctrl); /** Set scan response data in connectable and scannable undirected advertising event. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_SetScanResponseData() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_data Pointer to scan response data. @@ -133,8 +123,6 @@ typedef struct st_rm_mesh_bearer_platform_api fsp_err_t (* setScanResponseData)(rm_mesh_bearer_platform_ctrl_t * const p_ctrl, uint8_t * p_data, uint8_t len); /** Request to create connection. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_Connect() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_remote_address Pointer to remote device address. @@ -145,8 +133,6 @@ typedef struct st_rm_mesh_bearer_platform_api uint8_t address_type, rm_mesh_bearer_platform_gatt_mode_t mode); /** Start service discovery for Mesh GATT service. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_DiscoverService() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Connection handle to identify device. @@ -156,8 +142,6 @@ typedef struct st_rm_mesh_bearer_platform_api rm_mesh_bearer_platform_gatt_mode_t mode); /** Configure GATT notification of Mesh GATT service. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_ConfigureNotification() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Connection handle to identify device. @@ -169,8 +153,6 @@ typedef struct st_rm_mesh_bearer_platform_api rm_mesh_bearer_platform_gatt_mode_t mode); /** Terminate Connection. - * @par Implemented as - * - @ref RM_MESH_BEARER_PLATFORM_Disconnect() * * @param[in] p_ctrl Pointer to control structure. * @param[in] handle Connection handle to identify device. diff --git a/ra/fsp/inc/api/rm_motor_120_control_api.h b/ra/fsp/inc/api/rm_motor_120_control_api.h index c9a55d067..028d69f14 100644 --- a/ra/fsp/inc/api/rm_motor_120_control_api.h +++ b/ra/fsp/inc/api/rm_motor_120_control_api.h @@ -26,9 +26,6 @@ * @section MOTOR_120_CONTROL_API_Summary Summary * The motor 120 control interface for speed calculation and setting, fixed cycle processing * - * The motor 120 control interface can be implemented by: - * - @ref MOTOR_120_CONTROL_SENSORLESS - * - @ref MOTOR_120_CONTROL_HALL * * @{ **********************************************************************************************************************/ @@ -153,9 +150,6 @@ typedef enum e_motor_120_control_voltage_ref } motor_120_control_voltage_ref_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_120_control_sensorless_instance_ctrl_t - * - motor_120_control_hall_instance_ctrl_t */ typedef void motor_120_control_ctrl_t; @@ -185,9 +179,6 @@ typedef struct st_motor_120_control_cfg typedef struct st_motor_120_control_api { /** Initialize the motor 120 control module. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_Open() - * - @ref RM_MOTOR_120_CONTROL_HALL_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -195,45 +186,30 @@ typedef struct st_motor_120_control_api fsp_err_t (* open)(motor_120_control_ctrl_t * const p_ctrl, motor_120_control_cfg_t const * const p_cfg); /** Close the motor 120 control module - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_Close() - * - @ref RM_MOTOR_120_CONTROL_HALL_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_120_control_ctrl_t * const p_ctrl); /** Run the motor 120 control module - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_Run() - * - @ref RM_MOTOR_120_CONTROL_HALL_Run() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* run)(motor_120_control_ctrl_t * const p_ctrl); /** Stop the motor 120 control module - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_Stop() - * - @ref RM_MOTOR_120_CONTROL_HALL_Stop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stop)(motor_120_control_ctrl_t * const p_ctrl); /** Reset variables of the motor 120 control module - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_Reset() - * - @ref RM_MOTOR_120_CONTROL_HALL_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_120_control_ctrl_t * const p_ctrl); /** Set speed[rpm] - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_SpeedSet() - * - @ref RM_MOTOR_120_CONTROL_HALL_SpeedSet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] speed_rpm Pointer to get speed data[rpm] @@ -241,9 +217,6 @@ typedef struct st_motor_120_control_api fsp_err_t (* speedSet)(motor_120_control_ctrl_t * const p_ctrl, float const speed_rpm); /** Get speed. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_SpeedGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_SpeedGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_speed_rpm Pointer to get speed data[rpm] @@ -251,9 +224,6 @@ typedef struct st_motor_120_control_api fsp_err_t (* speedGet)(motor_120_control_ctrl_t * const p_ctrl, float * const p_speed_rpm); /** Get phase current, Vdc and Va_max data. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_CurrentGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_CurrentGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_current_status Pointer to get data structure. @@ -262,9 +232,6 @@ typedef struct st_motor_120_control_api motor_120_driver_current_status_t * const p_current_status); /** Get wait stop flag. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_WaitStopFlagGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_WaitStopFlagGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_flag Pointer to wait stop flag @@ -273,9 +240,6 @@ typedef struct st_motor_120_control_api motor_120_control_wait_stop_flag_t * const p_flag); /** Get timerout error flag. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_TimeoutErrorFlagGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_TimeoutErrorFlagGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_timeout_error_flag Pointer to timeout error flag @@ -284,9 +248,6 @@ typedef struct st_motor_120_control_api motor_120_control_timeout_error_flag_t * const p_timeout_error_flag); /** Get pattern error flag. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_PatternErrorFlagGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_PatternErrorFlagGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_pattern_error_flag Pointer to pattern error flag @@ -295,9 +256,6 @@ typedef struct st_motor_120_control_api motor_120_control_pattern_error_flag_t * const p_pattern_error_flag); /** Get voltage ref. - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_VoltageRefGet() - * - @ref RM_MOTOR_120_CONTROL_HALL_VoltageRefGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_voltage_ref Pointer to flag voltage ref @@ -306,9 +264,6 @@ typedef struct st_motor_120_control_api motor_120_control_voltage_ref_t * const p_voltage_ref); /** Update configuration parameters for the calculation in the motor 120 control module - * @par Implemented as - * - @ref RM_MOTOR_120_CONTROL_SENSORLESS_ParameterUpdate() - * - @ref RM_MOTOR_120_CONTROL_HALL_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_120_driver_api.h b/ra/fsp/inc/api/rm_motor_120_driver_api.h index 070ce73c4..1c436902a 100644 --- a/ra/fsp/inc/api/rm_motor_120_driver_api.h +++ b/ra/fsp/inc/api/rm_motor_120_driver_api.h @@ -26,8 +26,6 @@ * @section MOTOR_120_DRIVER_API_Summary Summary * The MOTOR_120_DRIVER interface for setting the PWM modulation duty * - * The motor current control interface can be implemented by: - * - @ref MOTOR_120_DRIVER * * @{ **********************************************************************************************************************/ @@ -123,8 +121,6 @@ typedef struct st_motor_120_driver_current_status } motor_120_driver_current_status_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_120_driver_instance_ctrl_t */ typedef void motor_120_driver_ctrl_t; @@ -140,8 +136,6 @@ typedef struct st_motor_120_driver_cfg typedef struct st_motor_120_driver_api { /** Initialize the motor 120 driver module. - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -149,40 +143,30 @@ typedef struct st_motor_120_driver_api fsp_err_t (* open)(motor_120_driver_ctrl_t * const p_ctrl, motor_120_driver_cfg_t const * const p_cfg); /** Close the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_120_driver_ctrl_t * const p_ctrl); /** Run the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_Run() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* run)(motor_120_driver_ctrl_t * const p_ctrl); /** Stop the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_Stop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stop)(motor_120_driver_ctrl_t * const p_ctrl); /** Reset variables of the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_120_driver_ctrl_t * const p_ctrl); /** Set (Input) phase voltage data into the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_PhaseVoltageSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] u_voltage U phase voltage [V] @@ -193,8 +177,6 @@ typedef struct st_motor_120_driver_api float const w_voltage); /** Set phase voltage pattern the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_PhasePatternSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] pattern Voltage pattern @@ -203,8 +185,6 @@ typedef struct st_motor_120_driver_api motor_120_driver_phase_pattern_t const pattern); /** Get phase current, Vdc and Va_max data from the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_CurrentGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_current_status Pointer to get data structure. @@ -213,16 +193,12 @@ typedef struct st_motor_120_driver_api motor_120_driver_current_status_t * const p_current_status); /** current offset detection from the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_CurrentOffsetCalc() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* currentOffsetCalc)(motor_120_driver_ctrl_t * const p_ctrl); /** Get the flag of finish current offset detection from the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_FlagCurrentOffsetGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_flag_offset Flag of finish current offset detection @@ -231,8 +207,6 @@ typedef struct st_motor_120_driver_api motor_120_driver_flag_offset_calc_t * const p_flag_offset); /** Update configuration parameters for the calculation in the motor 120 driver module - * @par Implemented as - * - @ref RM_MOTOR_120_DRIVER_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_angle_api.h b/ra/fsp/inc/api/rm_motor_angle_api.h index 216318932..00740d0eb 100644 --- a/ra/fsp/inc/api/rm_motor_angle_api.h +++ b/ra/fsp/inc/api/rm_motor_angle_api.h @@ -26,11 +26,6 @@ * @section MOTOR_ANGLE_API_Summary Summary * The Motor angle interface calculates the rotor angle and rotational speed from other data. * - * The motor angle interface can be implemented by: - * - @ref MOTOR_ESTIMATE - * - @ref MOTOR_SENSE_ENCODER - * - @ref MOTOR_SENSE_INDUCTION - * - @ref MOTOR_SENSE_HALL * * @{ **********************************************************************************************************************/ @@ -57,8 +52,6 @@ FSP_HEADER **********************************************************************************************************************/ /** Motor Angle Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_angle_ctrl_t */ typedef void motor_angle_ctrl_t; @@ -129,11 +122,6 @@ typedef enum e_motor_angle_error typedef struct st_motor_angle_api { /** Initialize the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_Open() - * - @ref RM_MOTOR_SENSE_ENCODER_Open() - * - @ref RM_MOTOR_SENSE_INDUCTION_Open() - * - @ref RM_MOTOR_SENSE_HALL_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -141,33 +129,18 @@ typedef struct st_motor_angle_api fsp_err_t (* open)(motor_angle_ctrl_t * const p_ctrl, motor_angle_cfg_t const * const p_cfg); /** Close (Finish) the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_Close() - * - @ref RM_MOTOR_SENSE_ENCODER_Close() - * - @ref RM_MOTOR_SENSE_INDUCTION_Close() - * - @ref RM_MOTOR_SENSE_HALL_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_angle_ctrl_t * const p_ctrl); /** Reset the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_Reset() - * - @ref RM_MOTOR_SENSE_ENCODER_Reset() - * - @ref RM_MOTOR_SENSE_INDUCTION_Reset() - * - @ref RM_MOTOR_SENSE_HALL_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_angle_ctrl_t * const p_ctrl); /** Set (Input) Current & Voltage Reference data into the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_CurrentSet() - * - @ref RM_MOTOR_SENSE_ENCODER_CurrentSet() - * - @ref RM_MOTOR_SENSE_INDUCTION_CurrentSet() - * - @ref RM_MOTOR_SENSE_HALL_CurrentSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_st_current Pointer to current structure @@ -177,11 +150,6 @@ typedef struct st_motor_angle_api motor_angle_voltage_reference_t * const p_st_voltage); /** Set (Input) Speed Information into the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_SpeedSet() - * - @ref RM_MOTOR_SENSE_ENCODER_SpeedSet() - * - @ref RM_MOTOR_SENSE_INDUCTION_SpeedSet() - * - @ref RM_MOTOR_SENSE_HALL_SpeedSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] speed_ctrl Control reference of rotational speed [rad/s] @@ -190,11 +158,6 @@ typedef struct st_motor_angle_api fsp_err_t (* speedSet)(motor_angle_ctrl_t * const p_ctrl, float const speed_ctrl, float const damp_speed); /** Set the flag of PI Control runs. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_FlagPiCtrlSet() - * - @ref RM_MOTOR_SENSE_ENCODER_FlagPiCtrlSet() - * - @ref RM_MOTOR_SENSE_INDUCTION_FlagPiCtrlSet() - * - @ref RM_MOTOR_SENSE_HALL_FlagPiCtrlSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] flag_pi The flag of PI control runs @@ -202,22 +165,12 @@ typedef struct st_motor_angle_api fsp_err_t (* flagPiCtrlSet)(motor_angle_ctrl_t * const p_ctrl, uint32_t const flag_pi); /** Calculate internal parameters of encoder process. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_InternalCalculate() - * - @ref RM_MOTOR_SENSE_ENCODER_InternalCalculate() - * - @ref RM_MOTOR_SENSE_INDUCTION_InternalCalculate() - * - @ref RM_MOTOR_SENSE_HALL_InternalCalculate() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* internalCalculate)(motor_angle_ctrl_t * const p_ctrl); /** Get rotor angle and rotational speed from the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_AngleSpeedGet() - * - @ref RM_MOTOR_SENSE_ENCODER_AngleSpeedGet() - * - @ref RM_MOTOR_SENSE_INDUCTION_AngleSpeedGet() - * - @ref RM_MOTOR_SENSE_HALL_AngleSpeedGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_angl Memory address to get rotor angle data @@ -228,41 +181,24 @@ typedef struct st_motor_angle_api float * const p_phase_err); /** Angle Adjustment Process. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_AngleAdjust() - * - @ref RM_MOTOR_SENSE_ENCODER_AngleAdjust() - * - @ref RM_MOTOR_SENSE_INDUCTION_AngleAdjust() - * - @ref RM_MOTOR_SENSE_HALL_AngleAdjust() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* angleAdjust)(motor_angle_ctrl_t * const p_ctrl); /** DEPRECATED Encoder Cyclic Process. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_EncoderCyclic() - * - @ref RM_MOTOR_SENSE_ENCODER_EncoderCyclic() - * - @ref RM_MOTOR_SENSE_HALL_EncoderCyclic() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* encoderCyclic)(motor_angle_ctrl_t * const p_ctrl); /** Cyclic Process. please - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_CyclicProcess() - * - @ref RM_MOTOR_SENSE_ENCODER_CyclicProcess() - * - @ref RM_MOTOR_SENSE_INDUCTION_CyclicProcess() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* cyclicProcess)(motor_angle_ctrl_t * const p_ctrl); /** Set sensor A/D data into the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_SensorDataSet() - * - @ref RM_MOTOR_SENSE_ENCODER_SensorDataSet() - * - @ref RM_MOTOR_SENSE_INDUCTION_SensorDataSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_ad_data Pointer to A/D conversion data @@ -270,11 +206,6 @@ typedef struct st_motor_angle_api fsp_err_t (* sensorDataSet)(motor_angle_ctrl_t * const p_ctrl, motor_angle_ad_data_t * const p_ad_data); /** Get estimated d/q-axis component from the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_EstimatedComponentGet() - * - @ref RM_MOTOR_SENSE_ENCODER_EstimatedComponentGet() - * - @ref RM_MOTOR_SENSE_INDUCTION_EstimatedComponentGet() - * - @ref RM_MOTOR_SENSE_HALL_EstimatedComponentGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_ed Memory address to get estimated d-axis component @@ -283,11 +214,6 @@ typedef struct st_motor_angle_api fsp_err_t (* estimatedComponentGet)(motor_angle_ctrl_t * const p_ctrl, float * const p_ed, float * const p_eq); /** Get Encoder Calculate Information. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_InfoGet() - * - @ref RM_MOTOR_SENSE_ENCODER_InfoGet() - * - @ref RM_MOTOR_SENSE_INDUCTION_InfoGet() - * - @ref RM_MOTOR_SENSE_HALL_InfoGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Memory address to get angle internal information @@ -295,10 +221,6 @@ typedef struct st_motor_angle_api fsp_err_t (* infoGet)(motor_angle_ctrl_t * const p_ctrl, motor_angle_encoder_info_t * const p_info); /** Update Parameters for the calculation in the Motor_Angle. - * @par Implemented as - * - @ref RM_MOTOR_ESTIMATE_ParameterUpdate() - * - @ref RM_MOTOR_SENSE_ENCODER_ParameterUpdate() - * - @ref RM_MOTOR_SENSE_HALL_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_api.h b/ra/fsp/inc/api/rm_motor_api.h index 23716b3a3..32e883a69 100644 --- a/ra/fsp/inc/api/rm_motor_api.h +++ b/ra/fsp/inc/api/rm_motor_api.h @@ -26,12 +26,6 @@ * @section MOTOR_API_Summary Summary * The Motor interface provides Motor functionality. * - * Implemented by: - * - @ref MOTOR_SENSORLESS - * - @ref MOTOR_ENCODER - * - @ref MOTOR_HALL - * - @ref MOTOR_120_DEGREE - * - @ref MOTOR_INDUCTION * * @{ **********************************************************************************************************************/ @@ -112,8 +106,6 @@ typedef struct st_rm_motor_callback_args } motor_callback_args_t; /** Motor Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_instance_ctrl_t */ typedef void motor_ctrl_t; @@ -133,11 +125,6 @@ typedef struct st_motor_cfg typedef struct st_motor_api { /** Open driver. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_Open() - * - @ref RM_MOTOR_ENCODER_Open() - * - @ref RM_MOTOR_120_DEGREE_Open() - * - @ref RM_MOTOR_INDUCTION_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -145,55 +132,30 @@ typedef struct st_motor_api fsp_err_t (* open)(motor_ctrl_t * const p_ctrl, motor_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_Close() - * - @ref RM_MOTOR_ENCODER_Close() - * - @ref RM_MOTOR_120_DEGREE_Close() - * - @ref RM_MOTOR_INDUCTION_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_ctrl_t * const p_ctrl); /** Run the motor. (Start the motor rotation.) - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_Run() - * - @ref RM_MOTOR_ENCODER_Run() - * - @ref RM_MOTOR_120_DEGREE_Run() - * - @ref RM_MOTOR_INDUCTION_Run() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* run)(motor_ctrl_t * const p_ctrl); /** Stop the motor. (Stop the motor rotation.) - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_Stop() - * - @ref RM_MOTOR_ENCODER_Stop() - * - @ref RM_MOTOR_120_DEGREE_Stop() - * - @ref RM_MOTOR_INDUCTION_Stop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stop)(motor_ctrl_t * const p_ctrl); /** Reset the motor control. (Recover from the error status.) - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_Reset() - * - @ref RM_MOTOR_ENCODER_Reset() - * - @ref RM_MOTOR_120_DEGREE_Reset() - * - @ref RM_MOTOR_INDUCTION_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_ctrl_t * const p_ctrl); /** Set Error Information. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_ErrorSet() - * - @ref RM_MOTOR_ENCODER_ErrorSet() - * - @ref RM_MOTOR_120_DEGREE_ErrorSet() - * - @ref RM_MOTOR_INDUCTION_ErrorSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] error Happend error code @@ -201,11 +163,6 @@ typedef struct st_motor_api fsp_err_t (* errorSet)(motor_ctrl_t * const p_ctrl, motor_error_t const error); /** Set rotation speed. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_SpeedSet() - * - @ref RM_MOTOR_ENCODER_SpeedSet() - * - @ref RM_MOTOR_120_DEGREE_SpeedSet() - * - @ref RM_MOTOR_INDUCTION_SpeedSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] speed_rpm Required rotation speed [rpm] @@ -213,11 +170,6 @@ typedef struct st_motor_api fsp_err_t (* speedSet)(motor_ctrl_t * const p_ctrl, float const speed_rpm); /** Set reference position. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_PositionSet() - * - @ref RM_MOTOR_ENCODER_PositionSet() - * - @ref RM_MOTOR_120_DEGREE_PositionSet() - * - @ref RM_MOTOR_INDUCTION_PositionSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_position Pointer to set required data @@ -225,11 +177,6 @@ typedef struct st_motor_api fsp_err_t (* positionSet)(motor_ctrl_t * const p_ctrl, motor_speed_position_data_t const * const p_position); /** Get the motor control status. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_StatusGet() - * - @ref RM_MOTOR_ENCODER_StatusGet() - * - @ref RM_MOTOR_120_DEGREE_StatusGet() - * - @ref RM_MOTOR_INDUCTION_StatusGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_status Pointer to get the motor control status @@ -237,11 +184,6 @@ typedef struct st_motor_api fsp_err_t (* statusGet)(motor_ctrl_t * const p_ctrl, uint8_t * const p_status); /** Get the rotor angle. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_AngleGet() - * - @ref RM_MOTOR_ENCODER_AngleGet() - * - @ref RM_MOTOR_120_DEGREE_AngleGet() - * - @ref RM_MOTOR_INDUCTION_AngleGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_angle_rad Pointer to get the rotor angle [rad] @@ -249,11 +191,6 @@ typedef struct st_motor_api fsp_err_t (* angleGet)(motor_ctrl_t * const p_ctrl, float * const p_angle_rad); /** Get the rotation speed. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_SpeedGet() - * - @ref RM_MOTOR_ENCODER_SpeedGet() - * - @ref RM_MOTOR_120_DEGREE_SpeedGet() - * - @ref RM_MOTOR_INDUCTION_SpeedGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_speed_rpm Pointer to get the rotation speed [rpm] @@ -261,11 +198,6 @@ typedef struct st_motor_api fsp_err_t (* speedGet)(motor_ctrl_t * const p_ctrl, float * const p_speed_rpm); /** Get wait stop flag. - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_WaitStopFlagGet() - * - @ref RM_MOTOR_ENCODER_WaitStopFlagGet() - * - @ref RM_MOTOR_120_DEGREE_WaitStopFlagGet() - * - @ref RM_MOTOR_INDUCTION_WaitStopFlagGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_flag Pointer to wait stop flag @@ -273,11 +205,6 @@ typedef struct st_motor_api fsp_err_t (* waitStopFlagGet)(motor_ctrl_t * const p_ctrl, motor_wait_stop_flag_t * const p_flag); /** Check the error occurrence - * @par Implemented as - * - @ref RM_MOTOR_SENSORLESS_ErrorCheck() - * - @ref RM_MOTOR_ENCODER_ErrorCheck() - * - @ref RM_MOTOR_120_DEGREE_ErrorCheck() - * - @ref RM_MOTOR_INDUCTION_ErrorCheck() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_error Pointer to get occured error @@ -285,12 +212,6 @@ typedef struct st_motor_api fsp_err_t (* errorCheck)(motor_ctrl_t * const p_ctrl, uint16_t * const p_error); /** FunctionSelect. - * @par Implemented as - * - @ref RM_MOTOR_ENCODER_FunctionSelect() - * - @ref RM_MOTOR_INDUCTION_FunctionSelect() - * - @ref RM_MOTOR_SENSORLESS_FunctionSelect() - * - @ref RM_MOTOR_HALL_FunctionSelect() - * - @ref RM_MOTOR_120_DEGREE_FunctionSelect() * * @param[in] p_ctrl Pointer to control structure. * @param[in] function Selected function diff --git a/ra/fsp/inc/api/rm_motor_current_api.h b/ra/fsp/inc/api/rm_motor_current_api.h index 5f0fa5fd7..fb2e0b6f9 100644 --- a/ra/fsp/inc/api/rm_motor_current_api.h +++ b/ra/fsp/inc/api/rm_motor_current_api.h @@ -26,8 +26,6 @@ * @section MOTOR_CURRENT_API_Summary Summary * The Motor current interface for getting the PWM modulation duty from electric current and speed * - * The motor current control interface can be implemented by: - * - @ref MOTOR_CURRENT * * @{ **********************************************************************************************************************/ @@ -135,8 +133,6 @@ typedef struct st_motor_current_get_voltage } motor_current_get_voltage_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_current_ctrl_t */ typedef void motor_current_ctrl_t; @@ -160,8 +156,6 @@ typedef struct st_motor_current_cfg typedef struct st_motor_current_api { /** Initialize the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -169,32 +163,24 @@ typedef struct st_motor_current_api fsp_err_t (* open)(motor_current_ctrl_t * const p_ctrl, motor_current_cfg_t const * const p_cfg); /** Close (Finish) the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_current_ctrl_t * const p_ctrl); /** Reset variables for the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_current_ctrl_t * const p_ctrl); /** Activate the motor current control. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_Run() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* run)(motor_current_ctrl_t * const p_ctrl); /** Set (Input) parameters into the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_ParameterSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_st_input Pointer to input data structure(speed control output data) @@ -202,8 +188,6 @@ typedef struct st_motor_current_api fsp_err_t (* parameterSet)(motor_current_ctrl_t * const p_ctrl, motor_current_input_t const * const p_st_input); /** Set (Input) Current reference into the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_CurrentReferenceSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] id_reference D-axis current reference [A] @@ -213,8 +197,6 @@ typedef struct st_motor_current_api float const iq_reference); /** Set (Input) Speed & Phase data into the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_SpeedPhaseSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] speed_rad Rotational speed [rad/s] @@ -223,8 +205,6 @@ typedef struct st_motor_current_api fsp_err_t (* speedPhaseSet)(motor_current_ctrl_t * const p_ctrl, float const speed_rad, float const phase_rad); /** Set (Input) Current data into the motor current module. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_CurrentSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_st_current Pointer to input current structure @@ -235,8 +215,6 @@ typedef struct st_motor_current_api motor_current_input_voltage_t const * const p_st_voltage); /** Get (output) parameters from the motor current module - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_ParameterGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_st_output Pointer to output data structure(speed control input data) @@ -244,8 +222,6 @@ typedef struct st_motor_current_api fsp_err_t (* parameterGet)(motor_current_ctrl_t * const p_ctrl, motor_current_output_t * const p_st_output); /** Get d/q-axis current - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_CurrentGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_id Pointer to get d-axis current [A] @@ -254,8 +230,6 @@ typedef struct st_motor_current_api fsp_err_t (* currentGet)(motor_current_ctrl_t * const p_ctrl, float * const p_id, float * const p_iq); /** Get phase output voltage - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_PhaseVoltageGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_voltage Pointer to get voltages @@ -263,8 +237,6 @@ typedef struct st_motor_current_api fsp_err_t (* phaseVoltageGet)(motor_current_ctrl_t * const p_ctrl, motor_current_get_voltage_t * const p_voltage); /** Update parameters for the calculation in the motor current control. - * @par Implemented as - * - @ref RM_MOTOR_CURRENT_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_driver_api.h b/ra/fsp/inc/api/rm_motor_driver_api.h index 46b2ed4d9..f9b4a1bc1 100644 --- a/ra/fsp/inc/api/rm_motor_driver_api.h +++ b/ra/fsp/inc/api/rm_motor_driver_api.h @@ -26,8 +26,6 @@ * @section MOTOR_DRIVER_API_Summary Summary * The Motor driver interface for setting the PWM modulation duty * - * The motor current control interface can be implemented by: - * - @ref MOTOR_DRIVER * * @{ **********************************************************************************************************************/ @@ -93,8 +91,6 @@ typedef struct st_motor_driver_current_get } motor_driver_current_get_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_driver_ctrl_t */ typedef void motor_driver_ctrl_t; @@ -129,8 +125,6 @@ typedef struct st_motor_driver_cfg typedef struct st_motor_driver_api { /** Initialize the Motor Driver Module. - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -138,24 +132,18 @@ typedef struct st_motor_driver_api fsp_err_t (* open)(motor_driver_ctrl_t * const p_ctrl, motor_driver_cfg_t const * const p_cfg); /** Close the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_driver_ctrl_t * const p_ctrl); /** Reset variables of the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_driver_ctrl_t * const p_ctrl); /** Set (Input) Phase Voltage data into the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_PhaseVoltageSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] u_voltage U phase voltage [V] @@ -166,8 +154,6 @@ typedef struct st_motor_driver_api float const w_voltage); /** Get Phase current, Vdc and Va_max data from the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_CurrentGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_current_get Pointer to get data structure. @@ -175,8 +161,6 @@ typedef struct st_motor_driver_api fsp_err_t (* currentGet)(motor_driver_ctrl_t * const p_ctrl, motor_driver_current_get_t * const p_current_get); /** Get the flag of finish current offset detection from the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_FlagCurrentOffsetGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_flag_offset Flag of finish current offset detection @@ -184,16 +168,12 @@ typedef struct st_motor_driver_api fsp_err_t (* flagCurrentOffsetGet)(motor_driver_ctrl_t * const p_ctrl, uint8_t * const p_flag_offset); /** Restart current offset detection - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_CurrentOffsetRestart() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* currentOffsetRestart)(motor_driver_ctrl_t * const p_ctrl); /** Update Configuration Parameters for the calculation in the Motor Driver Module - * @par Implemented as - * - @ref RM_MOTOR_DRIVER_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h b/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h index 02537e822..4c932a00b 100644 --- a/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h +++ b/ra/fsp/inc/api/rm_motor_inertia_estimate_api.h @@ -26,8 +26,6 @@ * @section MOTOR_INERTIA_ESTIMATE_API_Summary Summary * The Motor interface provides Motor inertia estimate functionality. * - * Implemented by: - * - @ref MOTOR_INERTIA_ESTIMATE * * @{ **********************************************************************************************************************/ @@ -82,8 +80,6 @@ typedef struct st_motor_inertia_estimate_set_data } motor_inertia_estimate_set_data_t; /** Motor inertia estimate block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_inertia_estimate_instance_ctrl_t */ typedef void motor_inertia_estimate_ctrl_t; @@ -98,8 +94,6 @@ typedef struct st_motor_inertia_estimate_cfg typedef struct st_motor_inertia_estimate_api { /** Open driver. - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -107,40 +101,30 @@ typedef struct st_motor_inertia_estimate_api fsp_err_t (* open)(motor_inertia_estimate_ctrl_t * const p_ctrl, motor_inertia_estimate_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Start the function. - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_Start() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* start)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Stop( same as cancel ) the function. - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_Stop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stop)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Reset the function. (recover from error state) - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Get information from the function (to set speed & position control) - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_InfoGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Pointer to information @@ -148,8 +132,6 @@ typedef struct st_motor_inertia_estimate_api fsp_err_t (* infoGet)(motor_inertia_estimate_ctrl_t * const p_ctrl, motor_inertia_estimate_info_t * const p_info); /** Set the data to the function (from speed, position and current control) - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_DataSet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_set_data Pointer to set the data @@ -158,24 +140,18 @@ typedef struct st_motor_inertia_estimate_api motor_inertia_estimate_set_data_t * const p_set_data); /** Speed cyclic process of the function - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_SpeedCyclic() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* speedCyclic)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Current cyclic process of the function - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_CurrentCyclic() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* currentCyclic)(motor_inertia_estimate_ctrl_t * const p_ctrl); /** Update parameters for the function. - * @par Implemented as - * - @ref RM_MOTOR_INERTIA_ESTIMATE_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_position_api.h b/ra/fsp/inc/api/rm_motor_position_api.h index 89e603ce1..df86c0490 100644 --- a/ra/fsp/inc/api/rm_motor_position_api.h +++ b/ra/fsp/inc/api/rm_motor_position_api.h @@ -26,8 +26,6 @@ * @section MOTOR_POSITION_API_Summary Summary * The Motor position interface for getting the speed references from Encoder Sensor * - * The motor position interface can be implemented by: - * - @ref MOTOR_POSITION * * @{ **********************************************************************************************************************/ @@ -71,8 +69,6 @@ typedef struct e_motor_position_info } motor_position_info_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_position_ctrl_t */ typedef void motor_position_ctrl_t; @@ -87,8 +83,6 @@ typedef struct st_motor_position_cfg typedef struct st_motor_position_api { /** Initialize the Motor Position Module. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -96,24 +90,18 @@ typedef struct st_motor_position_api fsp_err_t (* open)(motor_position_ctrl_t * const p_ctrl, motor_position_cfg_t const * const p_cfg); /** Close (Finish) the Motor Position Module. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_position_ctrl_t * const p_ctrl); /** Reset(Stop) the Motor Position Module. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_position_ctrl_t * const p_ctrl); /** Get Position data. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_PositionGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_position Pointer to get position data @@ -121,8 +109,6 @@ typedef struct st_motor_position_api fsp_err_t (* positionGet)(motor_position_ctrl_t * const p_ctrl, int16_t * const p_position); /** Set Position data from Encoder. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_PositionSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] position_rad Position data [radian] @@ -130,8 +116,6 @@ typedef struct st_motor_position_api fsp_err_t (* positionSet)(motor_position_ctrl_t * const p_ctrl, float const position_rad); /** Set (Input) Position reference into the Motor Position Module. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_PositionReferenceSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] position_refernce_deg Position reference [degree] @@ -139,8 +123,6 @@ typedef struct st_motor_position_api fsp_err_t (* positionReferenceSet)(motor_position_ctrl_t * const p_ctrl, int16_t const position_reference_deg); /** Set (Input) Position Control Mode. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_ControlModeSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] mode Position Control Mode @@ -148,16 +130,12 @@ typedef struct st_motor_position_api fsp_err_t (* controlModeSet)(motor_position_ctrl_t * const p_ctrl, motor_position_ctrl_mode_t const mode); /** Calculate internal position reference - * @par Implemented as - * - @ref RM_MOTOR_POSITION_PositionControl() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* positionControl)(motor_position_ctrl_t * const p_ctrl); /** Calculate iq reference - * @par Implemented as - * - @ref RM_MOTOR_POSITION_IpdSpeedPControl() * * @param[in] p_ctrl Pointer to control structure. * @param[in] ref_speed_rad Speed Reference [rad/sec] @@ -168,8 +146,6 @@ typedef struct st_motor_position_api float const speed_rad, float * const p_iq_ref); /** Get Speed Reference by P Control - * @par Implemented as - * - @ref RM_MOTOR_POSITION_SpeedReferencePControlGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_speed_ref Pointer to get speed reference @@ -177,8 +153,6 @@ typedef struct st_motor_position_api fsp_err_t (* speedReferencePControlGet)(motor_position_ctrl_t * const p_ctrl, float * const p_speed_ref); /** Get Speed Reference by IPD Control - * @par Implemented as - * - @ref RM_MOTOR_POSITION_SpeedReferenceIpdControlGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_speed_ref Pointer to get speed reference @@ -187,8 +161,6 @@ typedef struct st_motor_position_api float * const p_speed_ref); /** Get Speed Reference by Speed Feedforward - * @par Implemented as - * - @ref RM_MOTOR_POSITION_SpeedReferenceFeedforwardGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_speed_ref Pointer to get speed reference @@ -196,8 +168,6 @@ typedef struct st_motor_position_api fsp_err_t (* speedReferenceFeedforwardGet)(motor_position_ctrl_t * const p_ctrl, float * const p_speed_ref); /** Get Position information. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_InfoGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Pointer to get information @@ -205,8 +175,6 @@ typedef struct st_motor_position_api fsp_err_t (* infoGet)(motor_position_ctrl_t * const p_ctrl, motor_position_info_t * const p_info); /** Update Parameters for the calculation in the Motor Position Module. - * @par Implemented as - * - @ref RM_MOTOR_POSITION_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_return_origin_api.h b/ra/fsp/inc/api/rm_motor_return_origin_api.h index e17960c5d..7eaef237d 100644 --- a/ra/fsp/inc/api/rm_motor_return_origin_api.h +++ b/ra/fsp/inc/api/rm_motor_return_origin_api.h @@ -26,8 +26,6 @@ * @section MOTOR_RETURN_ORIGIN_API_Summary Summary * The Motor interface provides Motor return origin functionality. * - * Implemented by: - * - @ref MOTOR_RETURN_ORIGIN * * @{ **********************************************************************************************************************/ @@ -89,8 +87,6 @@ typedef struct st_motor_return_origin_set_data } motor_return_origin_set_data_t; /** Motor return origin function block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_return_origin_instance_ctrl_t */ typedef void motor_return_origin_ctrl_t; @@ -107,8 +103,6 @@ typedef struct st_motor_return_origin_cfg typedef struct st_motor_return_origin_api { /** Open driver. - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -116,40 +110,30 @@ typedef struct st_motor_return_origin_api fsp_err_t (* open)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_cfg_t const * const p_cfg); /** Close driver. - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_return_origin_ctrl_t * const p_ctrl); /** Start the function. - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_Start() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* start)(motor_return_origin_ctrl_t * const p_ctrl); /** Stop the function. (Cancel the function works.) - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_Stop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* stop)(motor_return_origin_ctrl_t * const p_ctrl); /** Reset the function. (Initialize the function.) - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_return_origin_ctrl_t * const p_ctrl); /** Get the function information. - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_InfoGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_info Pointer to info @@ -157,8 +141,6 @@ typedef struct st_motor_return_origin_api fsp_err_t (* infoGet)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_info_t * const p_info); /** Set the data to the function - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_DataSet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_set_data Pointer to set the data @@ -166,16 +148,12 @@ typedef struct st_motor_return_origin_api fsp_err_t (* dataSet)(motor_return_origin_ctrl_t * const p_ctrl, motor_return_origin_set_data_t * const p_set_data); /** Speed cyclic process of the function - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_SpeedCyclic() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* speedCyclic)(motor_return_origin_ctrl_t * const p_ctrl); /** Update parameters for the function. - * @par Implemented as - * - @ref RM_MOTOR_RETURN_ORIGIN_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_motor_speed_api.h b/ra/fsp/inc/api/rm_motor_speed_api.h index 65481603a..59f1044dd 100644 --- a/ra/fsp/inc/api/rm_motor_speed_api.h +++ b/ra/fsp/inc/api/rm_motor_speed_api.h @@ -26,8 +26,6 @@ * @section MOTOR_SPEED_API_Summary Summary * The Motor speed interface for getting the current references from electric current and rotational speed * - * The motor speed interface can be implemented by: - * - @ref MOTOR_SPEED * * @{ **********************************************************************************************************************/ @@ -131,8 +129,6 @@ typedef struct st_motor_speed_position_data } motor_speed_position_data_t; /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - motor_speed_ctrl_t */ typedef void motor_speed_ctrl_t; @@ -157,8 +153,6 @@ typedef struct st_motor_speed_cfg typedef struct st_motor_speed_api { /** Initialize the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -166,32 +160,24 @@ typedef struct st_motor_speed_api fsp_err_t (* open)(motor_speed_ctrl_t * const p_ctrl, motor_speed_cfg_t const * const p_cfg); /** Close (Finish) the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(motor_speed_ctrl_t * const p_ctrl); /** Reset(Stop) the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_Reset() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* reset)(motor_speed_ctrl_t * const p_ctrl); /** Activate the motor speed control. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_Run() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* run)(motor_speed_ctrl_t * const p_ctrl); /** Set (Input) speed reference into the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_SpeedReferenceSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] speed_refernce_rpm Speed reference [rpm] @@ -199,8 +185,6 @@ typedef struct st_motor_speed_api fsp_err_t (* speedReferenceSet)(motor_speed_ctrl_t * const p_ctrl, float const speed_reference_rpm); /** Set (Input) position reference and control mode - * @par Implemented as - * - @ref RM_MOTOR_SPEED_PositionReferenceSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_position_data Pointer to structure position data @@ -209,8 +193,6 @@ typedef struct st_motor_speed_api motor_speed_position_data_t const * const p_position_data); /** Set (Input) speed parameters into the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_ParameterSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_st_input Pointer to structure to input parameters. @@ -218,16 +200,12 @@ typedef struct st_motor_speed_api fsp_err_t (* parameterSet)(motor_speed_ctrl_t * const p_ctrl, motor_speed_input_t const * const p_st_input); /** Calculate current reference - * @par Implemented as - * - @ref RM_MOTOR_SPEED_SpeedControl() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* speedControl)(motor_speed_ctrl_t * const p_ctrl); /** Get speed control output parameters - * @par Implemented as - * - @ref RM_MOTOR_SPEED_ParameterGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_st_output Pointer to get speed control parameters @@ -235,8 +213,6 @@ typedef struct st_motor_speed_api fsp_err_t (* parameterGet)(motor_speed_ctrl_t * const p_ctrl, motor_speed_output_t * const p_st_output); /** Update Parameters for the calculation in the motor speed module. - * @par Implemented as - * - @ref RM_MOTOR_SPEED_ParameterUpdate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure include update parameters. diff --git a/ra/fsp/inc/api/rm_ob1203_api.h b/ra/fsp/inc/api/rm_ob1203_api.h index cf481ec5a..27c6aea6c 100644 --- a/ra/fsp/inc/api/rm_ob1203_api.h +++ b/ra/fsp/inc/api/rm_ob1203_api.h @@ -26,8 +26,6 @@ * @section RM_OB1203_API_Summary Summary * The OB1203 interface provides OB1203 functionality. * - * The OB1203 interface can be implemented by: - * - @ref RM_OB1203 * * @{ **********************************************************************************************************************/ @@ -466,8 +464,6 @@ typedef struct st_rm_ob1203_cfg } rm_ob1203_cfg_t; /** OB1203 control block. Allocate an instance specific control block to pass into the OB1203 API calls. - * @par Implemented as - * - rm_ob1203_instance_ctrl_t */ typedef void rm_ob1203_ctrl_t; @@ -475,8 +471,6 @@ typedef void rm_ob1203_ctrl_t; typedef struct st_rm_ob1203_api { /** Open sensor. - * @par Implemented as - * - @ref RM_OB1203_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. @@ -484,8 +478,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* open)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_cfg_t const * const p_cfg); /** Start measurement. - * @par Implemented as - * - @ref RM_OB1203_MeasurementStart() * * @param[in] p_ctrl Pointer to control structure. * @param[in] mode Sensor mode. @@ -493,8 +485,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* measurementStart)(rm_ob1203_ctrl_t * const p_ctrl); /** Stop measurement. - * @par Implemented as - * - @ref RM_OB1203_MeasurementStop() * * @param[in] p_ctrl Pointer to control structure. * @param[in] mode Sensor mode. @@ -502,8 +492,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* measurementStop)(rm_ob1203_ctrl_t * const p_ctrl); /** Read Light ADC data from OB1203. - * @par Implemented as - * - @ref RM_OB1203_LightRead() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -513,8 +501,6 @@ typedef struct st_rm_ob1203_api rm_ob1203_light_data_type_t type); /** Calculate Light data from raw data. - * @par Implemented as - * - @ref RM_OB1203_LightDataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -524,8 +510,6 @@ typedef struct st_rm_ob1203_api rm_ob1203_light_data_t * const p_ob1203_data); /** Read Proximity ADC data from OB1203. - * @par Implemented as - * - @ref RM_OB1203_ProxRead() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -533,8 +517,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* proxRead)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_raw_data_t * const p_raw_data); /** Calculate Proximity data from raw data. - * @par Implemented as - * - @ref RM_OB1203_ProxDataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -544,8 +526,6 @@ typedef struct st_rm_ob1203_api rm_ob1203_prox_data_t * const p_ob1203_data); /** Read PPG ADC data from OB1203. - * @par Implemented as - * - @ref RM_OB1203_PpgRead() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -555,8 +535,6 @@ typedef struct st_rm_ob1203_api uint8_t const number_of_samples); /** Calculate PPG data from raw data. - * @par Implemented as - * - @ref RM_OB1203_PpgDataCalculate() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. @@ -566,8 +544,6 @@ typedef struct st_rm_ob1203_api rm_ob1203_ppg_data_t * const p_ob1203_data); /** Get device status. Read STATUS_0 and STATUS_1 registers. - * @par Implemented as - * - @ref RM_OB1203_DeviceStatusGet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_status Pointer to device status. @@ -575,8 +551,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* deviceStatusGet)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_device_status_t * const p_status); /** Set device interrupt configuration. - * @par Implemented as - * - @ref RM_OB1203_DeviceInterruptCfgSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] interrupt_cfg Device interrupt configuration. @@ -585,8 +559,6 @@ typedef struct st_rm_ob1203_api rm_ob1203_device_interrupt_cfg_t const interrupt_cfg); /** Set gain. - * @par Implemented as - * - @ref RM_OB1203_GainSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] gain Gain configuration. @@ -594,8 +566,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* gainSet)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_gain_t const gain); /** Set LED current value. - * @par Implemented as - * - @ref RM_OB1203_LedCurrentSet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] led_current Current value structure. @@ -603,8 +573,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* ledCurrentSet)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_led_current_t const led_current); /** Get FIFO information. - * @par Implemented as - * - @ref RM_OB1203_FifoInfoGet() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_fifo_info Pointer to FIFO information (write index, read index and overflow counter). @@ -612,8 +580,6 @@ typedef struct st_rm_ob1203_api fsp_err_t (* fifoInfoGet)(rm_ob1203_ctrl_t * const p_ctrl, rm_ob1203_fifo_info_t * const p_fifo_info); /** Close OB1203. - * @par Implemented as - * - @ref RM_OB1203_Close() * * @param[in] p_ctrl Pointer to control structure. */ diff --git a/ra/fsp/inc/api/rm_rai_data_collector_api.h b/ra/fsp/inc/api/rm_rai_data_collector_api.h index d9609f829..b054f2d28 100644 --- a/ra/fsp/inc/api/rm_rai_data_collector_api.h +++ b/ra/fsp/inc/api/rm_rai_data_collector_api.h @@ -30,8 +30,6 @@ * The rai data collector interface provides functionality to collect data from differnet channels using snapshot mode, * data feed mode or mixed mode. * - * Implemented by: - * - @ref RM_RAI_DATA_COLLECTOR * * @{ **********************************************************************************************************************/ @@ -142,8 +140,6 @@ typedef struct st_rai_data_collector_cfg } rai_data_collector_cfg_t; /** Data Collector control block. Allocate an instance specific control block to pass into the Data Collector API calls. - * @par Implemented as - * - @ref rai_data_collector_instance_ctrl_t */ typedef void rai_data_collector_ctrl_t; @@ -151,8 +147,6 @@ typedef void rai_data_collector_ctrl_t; typedef struct st_rai_data_collector_api { /** Initialize Data Collector module instance. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_Open() * * @note To reopen after calling this function, call @ref rai_data_collector_api_t::close first. * @param[in] p_ctrl Pointer to control handle structure @@ -161,20 +155,16 @@ typedef struct st_rai_data_collector_api fsp_err_t (* open)(rai_data_collector_ctrl_t * const p_ctrl, rai_data_collector_cfg_t const * const p_cfg); /** Config transfer source address for snapshot mode channel - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_SnapshotChannelRegister() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] p_src Pointer to transfer source address * */ - fsp_err_t (* snapshotChannelRegister)(rai_data_collector_ctrl_t * const p_api_ctrl, uint8_t channel, + fsp_err_t (* snapshotChannelRegister)(rai_data_collector_ctrl_t * const p_ctrl, uint8_t channel, void const * p_src); /** Release frame buffers by upper modules - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_BufferRelease() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] channel Which snapshot mode channel @@ -183,16 +173,12 @@ typedef struct st_rai_data_collector_api fsp_err_t (* bufferRelease)(rai_data_collector_ctrl_t * const p_ctrl); /** Reset internal buffers - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_BufferReset() * * @param[in] p_ctrl Pointer to control handle structure */ fsp_err_t (* bufferReset)(rai_data_collector_ctrl_t * const p_ctrl); /** Starts snapshot mode. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_SnapshotStart() * * @param[in] p_ctrl Pointer to control handle structure * @@ -200,8 +186,6 @@ typedef struct st_rai_data_collector_api fsp_err_t (* snapshotStart)(rai_data_collector_ctrl_t * const p_ctrl); /** Stops snapshot mode. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_SnapshotStop() * * @param[in] p_ctrl Pointer to control handle structure * @@ -209,19 +193,15 @@ typedef struct st_rai_data_collector_api fsp_err_t (* snapshotStop)(rai_data_collector_ctrl_t * const p_ctrl); /** Get the PING or PONG buffer address for data transfer. For data feed mode only. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_ChannelBufferGet() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] channel Which data feed mode channel * @param[out] pp_buf Returned buffer address * */ - fsp_err_t (* channelBufferGet)(rai_data_collector_ctrl_t * const p_api_ctrl, uint8_t channel, void ** pp_buf); + fsp_err_t (* channelBufferGet)(rai_data_collector_ctrl_t * const p_ctrl, uint8_t channel, void ** pp_buf); /** Write data to frame buffer using CPU copy. For data feed mode only. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_ChannelWrite() * * @param[in] p_ctrl Pointer to control handle structure * @param[in] channel Which data feed mode channel @@ -229,12 +209,10 @@ typedef struct st_rai_data_collector_api * @param[in] len Length of data buffer in data samples * */ - fsp_err_t (* channelWrite)(rai_data_collector_ctrl_t * const p_api_ctrl, uint8_t channel, const void * p_buf, + fsp_err_t (* channelWrite)(rai_data_collector_ctrl_t * const p_ctrl, uint8_t channel, const void * p_buf, uint32_t len); /** Close the specified Data Collector module instance. - * @par Implemented as - * - @ref RM_RAI_DATA_COLLECTOR_Close() * * @param[in] p_ctrl Pointer to control handle structure */ diff --git a/ra/fsp/inc/api/rm_rai_data_shipper_api.h b/ra/fsp/inc/api/rm_rai_data_shipper_api.h index 481a88a97..0c7584bd5 100644 --- a/ra/fsp/inc/api/rm_rai_data_shipper_api.h +++ b/ra/fsp/inc/api/rm_rai_data_shipper_api.h @@ -29,8 +29,6 @@ * @section RM_RAI_DATA_SHIPPER_API_SUMMARY Summary * The rai data shipper interface provides multiple communication methods. * - * Implemented by: - * - @ref RM_RAI_DATA_SHIPPER * * @{ **********************************************************************************************************************/ @@ -85,8 +83,6 @@ typedef struct st_rai_data_shipper_cfg } rai_data_shipper_cfg_t; /** Data Shipper control block. Allocate an instance specific control block to pass into the Data Shipper API calls. - * @par Implemented as - * - @ref rai_data_shipper_instance_ctrl_t */ typedef void rai_data_shipper_ctrl_t; @@ -94,8 +90,6 @@ typedef void rai_data_shipper_ctrl_t; typedef struct st_rai_data_shipper_api { /** Initialize Data Shipper module instance. - * @par Implemented as - * - @ref RM_RAI_DATA_SHIPPER_Open() * * @note To reopen after calling this function, call @ref rai_data_shipper_api_t::close first. * @param[in] p_ctrl Pointer to control handle structure @@ -104,28 +98,21 @@ typedef struct st_rai_data_shipper_api fsp_err_t (* open)(rai_data_shipper_ctrl_t * const p_ctrl, rai_data_shipper_cfg_t const * const p_cfg); /** Read data. - * @par Implemented as - * - @ref RM_RAI_DATA_SHIPPER_Read() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_buf Pointer to the location to store read data. * @param[in] buf_len Number of bytes to read. */ - fsp_err_t (* read)(rai_data_shipper_ctrl_t * const p_api_ctrl, void * const p_buf, uint32_t * const buf_len); + fsp_err_t (* read)(rai_data_shipper_ctrl_t * const p_ctrl, void * const p_buf, uint32_t * const buf_len); /** Write data. - * @par Implemented as - * - @ref RM_RAI_DATA_SHIPPER_Write() * * @param[in] p_ctrl Pointer to control structure. * @param[in] write_params Pointer to write parameters structure */ - fsp_err_t (* write)(rai_data_shipper_ctrl_t * const p_api_ctrl, - rai_data_shipper_write_params_t const * p_write_params); + fsp_err_t (* write)(rai_data_shipper_ctrl_t * const p_ctrl, rai_data_shipper_write_params_t const * p_write_params); /** Close the specified Data Shipper module instance. - * @par Implemented as - * - @ref RM_RAI_DATA_SHIPPER_Close() * * @param[in] p_ctrl Pointer to control handle structure */ diff --git a/ra/fsp/inc/api/rm_touch_api.h b/ra/fsp/inc/api/rm_touch_api.h index ca22efc0a..e5c8f2fd5 100644 --- a/ra/fsp/inc/api/rm_touch_api.h +++ b/ra/fsp/inc/api/rm_touch_api.h @@ -26,8 +26,6 @@ * @section TOUCH_API_Summary Summary * The TOUCH interface provides TOUCH functionality. * - * The TOUCH interface can be implemented by: - * - @ref TOUCH * * @{ **********************************************************************************************************************/ @@ -59,8 +57,6 @@ FSP_HEADER **********************************************************************************************************************/ /** Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - touch_instance_ctrl_t */ typedef void touch_ctrl_t; @@ -138,8 +134,6 @@ typedef struct st_touch_sensitivity_info typedef struct st_touch_api { /** Open driver. - * @par Implemented as - * - @ref RM_TOUCH_Open() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to pin configuration structure. @@ -147,16 +141,12 @@ typedef struct st_touch_api fsp_err_t (* open)(touch_ctrl_t * const p_ctrl, touch_cfg_t const * const p_cfg); /** Scan start. - * @par Implemented as - * - @ref RM_TOUCH_ScanStart() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* scanStart)(touch_ctrl_t * const p_ctrl); /** Data get. - * @par Implemented as - * - @ref RM_TOUCH_DataGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_button_status Pointer to get data bitmap. @@ -167,16 +157,12 @@ typedef struct st_touch_api uint16_t * p_wheel_position); /** ScanStop. - * @par Implemented as - * - @ref RM_TOUCH_ScanStop() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* scanStop)(ctsu_ctrl_t * const p_ctrl); /** pad data get. - * @par Implemented as - * - @ref RM_TOUCH_PadDataGet() * * @param[in] p_ctrl Pointer to control structure. * @param[out] p_pad_rx_coordinate Pointer to get coordinate of receiver side. @@ -187,8 +173,6 @@ typedef struct st_touch_api uint16_t * p_pad_tx_coordinate, uint8_t * p_pad_num_touch); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref RM_TOUCH_CallbackSet() * * @param[in] p_ctrl Pointer to the CTSU control block. * @param[in] p_callback Callback function @@ -196,20 +180,16 @@ typedef struct st_touch_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(touch_ctrl_t * const p_api_ctrl, void (* p_callback)(touch_callback_args_t *), + fsp_err_t (* callbackSet)(touch_ctrl_t * const p_ctrl, void (* p_callback)(touch_callback_args_t *), void const * const p_context, touch_callback_args_t * const p_callback_memory); /** Close driver. - * @par Implemented as - * - @ref RM_TOUCH_Close() * * @param[in] p_ctrl Pointer to control structure. */ fsp_err_t (* close)(touch_ctrl_t * const p_ctrl); /** Sensitivity ratio get. - * @par Implemented as - * - @ref RM_TOUCH_SensitivityRatioGet() * * @param[in] p_ctrl Pointer to control structure. * @param[in,out] p_touch_sensitivity_info Pointer to touch sensitivity structure. @@ -217,8 +197,6 @@ typedef struct st_touch_api fsp_err_t (* sensitivityRatioGet)(touch_ctrl_t * const p_ctrl, touch_sensitivity_info_t * p_touch_sensitivity_info); /** Threshold adjust. - * @par Implemented as - * - @ref RM_TOUCH_ThresholdAdjust() * * @param[in] p_ctrl Pointer to control structure. * @param[in] p_touch_sensitivity_info Pointer to touch sensitivity structure. @@ -226,8 +204,6 @@ typedef struct st_touch_api fsp_err_t (* thresholdAdjust)(touch_ctrl_t * const p_ctrl, touch_sensitivity_info_t * p_touch_sensitivity_info); /** Drift control. - * @par Implemented as - * - @ref RM_TOUCH_DriftControl() * * @param[in] p_ctrl Pointer to control structure. * @param[in] input_drift_freq Drift frequency value. diff --git a/ra/fsp/inc/api/rm_vee_api.h b/ra/fsp/inc/api/rm_vee_api.h index 5890677cf..9a9c90c21 100644 --- a/ra/fsp/inc/api/rm_vee_api.h +++ b/ra/fsp/inc/api/rm_vee_api.h @@ -30,8 +30,6 @@ * The Virtual EEPROM Port configures a fail-safe key value store designed for microcontrollers on top of a lower * level storage device. * - * Implemented by: - * @ref RM_VEE_FLASH * * @{ **********************************************************************************************************************/ @@ -94,8 +92,6 @@ typedef struct st_rm_vee_status } rm_vee_status_t; /** Virtual EEPROM API control block. Allocate an instance specific control block to pass into the VEE API calls. - * @par Implemented as - * - @ref rm_vee_flash_instance_ctrl_t */ typedef void rm_vee_ctrl_t; @@ -103,8 +99,6 @@ typedef void rm_vee_ctrl_t; typedef struct st_rm_vee_api { /** Initializes the driver’s internal structures and opens the Flash driver. - * @par Implemented as - * - @ref RM_VEE_FLASH_Open * * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. @@ -112,8 +106,6 @@ typedef struct st_rm_vee_api fsp_err_t (* open)(rm_vee_ctrl_t * const p_ctrl, rm_vee_cfg_t const * const p_cfg); /** Writes a record to data flash. - * @par Implemented as - * - @ref RM_VEE_FLASH_RecordWrite * * @param[in] p_ctrl Pointer to control block. * @param[in] rec_id ID of record to write. @@ -124,8 +116,6 @@ typedef struct st_rm_vee_api uint32_t num_bytes); /** This function gets the pointer to the most recent version of a record specified by ID. - * @par Implemented as - * - @ref RM_VEE_FLASH_RecordPtrGet * * @param[in] p_ctrl Pointer to control block. * @param[in] rec_id ID of record to locate. @@ -136,8 +126,6 @@ typedef struct st_rm_vee_api uint32_t * const p_num_bytes); /** Writes new Reference data to the reference update area. - * @par Implemented as - * - @ref RM_VEE_FLASH_RefDataWrite * * @param[in] p_ctrl Pointer to control block. * @param[in] p_ref_data Pointer to data to write to the reference data update area. @@ -145,8 +133,6 @@ typedef struct st_rm_vee_api fsp_err_t (* refDataWrite)(rm_vee_ctrl_t * const p_ctrl, uint8_t const * const p_ref_data); /** Gets a pointer to the most recent reference data. - * @par Implemented as - * - @ref RM_VEE_FLASH_RefDataPtrGet * * @param[in] p_ctrl Pointer to control block. * @param[in] pp_ref_data Pointer to set to the most recent valid reference data. @@ -154,8 +140,6 @@ typedef struct st_rm_vee_api fsp_err_t (* refDataPtrGet)(rm_vee_ctrl_t * const p_ctrl, uint8_t ** const pp_ref_data); /** Get the current status of the VEE driver. - * @par Implemented as - * - @ref RM_VEE_FLASH_StatusGet * * @param[in] p_ctrl Pointer to control block. * @param[in] p_status Pointer to store the current status of the VEE driver. @@ -163,16 +147,12 @@ typedef struct st_rm_vee_api fsp_err_t (* statusGet)(rm_vee_ctrl_t * const p_ctrl, rm_vee_status_t * const p_status); /** Manually start a refresh operation. - * @par Implemented as - * - @ref RM_VEE_FLASH_Refresh * * @param[in] p_ctrl Pointer to control block. */ fsp_err_t (* refresh)(rm_vee_ctrl_t * const p_ctrl); /** Format the Virtual EEPROM. - * @par Implemented as - * - @ref RM_VEE_FLASH_Format * * @param[in] p_ctrl Pointer to control block. * @param[in] p_ref_data Optional pointer to reference data to write during format. @@ -180,8 +160,6 @@ typedef struct st_rm_vee_api fsp_err_t (* format)(rm_vee_ctrl_t * const p_ctrl, uint8_t const * const p_ref_data); /** Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - @ref RM_VEE_FLASH_CallbackSet() * * @param[in] p_ctrl Control block set in @ref rm_vee_api_t::open call. * @param[in] p_callback Callback function to register @@ -189,12 +167,10 @@ typedef struct st_rm_vee_api * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. * Callback arguments allocated here are only valid during the callback. */ - fsp_err_t (* callbackSet)(rm_vee_ctrl_t * const p_api_ctrl, void (* p_callback)(rm_vee_callback_args_t *), + fsp_err_t (* callbackSet)(rm_vee_ctrl_t * const p_ctrl, void (* p_callback)(rm_vee_callback_args_t *), void const * const p_context, rm_vee_callback_args_t * const p_callback_memory); /** Closes the module and lower level storage device. - * @par Implemented as - * - @ref RM_VEE_FLASH_Close * * @param[in] p_ctrl Control block set in @ref rm_vee_api_t::open call. */ diff --git a/ra/fsp/inc/api/rm_zmod4xxx_api.h b/ra/fsp/inc/api/rm_zmod4xxx_api.h index 9ab0b3cc0..749d1a5b4 100644 --- a/ra/fsp/inc/api/rm_zmod4xxx_api.h +++ b/ra/fsp/inc/api/rm_zmod4xxx_api.h @@ -26,8 +26,6 @@ * @section RM_ZMOD4XXX_API_Summary Summary * The ZMOD4XXX interface provides ZMOD4XXX functionality. * - * The ZMOD4XXX interface can be implemented by: - * - @ref RM_ZMOD4XXX * * @{ **********************************************************************************************************************/ @@ -191,8 +189,6 @@ typedef struct st_rm_zmod4xxx_cfg } rm_zmod4xxx_cfg_t; /** ZMOD4xxx Control block. Allocate an instance specific control block to pass into the API calls. - * @par Implemented as - * - rm_zmod4xxx_instance_ctrl_t */ typedef void rm_zmod4xxx_ctrl_t; @@ -200,176 +196,137 @@ typedef void rm_zmod4xxx_ctrl_t; typedef struct st_rm_zmod4xxx_api { /** Open sensor. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Open() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_cfg Pointer to configuration structure. */ - fsp_err_t (* open)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_cfg_t const * const p_cfg); + fsp_err_t (* open)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_cfg_t const * const p_cfg); /** Start measurement - * @par Implemented as - * - @ref RM_ZMOD4XXX_MeasurementStart() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* measurementStart)(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + fsp_err_t (* measurementStart)(rm_zmod4xxx_ctrl_t * const p_ctrl); /** Stop measurement - * @par Implemented as - * - @ref RM_ZMOD4XXX_MeasurementStop() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* measurementStop)(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + fsp_err_t (* measurementStop)(rm_zmod4xxx_ctrl_t * const p_ctrl); /** Read status of the sensor - * @par Implemented as - * - @ref RM_ZMOD4XXX_StatusCheck() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* statusCheck)(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + fsp_err_t (* statusCheck)(rm_zmod4xxx_ctrl_t * const p_ctrl); /** Read ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Read() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data structure. */ - fsp_err_t (* read)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data); + fsp_err_t (* read)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data); /** Calculate IAQ 1st Gen. values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Iaq1stGenDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* iaq1stGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, - rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* iaq1stGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_iaq_1st_data_t * const p_zmod4xxx_data); /** Calculate IAQ 2nd Gen. values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Iaq2ndGenDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* iaq2ndGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, - rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* iaq2ndGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_iaq_2nd_data_t * const p_zmod4xxx_data); /** Calculate Odor values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_OdorDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* odorDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* odorDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_odor_data_t * const p_zmod4xxx_data); /** Calculate Sulfur Odor values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_SulfurOdorDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* sulfurOdorDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, - rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* sulfurOdorDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_sulfur_odor_data_t * const p_zmod4xxx_data); /** Calculate OAQ 1st Gen. values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Oaq1stGenDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* oaq1stGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, - rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* oaq1stGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_oaq_1st_data_t * const p_zmod4xxx_data); /** Calculate OAQ 2nd Gen. values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_Oaq2ndGenDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* oaq2ndGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, - rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* oaq2ndGenDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_oaq_2nd_data_t * const p_zmod4xxx_data); /** Calculate RAQ values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_RaqDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* raqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* raqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_raq_data_t * const p_zmod4xxx_data); /** Calculate Relative IAQ values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_RelIaqDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* relIaqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* relIaqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_rel_iaq_data_t * const p_zmod4xxx_data); /** Calculate PBAQ values from ADC data. - * @par Implemented as - * - @ref RM_ZMOD4XXX_PbaqDataCalculate() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] p_raw_data Pointer to raw data. * @param[in] p_zmod4xxx_data Pointer to ZMOD4XXXX data structure. */ - fsp_err_t (* pbaqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, + fsp_err_t (* pbaqDataCalculate)(rm_zmod4xxx_ctrl_t * const p_ctrl, rm_zmod4xxx_raw_data_t * const p_raw_data, rm_zmod4xxx_pbaq_data_t * const p_zmod4xxx_data); /** Set temperature and humidity. - * @par Implemented as - * - @ref RM_ZMOD4XXX_TemperatureAndHumiditySet() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. * @param[in] temperature Temperature (deg C). * @param[in] humidity Humidity (percent). */ - fsp_err_t (* temperatureAndHumiditySet)(rm_zmod4xxx_ctrl_t * const p_api_ctrl, float temperature, float humidity); + fsp_err_t (* temperatureAndHumiditySet)(rm_zmod4xxx_ctrl_t * const p_ctrl, float temperature, float humidity); /** Check device error event. - * @par Implemented as - * - @ref RM_ZMOD4XXX_DeviceErrorCheck() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* deviceErrorCheck)(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + fsp_err_t (* deviceErrorCheck)(rm_zmod4xxx_ctrl_t * const p_ctrl); /** Close the sensor - * @par Implemented as - * - @ref RM_ZMOD4XXX_Close() * - * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_ctrl Pointer to control structure. */ - fsp_err_t (* close)(rm_zmod4xxx_ctrl_t * const p_api_ctrl); + fsp_err_t (* close)(rm_zmod4xxx_ctrl_t * const p_ctrl); } rm_zmod4xxx_api_t; /** ZMOD4XXX instance */ diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 0850eb73d..a35315706 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -42,10 +42,10 @@ extern "C" { **********************************************************************************************************************/ /** FSP pack major version. */ - #define FSP_VERSION_MAJOR (4U) + #define FSP_VERSION_MAJOR (5U) /** FSP pack minor version. */ - #define FSP_VERSION_MINOR (6U) + #define FSP_VERSION_MINOR (0U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -54,10 +54,10 @@ extern "C" { #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("4.6.0") + #define FSP_VERSION_STRING ("5.0.0") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.6.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.0.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc_b.h b/ra/fsp/inc/instances/r_adc_b.h index 0b689629c..f8331fead 100644 --- a/ra/fsp/inc/instances/r_adc_b.h +++ b/ra/fsp/inc/instances/r_adc_b.h @@ -544,7 +544,7 @@ typedef struct st_adc_b_isr_cfg } adc_b_isr_cfg_t; /** ADC extended configuration data */ -typedef __PACKED_STRUCT st_adc_b_extended_cfg +typedef struct st_adc_b_extended_cfg { /* Data used to calculate register settings */ adc_b_pga_gain_t pga_gain[4]; ///< PGA Gain selection diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h index d53d78ab7..3481e3429 100644 --- a/ra/fsp/inc/instances/r_agt.h +++ b/ra/fsp/inc/instances/r_agt.h @@ -67,6 +67,7 @@ typedef enum e_agt_clock AGT_CLOCK_SUBCLOCK = 0x60, ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed AGT_CLOCK_P402 = 0x92, ///< Counts events on P402, events are counted in deep software standby mode AGT_CLOCK_P403 = 0x93, ///< Counts events on P403, events are counted in deep software standby mode + AGT_CLOCK_P404 = 0x91, ///< Counts events on P404, events are counted in deep software standby mode AGT_CLOCK_AGTIO = 0x80, ///< Counts events on AGTIOn, events are not counted in software standby modes } agt_clock_t; diff --git a/ra/fsp/inc/instances/r_cac.h b/ra/fsp/inc/instances/r_cac.h index e1e80edf5..d0a075b63 100644 --- a/ra/fsp/inc/instances/r_cac.h +++ b/ra/fsp/inc/instances/r_cac.h @@ -74,7 +74,7 @@ extern const cac_api_t g_cac_on_cac; fsp_err_t R_CAC_Open(cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg); fsp_err_t R_CAC_StartMeasurement(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_StopMeasurement(cac_ctrl_t * const p_ctrl); -fsp_err_t R_CAC_Read(cac_ctrl_t * const p_ctrl, uint16_t * const p_counter); +fsp_err_t R_CAC_Read(cac_ctrl_t * const p_ctrl, uint32_t * const p_counter); fsp_err_t R_CAC_Close(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_CallbackSet(cac_ctrl_t * const p_ctrl, void ( * p_callback)(cac_callback_args_t *), diff --git a/ra/fsp/inc/instances/r_ceu.h b/ra/fsp/inc/instances/r_ceu.h new file mode 100644 index 000000000..a0336d1c6 --- /dev/null +++ b/ra/fsp/inc/instances/r_ceu.h @@ -0,0 +1,182 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup CEU + * @{ + **********************************************************************************************************************/ + +#ifndef R_CEU_H +#define R_CEU_H + +#include "bsp_api.h" +#include "r_capture_api.h" +#include "r_ceu.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Capture mode */ +typedef enum e_ceu_capture_mode +{ + CEU_CAPTURE_MODE_SINGLE = 0U, ///< Single image capture + CEU_CAPTURE_MODE_CONTINUOUS = 1U, ///< Continuous image capture +} ceu_capture_mode_t; + +/** Data bus width */ +typedef enum e_ceu_data_bus_size +{ + CEU_DATA_BUS_SIZE_8_BIT = 0U, ///< Data bus is 8-bit + CEU_DATA_BUS_SIZE_16_BIT = 1U, ///< Data bus is 16-bit +} ceu_data_bus_size_t; + +/** Polarity of input HSYNC signal */ +typedef enum e_ceu_hsync_polarity +{ + CEU_HSYNC_POLARITY_HIGH = 0U, ///< HSYNC signal is active high + CEU_HSYNC_POLARITY_LOW = 1U, ///< HSYNC signal is active low +} ceu_hsync_polarity_t; + +/** Polarity of input VSYNC signal */ +typedef enum e_ceu_vsync_polarity +{ + CEU_VSYNC_POLARITY_HIGH = 0U, ///< VSYNC signal is active high + CEU_VSYNC_POLARITY_LOW = 1U, ///< VSYNC signal is active low +} ceu_vsync_polarity_t; + +typedef enum e_ceu_burst_transfer_mode +{ + CEU_BURST_TRANSFER_MODE_X1 = (0u), ///< Transferred to the bus in 32-byte units */ + CEU_BURST_TRANSFER_MODE_X2 = (1u), ///< Transferred to the bus in 64-byte units */ + CEU_BURST_TRANSFER_MODE_X4 = (2u), ///< Transferred to the bus in 128-byte units */ + CEU_BURST_TRANSFER_MODE_X8 = (3u) ///< Transferred to the bus in 256-byte units */ +} ceu_burst_transfer_mode_t; + +typedef enum e_ceu_event +{ + CEU_EVENT_NONE = 0x00000000, // No event, default state + CEU_EVENT_FRAME_END = 0x00000001, ///< Frame end event (CPE) + CEU_EVENT_HD = 0x00000100, ///< (Not Used) HD received (HD) + CEU_EVENT_VD = 0x00000200, ///< VD received (VD) + CEU_EVENT_CRAM_OVERFLOW = 0x00010000, ///< Data overflowed in the CRAM buffer (CDTOF) + CEU_EVENT_HD_MISMATCH = 0x00020000, ///< HD mismatch (IGHS) + CEU_EVENT_VD_MISMATCH = 0x00040000, ///< VD mismatch (IGVS) + CEU_EVENT_VD_ERROR = 0x00100000, ///< Invalid VD condition (VBP) + CEU_EVENT_FIREWALL = 0x00800000, ///< Data write address exceeds firewall (FWF) + CEU_EVENT_HD_MISSING = 0x01000000, ///< HD was expected but not input (NHD) + CEU_EVENT_VD_MISSING = 0x02000000, ///< VD was expected but not input (NVD) +} ceu_event_t; + +/** Capture mode for CEU. */ +typedef enum e_ceu_capture_format +{ + CEU_CAPTURE_FORMAT_DATA_SYNCHRONOUS = 0x1, ///< Raw formatted data. + CEU_CAPTURE_FORMAT_DATA_ENABLE = 0x2 ///< JPG formatted data +} ceu_capture_format_t; + +/** Swap bits configuration */ +typedef struct st_ceu_byte_swapping_t +{ + uint8_t swap_8bit_units : 1; ///< Byte swapping in 8-bit units + uint8_t swap_16bit_units : 1; ///< Byte swapping in 16-bit units + uint8_t swap_32bit_units : 1; ///< Byte swapping in 32-bit units +} ceu_byte_swapping_t; + +/** Edge information for latching signals */ +typedef struct st_ceu_edge_info_t +{ + uint8_t dsel : 1; ///< Sets the edge for fetching the image data (D15 to D0) from an external module. + uint8_t hdsel : 1; ///< Sets the edge for capturing hd from external module. + uint8_t vdsel : 1; ///< Sets the edge for capturing vd from external module. +} ceu_edge_info_t; + +/** Extended configuration structure for CEU. */ +typedef struct st_ceu_extended_cfg +{ + ceu_capture_format_t capture_format; ///< Capture format for incoming data + ceu_data_bus_size_t data_bus_width; ///< Size of camera data bus + ceu_edge_info_t edge_info; + ceu_hsync_polarity_t hsync_polarity; ///< Polarity of HSYNC input + ceu_vsync_polarity_t vsync_polarity; ///< Polarity of VSYNC input + uint32_t image_area_size; ///< Image capture size. Used when setting firewall address for Data Enable Fetch mode. + ceu_byte_swapping_t byte_swapping; ///< Controls byte swapping in 8-bit, 16-bit and 32-bit units + ceu_burst_transfer_mode_t burst_mode; ///< Bus transfer data size + uint32_t interrupts_enabled; ///< Enabled interrupt events bit mask + uint8_t ceu_ipl; ///< PDC interrupt priority + IRQn_Type ceu_irq; ///< PDC IRQ number +} ceu_extended_cfg_t; + +/** CEU instance control block. DO NOT INITIALIZE. */ +typedef struct st_ceu_instance_ctrl +{ + capture_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Indicates whether or not the driver is open called. + uint8_t * p_buffer; // Pointer to buffer currently in use + uint32_t image_area_size; // Size of capture area for image (Used for Data Enable Fetch) + uint32_t interrupts_enabled; // Interrupts enabled bitmask + void (* p_callback)(capture_callback_args_t *); // Pointer to callback that is called when an ceu_event_t occurs. + capture_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void const * p_context; // Pointer to context to be passed into callback function +} ceu_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const capture_api_t g_ceu_on_capture; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CEU_Open(capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg); + +fsp_err_t R_CEU_Close(capture_ctrl_t * const p_ctrl); + +fsp_err_t R_CEU_CaptureStart(capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer); + +fsp_err_t R_CEU_CallbackSet(capture_ctrl_t * const p_ctrl, + void ( * p_callback)(capture_callback_args_t *), + void const * const p_context, + capture_callback_args_t * const p_callback_memory); + +fsp_err_t R_CEU_StatusGet(capture_ctrl_t * const p_ctrl, capture_status_t * p_status); + +typedef uint32_t my_uint_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CEU_H + +/*******************************************************************************************************************//** + * @} (end defgroup CEU) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_cgc.h b/ra/fsp/inc/instances/r_cgc.h index 0421aa2ac..852f6d4e0 100644 --- a/ra/fsp/inc/instances/r_cgc.h +++ b/ra/fsp/inc/instances/r_cgc.h @@ -54,8 +54,29 @@ typedef struct st_cgc_instance_ctrl /** Placeholder for user data. Passed to the user callback in ::cgc_callback_args_t. */ void const * p_context; +#if BSP_FEATURE_CGC_HAS_OSTDCSE + void const * p_extend; +#endif } cgc_instance_ctrl_t; +#if BSP_FEATURE_CGC_HAS_OSTDCSE + +/** CGC extend configuration */ +typedef struct s_cgc_extended_cfg_t +{ + bool ostd_enable; /// , "Project Includes" + ******************************************************************************/ +#include "r_usb_hcdc_cfg.h" +#include "r_usb_basic_api.h" +#include "r_usb_hcdc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +fsp_err_t R_USB_HCDC_ControlDataRead(usb_ctrl_t * const p_api_ctrl, + uint8_t * p_buf, + uint32_t size, + uint8_t device_address); +fsp_err_t R_USB_HCDC_SpecificDeviceRegister(usb_ctrl_t * const p_api_ctrl, uint16_t vendor_id, uint16_t product_id); +fsp_err_t R_USB_HCDC_DeviceInfoGet(usb_ctrl_t * const p_api_ctrl, + usb_hcdc_device_info_t * p_info, + uint8_t device_address); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* USB_HCDC_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup USB_HCDC) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_at_transport_da16xxx.h b/ra/fsp/inc/instances/rm_at_transport_da16xxx.h new file mode 100644 index 000000000..02806adc0 --- /dev/null +++ b/ra/fsp/inc/instances/rm_at_transport_da16xxx.h @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup RM_AT_TRANSPORT_DA16XXX_API DA16XXX AT Command Transport Layer + * @brief Abstraction interface for DA16XXX AT Command functions. + * + * @section RM_DA16XXX_TRANSPORT_API_Summary Summary + * The DA16XXX AT Command Transport Layer interface provides functions for data communication and buffer handling over multiple communications interfaces. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef RM_AT_TRANSPORT_DA16XXX_API_H_ +#define RM_AT_TRANSPORT_DA16XXX_API_H_ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__ICCRX__) || defined(__RX__) + #include "platform.h" +#elif defined(__CCRL__) || defined(__ICCRL78__) || defined(__RL78__) + #include + #include + #include "r_cg_macrodriver.h" + #include "r_fsp_error.h" +#else + #include "bsp_api.h" + #include "rm_at_transport_da16xxx_uart_cfg.h" +#endif + +#if defined(__CCRX__) || defined(__ICCRX__) || defined(__RX__) +#elif defined(__CCRL__) || defined(__ICCRL78__) || defined(__RL78__) +#else + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Error Response Codes */ +#define AT_TRANSPORT_DA16XXX_ERR_UNKNOWN_CMD (-1) +#define AT_TRANSPORT_DA16XXX_ERR_INSUF_PARAMS (-2) +#define AT_TRANSPORT_DA16XXX_ERR_TOO_MANY_PARAMS (-3) +#define AT_TRANSPORT_DA16XXX_ERR_INVALID_PARAM (-4) +#define AT_TRANSPORT_DA16XXX_ERR_UNSUPPORTED_FUN (-5) +#define AT_TRANSPORT_DA16XXX_ERR_NOT_CONNECTED_AP (-6) +#define AT_TRANSPORT_DA16XXX_ERR_NO_RESULT (-7) +#define AT_TRANSPORT_DA16XXX_ERR_RESP_BUF_OVERFLOW (-8) +#define AT_TRANSPORT_DA16XXX_ERR_FUNC_NOT_CONFIG (-9) +#define AT_TRANSPORT_DA16XXX_ERR_CMD_TIMEOUT (-10) +#define AT_TRANSPORT_DA16XXX_ERR_NVRAM_WR_FAIL (-11) +#define AT_TRANSPORT_DA16XXX_ERR_RETEN_MEM_WR_FAIL (-12) +#define AT_TRANSPORT_DA16XXX_ERR_UNKNOWN (-99) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Event in the callback function */ +typedef enum e_at_transport_da16xxx_event +{ + AT_TRANSPORT_RX_BYTE_EVENT, +} at_transport_da16xxx_event_t; + +/** DA16xxx middleware callback parameter definition */ +typedef struct st_at_transport_da16xxx_callback_args +{ + void const * p_context; + at_transport_da16xxx_event_t event; + uint8_t data; +} at_transport_da16xxx_callback_args_t; + +/** DA16xxx middleware configuration block */ +typedef struct st_at_transport_da16xxx_cfg +{ + void const * p_extend; ///< Pointer to extended configuration by instance of interface. + void const * p_context; ///< Pointer to the user-provided context + bool (* p_callback)(at_transport_da16xxx_callback_args_t * p_args); ///< Pointer to callback function. +} at_transport_da16xxx_cfg_t; + +/** DA16xxx data structure */ +typedef struct st_at_transport_da16xxx_data_t +{ + uint8_t * p_at_cmd_string; ///< Pointer to ATCMD string. + uint32_t at_cmd_string_length; ///< ATCMD string length. + uint8_t * p_response_buffer; ///< Pointer to ATCMD response buffer. + uint32_t response_buffer_size; ///< ATCMD response buffer string length. + uint32_t timeout_ms; ///< ATCMD timeout in ms. + const char * p_expect_code; ///< Expected string in the ATCMD response. + uint32_t comm_ch_id; ///< Communication channel ID. +} at_transport_da16xxx_data_t; + +/** DA16xxx status indicators */ +typedef struct st_at_transport_da16xxx_status +{ + bool open; ///< True if driver is open +} at_transport_da16xxx_status_t; + +/** At transport control block. Allocate an instance specific control block to pass into the Communications API calls. + */ +typedef void at_transport_da16xxx_ctrl_t; + +/** AT Command APIs */ +typedef struct st_at_transport_da16xxx_api +{ + /** Open at cmd instance. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(at_transport_da16xxx_ctrl_t * const p_ctrl, at_transport_da16xxx_cfg_t const * const p_cfg); + + /** Close at cmd instance. + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(at_transport_da16xxx_ctrl_t * const p_ctrl); + + /** at cmd send thread safe. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_at_cmd Pointer to AT command data structure. + */ + fsp_err_t (* atCommandSendThreadSafe)(at_transport_da16xxx_ctrl_t * const p_ctrl, + at_transport_da16xxx_data_t * p_at_cmd); + + /** at cmd send. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_at_cmd Pointer to AT command data structure. + */ + fsp_err_t (* atCommandSend)(at_transport_da16xxx_ctrl_t * const p_ctrl, at_transport_da16xxx_data_t * p_at_cmd); + + /** Give the mutex. + * @param[in] p_ctrl Pointer to Transport layer instance control structure. + * @param[in] mutex_flag TX/RX Flags for the mutex. + */ + fsp_err_t (* giveMutex)(at_transport_da16xxx_ctrl_t * const p_ctrl, uint32_t mutex_flag); + + /** Take the mutex . + * @param[in] p_ctrl Pointer to Transport layer instance control structure. + * @param[in] mutex_flag TX/RX Flags for the mutex. + */ + fsp_err_t (* takeMutex)(at_transport_da16xxx_ctrl_t * const p_ctrl, uint32_t mutex_flag); + + /** Gets the status of the configured DA16xxx transport. + * + * @param[in] p_ctrl Pointer to the to Transport layer instance control structure. + * @param[out] p_status Pointer to store current status. + */ + fsp_err_t (* statusGet)(at_transport_da16xxx_ctrl_t * const p_ctrl, at_transport_da16xxx_status_t * p_status); + + /** Receive data from stream buffer. + * @param[in] p_ctrl Pointer to Transport layer instance control structure. + * @param[in] p_data Pointer to data. + * @param[in] length Data length. + * @param[in] rx_timeout Timeout for receiving data on the buffer. + * @param[in] trigger_level Trigger level for stream buffer. + */ + size_t (* bufferRecv)(at_transport_da16xxx_ctrl_t * const p_ctrl, const char * p_data, uint32_t length, + uint32_t rx_timeout); +} at_transport_da16xxx_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_at_transport_da16xxx_instance +{ + at_transport_da16xxx_ctrl_t * p_ctrl; + at_transport_da16xxx_cfg_t * p_cfg; + at_transport_da16xxx_api_t const * p_api; +} at_transport_da16xxx_instance_t; + +#if defined(__CCRX__) || defined(__ICCRX__) || defined(__RX__) +#elif defined(__CCRL__) || defined(__ICCRL78__) || defined(__RL78__) +#else + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_FOOTER +#endif + +#endif /* RM_AT_TRANSPORT_DA16XXX_API_H_ */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RM_AT_TRANSPORT_DA16XXX_API_H_) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_at_transport_da16xxx_uart.h b/ra/fsp/inc/instances/rm_at_transport_da16xxx_uart.h new file mode 100644 index 000000000..8afa136af --- /dev/null +++ b/ra/fsp/inc/instances/rm_at_transport_da16xxx_uart.h @@ -0,0 +1,97 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup AT_TRANSPORT_DA16XXX_UART + * @{ + **********************************************************************************************************************/ +#ifndef RM_AT_TRANSPORT_DA16XXX_H +#define RM_AT_TRANSPORT_DA16XXX_H + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +#include "r_uart_api.h" +#include "r_ioport_api.h" +#include "r_ioport.h" +#include "rm_at_transport_da16xxx.h" + +#include "FreeRTOS.h" +#include "semphr.h" +#include "stream_buffer.h" +#include "rm_at_transport_da16xxx_uart_cfg.h" + +/** User configuration structure, used in open function */ +typedef struct st_da16xxx_extended_transport_cfg +{ + const uint32_t num_uarts; ///< Number of UART interfaces to use + const uart_instance_t * uart_instances[AT_TRANSPORT_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< SCI UART instances + const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module +} at_transport_da16xxx_extended_cfg_t; + +/** AT_TRANSPORT_DA16XXX private control block. DO NOT MODIFY. */ +typedef struct st_da16xxx_transport_instance_ctrl +{ + at_transport_da16xxx_cfg_t const * p_cfg; ///< Pointer to initial configurations. + uint32_t num_uarts; ///< number of UARTS currently used for communication with module + uint32_t curr_cmd_port; ///< Current UART instance index for AT commands + uint32_t open; ///< Flag to indicate if transport instance has been initialized + + uint8_t cmd_rx_queue_buf[AT_TRANSPORT_DA16XXX_CFG_CMD_RX_BUF_SIZE]; ///< Command port receive buffer used by byte queue // FreeRTOS + StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle + StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info + + SemaphoreHandle_t tx_sem; ///< Transmit binary semaphore handle + SemaphoreHandle_t rx_sem; ///< Receive binary semaphore handle + + uart_instance_t * uart_instance_objects[AT_TRANSPORT_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART instance object + SemaphoreHandle_t uart_tei_sem[AT_TRANSPORT_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART transmission end binary semaphore + const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module + + /* Pointer to callback and optional working memory */ + bool (* p_callback)(at_transport_da16xxx_callback_args_t * p_args); ///< Pointer to callback function. + void const * p_context; ///< Pointer to the user-provided context +} at_transport_da16xxx_instance_ctrl_t; + +extern const char * g_at_transport_da16xxx_uart_cmd_baud; +extern at_transport_da16xxx_api_t const g_at_transport_da16xxx_on_uart; +void rm_at_transport_da16xxx_uart_callback(uart_callback_args_t * p_args); + +fsp_err_t rm_at_transport_da16xxx_uartOpen(at_transport_da16xxx_ctrl_t * const p_ctrl, + at_transport_da16xxx_cfg_t const * const p_cfg); +fsp_err_t rm_at_transport_da16xxx_uart_atCommandSendThreadSafe(at_transport_da16xxx_ctrl_t * const p_ctrl, + at_transport_da16xxx_data_t * p_at_cmd); +fsp_err_t rm_at_transport_da16xxx_uart_atCommandSend(at_transport_da16xxx_ctrl_t * const p_ctrl, + at_transport_da16xxx_data_t * p_at_cmd); +fsp_err_t rm_at_transport_da16xxx_uart_giveMutex(at_transport_da16xxx_ctrl_t * const p_ctrl, uint32_t mutex_flag); +fsp_err_t rm_at_transport_da16xxx_uart_takeMutex(at_transport_da16xxx_ctrl_t * const p_ctrl, uint32_t mutex_flag); +size_t rm_at_transport_da16xxx_uart_bufferRecv(at_transport_da16xxx_ctrl_t * const p_ctrl, + const char * p_data, + uint32_t length, + uint32_t rx_timeout); +fsp_err_t rm_at_transport_da16xxx_statusGet(at_transport_da16xxx_ctrl_t * const p_ctrl, + at_transport_da16xxx_status_t * p_status); +fsp_err_t rm_at_transport_da16xxx_uartClose(at_transport_da16xxx_ctrl_t * const p_ctrl); + +#endif // RM_AT_TRANSPORT_DA16XXX_H + +/*******************************************************************************************************************//** + * @} (end addtogroup AT_TRANSPORT_DA16XXX) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h index 97329ba31..7d43f97fa 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_battery_clt.h @@ -125,9 +125,6 @@ fsp_err_t RM_MESH_GENERIC_BATTERY_CLT_Close(rm_ble_mesh_model_client_ctrl_t * co fsp_err_t RM_MESH_GENERIC_BATTERY_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); -fsp_err_t RM_MESH_GENERIC_BATTERY_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_BATTERY_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h index c649b473f..8b19a745d 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_dtt_clt.h @@ -116,10 +116,6 @@ fsp_err_t RM_MESH_GENERIC_DTT_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_DTT_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_DTT_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_DTT_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_DTT_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h index fed745d39..cfe64139e 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_level_clt.h @@ -196,10 +196,6 @@ fsp_err_t RM_MESH_GENERIC_LEVEL_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_LEVEL_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_LEVEL_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_LEVEL_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_LEVEL_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h index 7b838d821..cecb2ab21 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_loc_clt.h @@ -182,10 +182,6 @@ fsp_err_t RM_MESH_GENERIC_LOC_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_LOC_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_LOC_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_LOC_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_LOC_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h index 1dc41c85c..b723a235e 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_on_off_clt.h @@ -129,10 +129,6 @@ fsp_err_t RM_MESH_GENERIC_ON_OFF_CLT_Open(rm_ble_mesh_model_client_ctrl_t * cons fsp_err_t RM_MESH_GENERIC_ON_OFF_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_ON_OFF_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_ON_OFF_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_ON_OFF_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h index be31023dc..9491cf362 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_pl_clt.h @@ -183,10 +183,6 @@ fsp_err_t RM_MESH_GENERIC_PL_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_PL_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_PL_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_PL_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_PL_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h index 19ce079d2..5d467ddf7 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_poo_clt.h @@ -89,10 +89,6 @@ fsp_err_t RM_MESH_GENERIC_POO_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_POO_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_POO_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_POO_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_POO_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h b/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h index b43928ff2..9aca95d5d 100644 --- a/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_generic_prop_clt.h @@ -268,10 +268,6 @@ fsp_err_t RM_MESH_GENERIC_PROP_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_GENERIC_PROP_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_GENERIC_PROP_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_GENERIC_PROP_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_GENERIC_PROP_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_health_clt.h b/ra/fsp/inc/instances/rm_mesh_health_clt.h index 7d6cb2df1..d02e18559 100644 --- a/ra/fsp/inc/instances/rm_mesh_health_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_health_clt.h @@ -132,10 +132,6 @@ fsp_err_t RM_MESH_HEALTH_CLIENT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ fsp_err_t RM_MESH_HEALTH_CLIENT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const p_model_handle); - -fsp_err_t RM_MESH_HEALTH_CLIENT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_HEALTH_CLIENT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h index 24ddaf446..4f01d8b3a 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_light_ctl_clt.h @@ -266,10 +266,6 @@ fsp_err_t RM_MESH_LIGHT_CTL_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_LIGHT_CTL_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_CTL_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_LIGHT_CTL_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_LIGHT_CTL_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h index a2fdfdcf4..75dc49ada 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_light_hsl_clt.h @@ -356,10 +356,6 @@ fsp_err_t RM_MESH_LIGHT_HSL_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_LIGHT_HSL_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_HSL_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_LIGHT_HSL_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_LIGHT_HSL_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h b/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h index 39bb04c28..08191e975 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_light_lc_clt.h @@ -183,10 +183,6 @@ fsp_err_t RM_MESH_LIGHT_LC_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_LIGHT_LC_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_LC_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_LIGHT_LC_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_LIGHT_LC_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h b/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h index 210055c58..f578d786b 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_light_lightness_clt.h @@ -247,10 +247,6 @@ fsp_err_t RM_MESH_LIGHT_LIGHTNESS_CLT_Open(rm_ble_mesh_model_client_ctrl_t * con fsp_err_t RM_MESH_LIGHT_LIGHTNESS_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_LIGHTNESS_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_LIGHT_LIGHTNESS_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_LIGHT_LIGHTNESS_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h b/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h index 96e4042e5..577e7c25d 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_light_xyl_clt.h @@ -238,10 +238,6 @@ fsp_err_t RM_MESH_LIGHT_XYL_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_LIGHT_XYL_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_XYL_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_LIGHT_XYL_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_LIGHT_XYL_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_scene_clt.h b/ra/fsp/inc/instances/rm_mesh_scene_clt.h index 981c82ad7..992f81877 100644 --- a/ra/fsp/inc/instances/rm_mesh_scene_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_scene_clt.h @@ -159,10 +159,6 @@ fsp_err_t RM_MESH_SCENE_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const p_ fsp_err_t RM_MESH_SCENE_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_SCENE_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_SCENE_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_SCENE_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h b/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h index 08cdd75d2..336d264d6 100644 --- a/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_scheduler_clt.h @@ -166,10 +166,6 @@ fsp_err_t RM_MESH_SCHEDULER_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const fsp_err_t RM_MESH_SCHEDULER_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_SCHEDULER_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_SCHEDULER_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_SCHEDULER_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_sensor_clt.h b/ra/fsp/inc/instances/rm_mesh_sensor_clt.h index efe9daed8..c9f3a2cbe 100644 --- a/ra/fsp/inc/instances/rm_mesh_sensor_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_sensor_clt.h @@ -400,10 +400,6 @@ fsp_err_t RM_MESH_SENSOR_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const p fsp_err_t RM_MESH_SENSOR_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_SENSOR_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_SENSOR_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_SENSOR_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mesh_time_clt.h b/ra/fsp/inc/instances/rm_mesh_time_clt.h index 3379eb90d..ed69761bd 100644 --- a/ra/fsp/inc/instances/rm_mesh_time_clt.h +++ b/ra/fsp/inc/instances/rm_mesh_time_clt.h @@ -166,10 +166,6 @@ fsp_err_t RM_MESH_TIME_CLT_Open(rm_ble_mesh_model_client_ctrl_t * const p_c fsp_err_t RM_MESH_TIME_CLT_Close(rm_ble_mesh_model_client_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_TIME_CLT_GetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, rm_ble_mesh_access_model_handle_t * const model_handle); - -fsp_err_t RM_MESH_TIME_CLT_SetModelHandle(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, - rm_ble_mesh_access_model_handle_t model_handle); - fsp_err_t RM_MESH_TIME_CLT_SendReliablePdu(rm_ble_mesh_model_client_ctrl_t * const p_ctrl, uint32_t req_opcode, void const * const parameter, diff --git a/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h b/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h index 7e2c7fe8b..4a41bd193 100644 --- a/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h +++ b/ra/fsp/inc/instances/rm_mqtt_onchip_da16xxx.h @@ -30,6 +30,8 @@ #include #include +#include "rm_wifi_da16xxx.h" +#include "rm_at_transport_da16xxx.h" #include "rm_mqtt_onchip_da16xxx_cfg.h" #define MQTT_ONCHIP_DA16XXX_MAX_ALPN (3) ///< Maximum number of ALPNs supported by DA16XXX. @@ -96,6 +98,7 @@ typedef struct st_mqtt_onchip_da16xxx_callback_args /** MQTT Configuration */ typedef struct st_mqtt_onchip_da16xxx_cfg { + at_transport_da16xxx_instance_t const * p_transport_instance; const uint8_t use_mqtt_v311; ///< Flag to use MQTT v3.1.1. const uint16_t rx_timeout; ///< MQTT Rx timeout in milliseconds. const uint16_t tx_timeout; ///< MQTT Tx timeout in milliseconds. diff --git a/ra/fsp/inc/instances/rm_wifi_da16xxx.h b/ra/fsp/inc/instances/rm_wifi_da16xxx.h new file mode 100644 index 000000000..edec8dfaa --- /dev/null +++ b/ra/fsp/inc/instances/rm_wifi_da16xxx.h @@ -0,0 +1,258 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup WIFI_DA16XXX WIFI_DA16XXX + * @{ + **********************************************************************************************************************/ +#ifndef RM_WIFI_DA16XXX_H +#define RM_WIFI_DA16XXX_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include +#include +#include +#include "bsp_api.h" +#include "time.h" + +#include "r_ioport_api.h" +#include "r_ioport.h" +#include "r_uart_api.h" + +/* DA16XXX transport includes. */ +#include "rm_at_transport_da16xxx.h" + +#include "FreeRTOS.h" +#include "semphr.h" +#include "stream_buffer.h" +#include "rm_wifi_config.h" +#include "rm_wifi_api.h" +#include "rm_wifi_da16xxx_cfg.h" + +/** + * @brief Max SSID length + */ +#ifndef wificonfigMAX_SSID_LEN + #define wificonfigMAX_SSID_LEN 32 +#endif + +/** + * @brief Max BSSID length + */ +#ifndef wificonfigMAX_BSSID_LEN + #define wificonfigMAX_BSSID_LEN 6 +#endif + +/** + * @brief Max passphrase length + */ +#ifndef wificonfigMAX_PASSPHRASE_LEN + #define wificonfigMAX_PASSPHRASE_LEN 32 +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Encryption Type supported by DA16XXX module */ +#define WIFI_DA16XXX_TKIP_ENC_TYPE (0) +#define WIFI_DA16XXX_AES_ENC_TYPE (1) +#define WIFI_DA16XXX_TKIP_AES_ENC_TYPE (2) + +#define SOCKETS_IPPROTO_V4_DA16XXX (4) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DA16XXX WiFi module enable/disable for SNTP */ +typedef enum e_wifi_da16xxx_sntp_enable +{ + WIFI_DA16XXX_SNTP_DISABLE = 0, + WIFI_DA16XXX_SNTP_ENABLE = 1 +} wifi_da16xxx_sntp_enable_t; + +/** DA16XXX Wifi socket status types */ +typedef enum e_da16xxx_socket_status +{ + WIFI_DA16XXX_SOCKET_STATUS_CLOSED = 0, + WIFI_DA16XXX_SOCKET_STATUS_SOCKET, + WIFI_DA16XXX_SOCKET_STATUS_BOUND, + WIFI_DA16XXX_SOCKET_STATUS_LISTEN, + WIFI_DA16XXX_SOCKET_STATUS_CONNECTED +} da16xxx_socket_status_t; + +/** DA16XXX socket shutdown channels */ +typedef enum e_da16xxx_socket_rw +{ + WIFI_DA16XXX_SOCKET_READ = 1, + WIFI_DA16XXX_SOCKET_WRITE = 2 +} da16xxx_socket_rw; + +/** DA16XXX socket receive state */ +typedef enum e_da16xxx_recv_state +{ + WIFI_DA16XXX_RECV_PREFIX, // + + WIFI_DA16XXX_RECV_CMD, // command + WIFI_DA16XXX_RECV_SUFFIX, // : + WIFI_DA16XXX_RECV_PARAM_CID, // cid parameter + WIFI_DA16XXX_RECV_PARAM_IP, // ip parameter + WIFI_DA16XXX_RECV_PARAM_PORT, // port parameter + WIFI_DA16XXX_RECV_PARAM_LEN, // length parameter + WIFI_DA16XXX_RECV_DATA +} da16xxx_recv_state; + +/** DA16XXX WiFi module enable/disable for SNTP Daylight */ +typedef enum e_wifi_da16xxx_sntp_daylight_savings_enable +{ + WIFI_DA16XXX_SNTP_DAYLIGHT_SAVINGS_DISABLE = 0, + WIFI_DA16XXX_SNTP_DAYLIGHT_SAVINGS_ENABLE = 1, +} wifi_da16xxx_sntp_daylight_savings_enable_t; + +/** User configuration structure, used in open function */ +typedef struct st_wifi_cfg +{ + at_transport_da16xxx_instance_t const * p_transport_instance; + const uint32_t num_sockets; ///< Number of sockets to initialize + const uint8_t * country_code; ///< Country code defined in ISO3166-1 alpha-2 standard + const uint8_t * sntp_server_ip; ///< The SNTP server IP address string + const int32_t sntp_utc_offset_in_hours; ///< Timezone offset in secs (-43200 - 43200) + void const * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< Pointer to extended configuration by instance of interface. +} wifi_da16xxx_cfg_t; + +/** DA16XXX Wifi internal socket instance structure */ +typedef struct +{ + uint8_t remote_ipaddr[4]; ///< Remote IP address + int remote_port; ///< Remote Port + int socket_recv_data_len; ///< Data length of incoming socket data + int socket_type; ///< Socket type (TCP Server | TCP Client | UDP) + uint32_t socket_status; ///< Current socket status + uint32_t socket_recv_error_count; ///< Socket receive error count + uint32_t socket_create_flag; ///< Flag to determine in socket has been created. + uint32_t socket_read_write_flag; ///< flag to determine if read and/or write channels are active. + da16xxx_recv_state socket_recv_state; ///< Incoming Socket data header information + + StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle + StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info + uint8_t socket_recv_buff[WIFI_DA16XXX_CFG_MAX_SOCKET_RX_SIZE]; ///< Socket receive buffer used by byte queue +} da16xxx_socket_t; + +/** WIFI_DA16XXX private control block. DO NOT MODIFY. */ +typedef struct st_wifi_da16xxx_instance_ctrl +{ + wifi_da16xxx_cfg_t const * p_wifi_da16xxx_cfg; ///< Pointer to initial configurations. + uint32_t num_creatable_sockets; ///< Number of simultaneous sockets supported + uint32_t curr_socket; ///< Current Socket index for AT commands + uint32_t open; ///< Flag to indicate if wifi instance has been initialized + uint8_t is_sntp_enabled; ///< Flag to indicate Enable/Disable of SNTP Client + + uint8_t cmd_tx_buff[WIFI_DA16XXX_CFG_CMD_TX_BUF_SIZE]; ///< Command send buffer + uint8_t cmd_rx_buff[WIFI_DA16XXX_CFG_CMD_RX_BUF_SIZE]; ///< Command receive buffer + + volatile uint32_t curr_socket_index; ///< Currently active socket instance + uint8_t curr_ipaddr[4]; ///< Current IP address of module + uint8_t curr_subnetmask[4]; ///< Current Subnet Mask of module + uint8_t curr_gateway[4]; ///< Current GAteway of module + + da16xxx_socket_t sockets[WIFI_DA16XXX_CFG_NUM_CREATEABLE_SOCKETS]; ///< Internal socket instances +} wifi_da16xxx_instance_ctrl_t; + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_DA16XXX) + **********************************************************************************************************************/ + +extern const wifi_da16xxx_cfg_t g_wifi_da16xxx_cfg; +extern bool rm_wifi_da16xxx_callback(at_transport_da16xxx_callback_args_t * p_args); + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t rm_wifi_da16xxx_open(wifi_da16xxx_cfg_t const * const p_cfg); +fsp_err_t rm_wifi_da16xxx_close(void); +fsp_err_t rm_wifi_da16xxx_disconnect(void); +fsp_err_t rm_wifi_da16xxx_connected(fsp_err_t * p_status); +fsp_err_t rm_wifi_da16xxx_network_info_get(uint32_t * p_ip_addr, uint32_t * p_subnet_mask, uint32_t * p_gateway); +fsp_err_t rm_wifi_da16xxx_connect(const char * p_ssid, + WIFISecurity_t security, + const char * p_passphrase, + uint8_t enc_type); +fsp_err_t rm_wifi_da16xxx_mac_addr_get(uint8_t * p_macaddr); +fsp_err_t rm_wifi_da16xxx_scan(WIFIScanResult_t * p_results, uint32_t maxNetworks); +fsp_err_t rm_wifi_da16xxx_ping(uint8_t * p_ip_addr, int count, uint32_t interval_ms); +fsp_err_t rm_wifi_da16xxx_ipaddr_get(uint32_t * p_ip_addr); +fsp_err_t rm_wifi_da16xxx_dns_query(const char * p_textstring, uint8_t * p_ip_addr); + +/* TCP Socket public function prototypes */ +fsp_err_t rm_wifi_da16xxx_avail_socket_get(uint32_t * p_socket_id); +fsp_err_t rm_wifi_da16xxx_socket_status_get(uint32_t socket_no, uint32_t * p_socket_status); +fsp_err_t rm_wifi_da16xxx_socket_create(uint32_t socket_no, uint32_t type, uint32_t ipversion); +fsp_err_t rm_wifi_da16xxx_tcp_connect(uint32_t socket_no, uint32_t ipaddr, uint32_t port); +int32_t rm_wifi_da16xxx_send(uint32_t socket_no, const uint8_t * p_data, uint32_t length, uint32_t timeout_ms); +int32_t rm_wifi_da16xxx_recv(uint32_t socket_no, uint8_t * p_data, uint32_t length, uint32_t timeout_ms); +fsp_err_t rm_wifi_da16xxx_socket_disconnect(uint32_t socket_no); + +/**********************************************************************************************************************************//** + * @addtogroup WIFI_DA16XXX WIFI_DA16XXX + * @{ + *************************************************************************************************************************************/ + +/**********************************************************************************************************************************//** + * Update the SNTP Server IP Address + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_SntpServerIpAddressSet(uint8_t * p_server_ip_addr); + +/**********************************************************************************************************************************//** + * Enable or Disable the SNTP Client Service + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_SntpEnableSet(wifi_da16xxx_sntp_enable_t enable); + +/**********************************************************************************************************************************//** + * Update the SNTP Timezone + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_SntpTimeZoneSet(int utc_offset_in_hours, + uint32_t minutes, + wifi_da16xxx_sntp_daylight_savings_enable_t daylightSavingsEnable); + +/**********************************************************************************************************************************//** + * Get the current local time based on current timezone in a string format + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_DA16XXX_LocalTimeGet(uint8_t * p_local_time, uint32_t size_string); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // RM_WIFI_DA16XXX_H + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_DA16XXX) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_da16xxx.h b/ra/fsp/inc/instances/rm_wifi_onchip_da16xxx.h deleted file mode 100644 index fc1c0d224..000000000 --- a/ra/fsp/inc/instances/rm_wifi_onchip_da16xxx.h +++ /dev/null @@ -1,290 +0,0 @@ -/*********************************************************************************************************************** - * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - * - * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products - * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are - * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use - * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property - * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas - * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION - * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT - * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR - * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM - * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION - * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, - * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, - * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY - * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup WIFI_ONCHIP_DA16XXX WIFI_ONCHIP_DA16XXX - * @{ - **********************************************************************************************************************/ -#ifndef RM_WIFI_ONCHIP_DA16XXX_H -#define RM_WIFI_ONCHIP_DA16XXX_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Register definitions, common services and error codes. */ -#include -#include -#include -#include "bsp_api.h" -#include "time.h" - -#include "r_ioport_api.h" -#include "r_ioport.h" -#include "r_uart_api.h" - -#include "FreeRTOS.h" -#include "semphr.h" -#include "stream_buffer.h" -#include "rm_wifi_config.h" -#include "rm_wifi_api.h" -#include "rm_wifi_onchip_da16xxx_cfg.h" - -/** - * @brief Max SSID length - */ -#ifndef wificonfigMAX_SSID_LEN - #define wificonfigMAX_SSID_LEN 32 -#endif - -/** - * @brief Max BSSID length - */ -#ifndef wificonfigMAX_BSSID_LEN - #define wificonfigMAX_BSSID_LEN 6 -#endif - -/** - * @brief Max passphrase length - */ -#ifndef wificonfigMAX_PASSPHRASE_LEN - #define wificonfigMAX_PASSPHRASE_LEN 32 -#endif - -#ifndef rm_wifi_onchip_da16xxx_uart_callback -void rm_wifi_onchip_da16xxx_uart_callback(uart_callback_args_t * p_args); - -#endif - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* Encryption Type supported by DA16XXX module */ -#define WIFI_ONCHIP_DA16XXX_TKIP_ENC_TYPE (0) -#define WIFI_ONCHIP_DA16XXX_AES_ENC_TYPE (1) -#define WIFI_ONCHIP_DA16XXX_TKIP_AES_ENC_TYPE (2) - -#define SOCKETS_IPPROTO_V4_DA16XXX (4) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -/** DA16XXX WiFi module enable/disable for SNTP */ -typedef enum e_wifi_onchip_da16xxx_sntp_enable -{ - WIFI_ONCHIP_DA16XXX_SNTP_DISABLE = 0, - WIFI_ONCHIP_DA16XXX_SNTP_ENABLE = 1 -} wifi_onchip_da16xxx_sntp_enable_t; - -/** DA16XXX Wifi socket status types */ -typedef enum e_da16xxx_socket_status -{ - WIFI_ONCHIP_DA16XXX_SOCKET_STATUS_CLOSED = 0, - WIFI_ONCHIP_DA16XXX_SOCKET_STATUS_SOCKET, - WIFI_ONCHIP_DA16XXX_SOCKET_STATUS_BOUND, - WIFI_ONCHIP_DA16XXX_SOCKET_STATUS_LISTEN, - WIFI_ONCHIP_DA16XXX_SOCKET_STATUS_CONNECTED -} da16xxx_socket_status_t; - -/** DA16XXX socket shutdown channels */ -typedef enum e_da16xxx_socket_rw -{ - WIFI_ONCHIP_DA16XXX_SOCKET_READ = 1, - WIFI_ONCHIP_DA16XXX_SOCKET_WRITE = 2 -} da16xxx_socket_rw; - -/** DA16XXX socket receive state */ -typedef enum e_da16xxx_recv_state -{ - WIFI_ONCHIP_DA16XXX_RECV_PREFIX, // + - WIFI_ONCHIP_DA16XXX_RECV_CMD, // command - WIFI_ONCHIP_DA16XXX_RECV_SUFFIX, // : - WIFI_ONCHIP_DA16XXX_RECV_PARAM_CID, // cid parameter - WIFI_ONCHIP_DA16XXX_RECV_PARAM_IP, // ip parameter - WIFI_ONCHIP_DA16XXX_RECV_PARAM_PORT, // port parameter - WIFI_ONCHIP_DA16XXX_RECV_PARAM_LEN, // length parameter - WIFI_ONCHIP_DA16XXX_RECV_DATA -} da16xxx_recv_state; - -/** DA16XXX WiFi module enable/disable for SNTP Daylight */ -typedef enum e_wifi_onchip_da16xxx_sntp_daylight_savings_enable -{ - WIFI_ONCHIP_DA16XXX_SNTP_DAYLIGHT_SAVINGS_DISABLE = 0, - WIFI_ONCHIP_DA16XXX_SNTP_DAYLIGHT_SAVINGS_ENABLE = 1, -} wifi_onchip_da16xxx_sntp_daylight_savings_enable_t; - -/** User configuration structure, used in open function */ -typedef struct st_wifi_onchip_cfg -{ - const uint32_t num_uarts; ///< Number of UART interfaces to use - const uint32_t num_sockets; ///< Number of sockets to initialize - const uint8_t * country_code; ///< Country code defined in ISO3166-1 alpha-2 standard - const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module - const uart_instance_t * uart_instances[WIFI_ONCHIP_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< SCI UART instances - const uint8_t * sntp_server_ip; ///< The SNTP server IP address string - const int32_t sntp_utc_offset_in_hours; ///< Timezone offset in secs (-43200 - 43200) - void const * p_context; ///< User defined context passed into callback function. - void const * p_extend; ///< Pointer to extended configuration by instance of interface. -} wifi_onchip_da16xxx_cfg_t; - -/** DA16XXX Wifi internal socket instance structure */ -typedef struct -{ - uint8_t remote_ipaddr[4]; ///< Remote IP address - int remote_port; ///< Remote Port - int socket_recv_data_len; ///< Data length of incoming socket data - int socket_type; ///< Socket type (TCP Server | TCP Client | UDP) - uint32_t socket_status; ///< Current socket status - uint32_t socket_recv_error_count; ///< Socket receive error count - uint32_t socket_create_flag; ///< Flag to determine in socket has been created. - uint32_t socket_read_write_flag; ///< flag to determine if read and/or write channels are active. - da16xxx_recv_state socket_recv_state; ///< Incoming Socket data header information - - StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle - StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info - uint8_t socket_recv_buff[WIFI_ONCHIP_DA16XXX_CFG_MAX_SOCKET_RX_SIZE]; ///< Socket receive buffer used by byte queue -} da16xxx_socket_t; - -/** WIFI_ONCHIP_DA16XXX private control block. DO NOT MODIFY. */ -typedef struct st_wifi_onchip_da16xxx_instance_ctrl -{ - wifi_onchip_da16xxx_cfg_t const * p_wifi_onchip_da16xxx_cfg; ///< Pointer to initial configurations. - bsp_io_port_pin_t reset_pin; ///< Wifi module reset pin - uint32_t num_uarts; ///< number of UARTS currently used for communication with module - uint32_t num_creatable_sockets; ///< Number of simultaneous sockets supported - uint32_t tx_data_size; ///< Size of the data to send - uint32_t curr_cmd_port; ///< Current UART instance index for AT commands - uint32_t open; ///< Flag to indicate if wifi instance has been initialized - uint8_t is_sntp_enabled; ///< Flag to indicate Enable/Disable of SNTP Client - - uint8_t cmd_rx_queue_buf[WIFI_ONCHIP_DA16XXX_CFG_CMD_RX_BUF_SIZE]; ///< Command port receive buffer used by byte queue // FreeRTOS - StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle - StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info - - volatile uint32_t curr_socket_index; ///< Currently active socket instance - uint8_t * p_current_cmd_rx_buffer; ///< Pointer to temporary receive buffer for dependent modules - uint32_t current_cmd_rx_buffer_size; ///< Size of the temporary buffer - uint8_t cmd_tx_buff[WIFI_ONCHIP_DA16XXX_CFG_CMD_TX_BUF_SIZE]; ///< Command send buffer - uint8_t cmd_rx_buff[WIFI_ONCHIP_DA16XXX_CFG_CMD_RX_BUF_SIZE]; ///< Command receive buffer - uint8_t curr_ipaddr[4]; ///< Current IP address of module - uint8_t curr_subnetmask[4]; ///< Current Subnet Mask of module - uint8_t curr_gateway[4]; ///< Current GAteway of module - - SemaphoreHandle_t tx_sem; ///< Transmit binary semaphore handle - SemaphoreHandle_t rx_sem; ///< Receive binary semaphore handle - - uart_instance_t * uart_instance_objects[WIFI_ONCHIP_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART instance object - SemaphoreHandle_t uart_tei_sem[WIFI_ONCHIP_DA16XXX_CFG_MAX_NUMBER_UART_PORTS]; ///< UART transmission end binary semaphore - da16xxx_socket_t sockets[WIFI_ONCHIP_DA16XXX_CFG_NUM_CREATEABLE_SOCKETS]; ///< Internal socket instances -} wifi_onchip_da16xxx_instance_ctrl_t; - -/*******************************************************************************************************************//** - * @} (end addtogroup WIFI_ONCHIP_DA16XXX) - **********************************************************************************************************************/ - -extern const wifi_onchip_da16xxx_cfg_t g_wifi_onchip_da16xxx_cfg; -extern const char * g_wifi_onchip_da16xxx_uart_cmd_baud; - -/********************************************************************************************************************** - * Public Function Prototypes - **********************************************************************************************************************/ -fsp_err_t rm_wifi_onchip_da16xxx_open(wifi_onchip_da16xxx_cfg_t const * const p_cfg); -fsp_err_t rm_wifi_onchip_da16xxx_close(void); -fsp_err_t rm_wifi_onchip_da16xxx_disconnect(void); -fsp_err_t rm_wifi_onchip_da16xxx_connected(fsp_err_t * p_status); -fsp_err_t rm_wifi_onchip_da16xxx_network_info_get(uint32_t * p_ip_addr, uint32_t * p_subnet_mask, uint32_t * p_gateway); -fsp_err_t rm_wifi_onchip_da16xxx_connect(const char * p_ssid, - WIFISecurity_t security, - const char * p_passphrase, - uint8_t enc_type); -fsp_err_t rm_wifi_onchip_da16xxx_mac_addr_get(uint8_t * p_macaddr); -fsp_err_t rm_wifi_onchip_da16xxx_scan(WIFIScanResult_t * p_results, uint32_t maxNetworks); -fsp_err_t rm_wifi_onchip_da16xxx_ping(uint8_t * p_ip_addr, int count, uint32_t interval_ms); -fsp_err_t rm_wifi_onchip_da16xxx_ipaddr_get(uint32_t * p_ip_addr); -fsp_err_t rm_wifi_onchip_da16xxx_dns_query(const char * p_textstring, uint8_t * p_ip_addr); -fsp_err_t rm_wifi_onchip_da16xxx_at_command_send(const char * p_textstring, - uint8_t * const p_response_buffer, - uint32_t response_buffer_size, - uint32_t timeout_ms, - uint32_t delay_ms, - char * response); -size_t rm_wifi_onchip_da16xxx_buffer_recv(const char * p_data, - uint32_t length, - uint32_t rx_timeout, - size_t trigger_level); - -/* TCP Socket public function prototypes */ -fsp_err_t rm_wifi_onchip_da16xxx_avail_socket_get(uint32_t * p_socket_id); -fsp_err_t rm_wifi_onchip_da16xxx_socket_status_get(uint32_t socket_no, uint32_t * p_socket_status); -fsp_err_t rm_wifi_onchip_da16xxx_socket_create(uint32_t socket_no, uint32_t type, uint32_t ipversion); -fsp_err_t rm_wifi_onchip_da16xxx_tcp_connect(uint32_t socket_no, uint32_t ipaddr, uint32_t port); -int32_t rm_wifi_onchip_da16xxx_send(uint32_t socket_no, const uint8_t * p_data, uint32_t length, uint32_t timeout_ms); -int32_t rm_wifi_onchip_da16xxx_recv(uint32_t socket_no, uint8_t * p_data, uint32_t length, uint32_t timeout_ms); -fsp_err_t rm_wifi_onchip_da16xxx_socket_disconnect(uint32_t socket_no); - -#ifndef rm_wifi_onchip_da16xxx_uart_callback -void rm_wifi_onchip_da16xxx_uart_callback(uart_callback_args_t * p_args); - -#endif - -/**********************************************************************************************************************************//** - * @addtogroup WIFI_ONCHIP_DA16XXX WIFI_ONCHIP_DA16XXX - * @{ - *************************************************************************************************************************************/ - -/**********************************************************************************************************************************//** - * Update the SNTP Server IP Address - * - *************************************************************************************************************************************/ -fsp_err_t RM_WIFI_ONCHIP_DA16XXX_SntpServerIpAddressSet(uint8_t * p_server_ip_addr); - -/**********************************************************************************************************************************//** - * Enable or Disable the SNTP Client Service - * - *************************************************************************************************************************************/ -fsp_err_t RM_WIFI_ONCHIP_DA16XXX_SntpEnableSet(wifi_onchip_da16xxx_sntp_enable_t enable); - -/**********************************************************************************************************************************//** - * Update the SNTP Timezone - * - *************************************************************************************************************************************/ -fsp_err_t RM_WIFI_ONCHIP_DA16XXX_SntpTimeZoneSet(int utc_offset_in_hours, - uint32_t minutes, - wifi_onchip_da16xxx_sntp_daylight_savings_enable_t daylightSavingsEnable); - -/**********************************************************************************************************************************//** - * Get the current local time based on current timezone in a string format - * - *************************************************************************************************************************************/ -fsp_err_t RM_WIFI_ONCHIP_DA16XXX_LocalTimeGet(uint8_t * p_local_time, uint32_t size_string); - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // RM_WIFI_ONCHIP_DA16XXX_H - -/*******************************************************************************************************************//** - * @} (end addtogroup WIFI_ONCHIP_DA16XXX) - **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h index 711abbaad..4898ecc6a 100644 --- a/ra/fsp/inc/instances/rm_wifi_onchip_silex.h +++ b/ra/fsp/inc/instances/rm_wifi_onchip_silex.h @@ -213,6 +213,7 @@ typedef struct uint8_t * p_next_packet_buffer; uint32_t packet_buffer_size; uint32_t current_cmd_buffer_index; + bool handle_socket_connect; #endif volatile uint32_t curr_socket_index; ///< Currently active socket instance uint8_t cmd_tx_buff[WIFI_ONCHIP_SILEX_CFG_CMD_TX_BUF_SIZE]; ///< Command send buffer diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h index c672b9a74..56c4da0ab 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h @@ -136,16 +136,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -361,9 +359,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -387,7 +384,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -397,29 +394,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -447,8 +1012,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -589,7 +1155,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -597,34 +1163,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2873,16 +3439,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4066,7 +4693,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -6214,46 +6856,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6750,10 +7427,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -11266,7 +11943,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13214,17 +13902,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -13241,6 +14103,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -13306,19 +14170,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -14252,10 +15116,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -14936,6 +15810,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -15924,30 +16805,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -17883,6 +18780,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h index 1db0a7709..aa73b6962 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h @@ -140,16 +140,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -365,9 +363,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -391,7 +388,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -401,29 +398,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -451,8 +1016,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -534,7 +1100,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -542,34 +1108,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2676,16 +3242,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3480,7 +4107,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -5609,46 +6251,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6145,10 +6822,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -10334,7 +11011,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -11185,17 +11873,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -11212,6 +12074,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ ELSEGR ================ */ @@ -11252,19 +12116,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -12134,10 +12998,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -12605,6 +13479,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -13597,30 +14478,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -15426,6 +16323,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h index 89fb4018a..22d9ccea2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h @@ -140,16 +140,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -365,9 +363,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -391,7 +388,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -401,29 +398,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -451,8 +1016,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -534,7 +1100,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -542,34 +1108,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2431,16 +2997,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -2706,7 +3333,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -4791,46 +5433,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -5327,10 +6004,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -10153,7 +10830,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -11000,17 +11688,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -11027,6 +11889,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ ELSEGR ================ */ @@ -11067,19 +11931,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -11833,10 +12697,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -11950,6 +12824,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -12919,30 +13800,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -15194,6 +16091,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h new file mode 100644 index 000000000..2200efd70 --- /dev/null +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E307.h @@ -0,0 +1,15532 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file ./out/R7FA2E307.h + * @brief CMSIS HeaderFile + * @version 0.50.00 + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA2E307 + * @{ + */ + +#ifndef R7FA2E307_H + #define R7FA2E307_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M23 Processor and Core Peripherals =========================== */ + #define __CM23_REV 0x0100U /*!< CM23 Core Revision */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 0 /*!< FPU present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm23.h" /*!< ARM Cortex-M23 processor and core peripherals */ + #include "system.h" /*!< R7FA2E307 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + uint16_t : 13; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } CTL_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[63]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + __IM uint32_t RESERVED3[63]; + __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ +} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) + */ +typedef struct +{ + union + { + __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + + struct + { + uint16_t : 2; + __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ + __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ + __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ + __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ + __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ + __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ + uint16_t : 4; + __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ + __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit + * is read as 1. The write value should be 1.) */ + __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ + __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ + } R_b; + }; + __IM uint16_t RESERVED; +} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED26[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 3; /*!< [26..24] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Slave MPU (R_MPU_SMPU) + */ + +typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ +{ + union + { + __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting + * of the PROTECT and OAD bit. */ + } SMPUCTL_b; + }; + __IM uint16_t RESERVED[7]; + __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ +} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + + struct + { + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; + }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ + + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ + uint8_t : 3; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint16_t RESERVED21; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED25; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED27; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED28; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED29[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED30[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED31; + __IM uint32_t RESERVED32[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED37[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED39[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED40[6]; + __IM uint16_t RESERVED41; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED42; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED43; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED44; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED47[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED48; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED49; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; + __IM uint32_t RESERVED53[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED54; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED55; + __IM uint32_t RESERVED56[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED57; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED58; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED60; + __IM uint16_t RESERVED61; + __IM uint32_t RESERVED62[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint16_t RESERVED[276]; + + union + { + __IM uint16_t TSCDR; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register */ + + struct + { + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; + }; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CRC_BASE 0x40074000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SMPU_BASE 0x40000C00UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_WDT_BASE 0x40044200UL + #define R_AGTX0_BASE 0x40084000UL + #define R_AGTX1_BASE 0x40084100UL + #define R_AGTX2_BASE 0x40084200UL + #define R_AGTX3_BASE 0x40084300UL + #define R_AGTX4_BASE 0x40084400UL + #define R_AGTX5_BASE 0x40084500UL + #define R_AGTX6_BASE 0x40084600UL + #define R_AGTX7_BASE 0x40084700UL + #define R_AGTX8_BASE 0x40084800UL + #define R_AGTX9_BASE 0x40084900UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== R =========================================================== */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (24UL) /*!< TPCS (Bit 24) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7000000UL) /*!< TPCS (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SMPUCTL ======================================================== */ + #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================== PRWCNTR ======================================================== */ + #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ + #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA2E307_H */ + +/** @} */ /* End of group R7FA2E307 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h index 2396cfb92..66d5c402b 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h @@ -140,16 +140,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -361,69 +359,636 @@ typedef struct union { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; - } SDMOD_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; + __IM uint16_t RESERVED2; union { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; - }; - - union - { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ } STAT_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -451,8 +1016,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -586,6 +1152,117 @@ typedef struct }; } R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + uint16_t : 13; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } CTL_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[63]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + __IM uint32_t RESERVED3[63]; + __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ +} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) + */ +typedef struct +{ + union + { + __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + + struct + { + uint16_t : 2; + __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ + __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ + __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ + __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ + __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ + __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ + uint16_t : 4; + __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ + __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit + * is read as 1. The write value should be 1.) */ + __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ + __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ + } R_b; + }; + __IM uint16_t RESERVED; +} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + /** * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ @@ -2624,16 +3301,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4043,7 +4781,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -6172,46 +6925,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6708,10 +7496,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -6851,6 +7639,46 @@ typedef struct /*!< (@ 0x40080000) R_KINT Structure }; } R_KINT_Type; /*!< Size = 9 (0x9) */ +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Slave MPU (R_MPU_SMPU) + */ + +typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ +{ + union + { + __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting + * of the PROTECT and OAD bit. */ + } SMPUCTL_b; + }; + __IM uint16_t RESERVED[7]; + __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ +} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ /* =========================================================================================================================== */ @@ -10857,7 +11685,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -11407,6 +12246,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_IIC2_BASE 0x40053200UL #define R_IWDT_BASE 0x40044400UL #define R_KINT_BASE 0x40080000UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ #define R_PORT0_BASE 0x40040000UL @@ -11507,6 +12348,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -11710,17 +12553,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -11737,6 +12754,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -11798,6 +12817,67 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== R =========================================================== */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ SP ================ */ /* =========================================================================================================================== */ @@ -12623,10 +13703,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -13534,6 +14624,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -14526,30 +15623,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -14968,6 +16081,22 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SMPUCTL ======================================================== */ + #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ /* =========================================================================================================================== */ @@ -16339,6 +17468,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h index 6a97e72b3..43aef43f2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,375 +400,362 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CAN0_MB [MB] (Mailbox) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ - - struct - { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; - }; - - union - { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ - - struct - { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; - }; - - union - { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) */ typedef struct { + __IM uint8_t RESERVED[36]; + union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint8_t RESERVED1[7]; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED2[3]; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED3; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED5; -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED6[3]; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED7; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED8; -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED9; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) */ typedef struct { @@ -779,8973 +763,9175 @@ typedef struct { union { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; }; - struct + union { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; }; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[5]; -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; - __IM uint8_t RESERVED1; + __IM uint16_t RESERVED; union { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; - - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; - __IM uint8_t RESERVED2; + __IM uint16_t RESERVED1[5]; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; - __IM uint8_t RESERVED3[3]; + __IM uint16_t RESERVED2; union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; - __IM uint8_t RESERVED4; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ - - struct - { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_B_CSa [CSa] (CS Registers) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; - }; - - union - { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ - - struct - { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_CAN0_MB [MB] (Mailbox) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) - */ -typedef struct -{ union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; }; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) */ typedef struct { union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + __IM uint16_t RESERVED; -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) - */ -typedef struct -{ union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ - - struct + union { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - union - { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + union + { + struct + { + __IM uint16_t RESERVED; -/** @} */ /* End of group Device_Peripheral_clusters */ + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_PFS_PORT [PORT] (Port [0..14]) */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +typedef struct { - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct + union { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; }; + __IM uint8_t RESERVED1; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - struct + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; }; + __IM uint8_t RESERVED2; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - struct + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; }; - __IM uint8_t RESERVED; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - struct + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; }; + __IM uint8_t RESERVED4; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; }; union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; union { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - union + struct { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; }; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct + union { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED7; + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; - struct + union { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; - __IM uint8_t RESERVED11; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED4; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; + __IM uint8_t RESERVED5; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; - __IM uint8_t RESERVED14; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED10; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; + __IM uint8_t RESERVED11; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; - __IM uint32_t RESERVED23[3]; union { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; - __IM uint16_t RESERVED24; union { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; union { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; union { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - uint32_t : 1; - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; union { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; - } PSARD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; - } MSSAR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; union { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; union { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; + __IM uint8_t RESERVED14; union { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; union { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; union { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; - }; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network (CAN) Module (R_CAN0) - */ - -typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ -{ - __IM uint32_t RESERVED[128]; - __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + __IM uint32_t RESERVED23[3]; union { - __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 3; - } MKR_b[8]; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } FIDCR_b[2]; + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; }; union { - __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ struct { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ - } MKIVLR_b; + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; union { - union + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct { - __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ - } MIER_b; - }; +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox - * Mode */ +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - } MIER_FIFO_b; - }; - }; - __IM uint32_t RESERVED1[252]; +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; union { - union - { - __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - - struct - { - __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ - __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox - * setting enabled) */ - __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting - * enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_TX_b[32]; - }; + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - union + struct { - __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ - - struct - { - __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ - __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting - * enabled) */ - __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_RX_b[32]; - }; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; union { - __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ - __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ - __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ - __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ - __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ - __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ - __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ - __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ - __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ - __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ - uint16_t : 2; - } CTLR_b; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; union { - __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ - __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ - __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ - __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ - __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ - __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ - __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ - __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ - __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ - __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ - __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ - __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ - __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ - __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ - __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ - uint16_t : 1; - } STR_b; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; }; union { - __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ struct { - __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ - uint32_t : 7; - __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ - uint32_t : 1; - __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ - uint32_t : 2; - __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the - * frequency of the CAN communication clock (fCANCLK). */ - uint32_t : 2; - __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ - } BCR_b; + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; }; union { - __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ struct { - __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ - __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ - __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ - __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ - __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ - __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ - } RFCR_b; + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; }; union { - __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ struct { - __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented - * by writing FFh to RFPCR. */ - } RFPCR_b; + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; }; union { - __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ - __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ - uint8_t : 2; - __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ - __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ - } TFCR_b; + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; }; union { - __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented - * by writing FFh to TFPCR. */ - } TFPCR_b; + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ - __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ - __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ - __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ - __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ - __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ - __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ - __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ - } EIER_b; + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ - __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ - __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ - __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ - __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ - __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ - __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ - __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ - } EIFR_b; + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; }; union { - __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements - * the counter value according to the error status of the - * CAN module during reception. */ - } RECR_b; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ - union - { - __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements - * the counter value according to the error status of the - * CAN module during transmission. */ - } TECR_b; - }; +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ - __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ - __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ - __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ - __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ - __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ - __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ - __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ - } ECSR_b; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; union { - __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ - - struct - { - __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel - * number is output to MSSR. */ - } CSSR_b; + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ }; + __IM uint32_t RESERVED4[58]; union { - __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ - - struct + union { - __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output - * the smallest mailbox number that is searched in each mode - * of MSMR. */ - uint8_t : 2; - __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ - } MSSR_b; + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ }; + __IM uint32_t RESERVED5[46]; union { - __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ - - struct - { - __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ - uint8_t : 6; - } MSMR_b; + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ }; + __IM uint32_t RESERVED6[33]; union { - __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ struct { - __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ - } TSR_b; + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; union { - __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ - - struct - { - __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, - * the value converted for data table search can be read. */ - } AFSR_b; + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ }; + __IM uint32_t RESERVED9[28]; union { - __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ - - struct - { - __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ - __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ - uint8_t : 5; - } TCR_b; + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ -/* ================ R_CRC ================ */ +/* ================ R_CAC ================ */ /* =========================================================================================================================== */ /** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) */ -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ { union { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; union { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; - __IM uint16_t RESERVED; union { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ - union + struct { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; }; union { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ - union + struct { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ struct { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ + __IM uint8_t RESERVED; -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ union { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ struct { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; }; union { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ struct { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; union { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ union { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ struct { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; }; union { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ struct { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; }; union { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ struct { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; }; union { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - struct + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; }; - __IM uint16_t RESERVED[9]; + __IM uint32_t RESERVED1[252]; union { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - struct + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ struct { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ union { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ struct { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ struct { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 14; - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ union { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ struct { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; union { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; }; - __IM uint32_t RESERVED3[15]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ union { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ struct { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; }; union { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ struct { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; }; union { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ struct { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; }; union { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ struct { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; }; union { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ struct { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ struct { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; }; union { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ struct { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ - } DMAMD_b; + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; }; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ struct { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address update mode for transfer source or destination. */ - } DMOFR_b; + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; }; union { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ struct { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; - }; - + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + union { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ struct { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; }; union { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ struct { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ struct { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ union { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ struct { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; }; union { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ struct { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ union { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - struct + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - struct + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; }; union { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ struct { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ -/* ================ R_DTC ================ */ +/* ================ R_DAC ================ */ /* =========================================================================================================================== */ /** - * @brief Data Transfer Controller (R_DTC) + * @brief D/A Converter (R_DAC) */ -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ { union { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ struct { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ - } DTCVBR_b; + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ struct { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ uint8_t : 7; - } DTCST_b; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; }; - __IM uint8_t RESERVED3; union { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ struct { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; }; union { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; - } DTCCR_SEC_b; + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ struct { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ -/** - * @brief Event Link Controller (R_ELC) - */ + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ union { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ struct { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; union { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; }; - __IM uint16_t RESERVED3; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ union { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ struct { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; }; - __IM uint16_t RESERVED4; + __IM uint32_t RESERVED[3]; union { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ struct { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ + __IM uint32_t RESERVED1[123]; -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ - -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ union { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ +/* ================ R_DMA ================ */ /* =========================================================================================================================== */ /** - * @brief Flash Application Command Interface (R_FACI_HP) + * @brief DMA Controller Common (R_DMA) */ -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ { - __IM uint32_t RESERVED[4]; - union { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; union { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; + __IM uint32_t RESERVED3[15]; union { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ struct { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ union { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ struct { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; }; union { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ struct { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; }; - __IM uint32_t RESERVED8[3]; union { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ struct { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10[12]; union { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ struct { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; }; - __IM uint16_t RESERVED11; union { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ struct { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; }; - __IM uint16_t RESERVED12; + __IM uint8_t RESERVED; union { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ struct { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; }; union { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ struct { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; + __IM uint16_t RESERVED1; union { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ struct { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[4]; union { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ struct { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[11]; union { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ struct { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; union { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ struct { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ struct { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; }; union { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ struct { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; }; union { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ struct { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; }; - __IM uint16_t RESERVED23; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ union { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ struct { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; }; - __IM uint16_t RESERVED24; + __IM uint8_t RESERVED; union { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ struct { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; }; - __IM uint16_t RESERVED25; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ +/* ================ R_DTC ================ */ /* =========================================================================================================================== */ /** - * @brief Flash Memory Cache (R_FCACHE) + * @brief Data Transfer Controller (R_DTC) */ -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ { - __IM uint16_t RESERVED[128]; - union { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ struct { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; }; + __IM uint8_t RESERVED; __IM uint16_t RESERVED1; union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ - uint16_t : 15; - } FCACHEIV_b; - }; - __IM uint16_t RESERVED2[11]; + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; union { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ struct { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; + __IM uint8_t RESERVED3; union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; - } FSAR_b; + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ +/* ================ R_ELC ================ */ /* =========================================================================================================================== */ /** - * @brief General PWM Timer (R_GPT0) + * @brief Event Link Controller (R_ELC) */ -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ { union { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ struct { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; union { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ struct { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; }; + __IM uint16_t RESERVED3; union { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ struct { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; }; + __IM uint16_t RESERVED4; union { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ struct { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ union { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ struct { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; union { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ struct { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; union { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ struct { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; - }; - - union - { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ - - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ struct { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; }; union { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ struct { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; - } GTICASR_b; + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; }; + __IM uint32_t RESERVED8[3]; union { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ struct { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; - } GTICBSR_b; + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; union { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ struct { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; }; + __IM uint16_t RESERVED11; union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - } GTUDDTYC_b; + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; }; + __IM uint16_t RESERVED12; union { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ struct { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; }; union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ struct { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; union { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ struct { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[11]; union { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ struct { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ struct { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; union { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ struct { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; }; union { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ struct { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; }; union { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ struct { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; }; + __IM uint16_t RESERVED23; union { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ struct { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ struct { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; - }; - - union - { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ - - struct - { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; - }; - - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; - - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ - - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; }; + __IM uint16_t RESERVED25; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - union - { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ - - struct - { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; - }; +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ +/** + * @brief Flash Memory Cache (R_FCACHE) + */ - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; union { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ struct { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; }; + __IM uint16_t RESERVED2[11]; union { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ struct { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; union { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - union - { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; +/** + * @brief General PWM Timer (R_GPT0) + */ +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ union { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ struct { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; }; union { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ struct { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; }; union { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ struct { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; union { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ struct { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; }; union { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ struct { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; }; union { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ struct { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; }; union { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ struct { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; - }; - - union - { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ - - struct - { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; }; union { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ struct { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; }; - __IM uint32_t RESERVED[4]; union { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ struct { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; }; union { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ struct { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; }; - __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ struct { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; }; union { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ struct { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ union { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; + uint32_t : 8; + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; }; - __IM uint32_t RESERVED[60]; union { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ struct { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; - }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; - + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + union { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ struct { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; union { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ struct { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ struct { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ struct { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; }; union { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ struct { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; }; - __IM uint32_t RESERVED10[6]; union { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ struct { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; union { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ struct { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; }; - __IM uint32_t RESERVED16[24]; union { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ struct { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ union { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ struct { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; - }; - - union - { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ - - struct - { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; }; union { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ struct { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; }; union { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ struct { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; }; union { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ struct { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; }; union { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ struct { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; }; union { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ struct { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; }; union { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ struct { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; }; union { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ struct { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; }; union { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ struct { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ struct { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; }; union { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ struct { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; }; union { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ struct { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; }; union { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ struct { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ struct { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; }; union { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ union { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ struct { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ struct { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; }; union { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ struct { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; }; + __IM uint32_t RESERVED[4]; union { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ struct { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; }; - __IM uint8_t RESERVED1; union { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ struct { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + __IM uint32_t RESERVED1[2]; -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ + __IM uint32_t RESERVED2; -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ /* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ +/* ================ R_GPT_POEG0 ================ */ /* =========================================================================================================================== */ /** - * @brief System-Module Stop (R_MSTP) + * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; }; + __IM uint32_t RESERVED[15]; union { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ struct { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ struct { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ union { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ struct { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; }; + __IM uint32_t RESERVED[60]; union { - union - { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; - - union + struct { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ union { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ struct { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; union { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ struct { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; union { - union - { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ struct { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; }; union { - union + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ struct { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ -/** - * @brief I/O Ports-PFS (R_PFS) - */ + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ union { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ +} R_ICU_Type; /*!< Size = 1152 (0x480) */ /* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ +/* ================ R_IIC0 ================ */ /* =========================================================================================================================== */ /** - * @brief I/O Ports-MISC (R_PMISC) + * @brief I2C Bus Interface (R_IIC0) */ -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ { union { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ struct { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - - struct + union { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; - }; - __IM uint8_t RESERVED1; + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - union - { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; - struct + union { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; - }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; - - union - { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - struct - { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ +} R_MSTP_Type; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ +/* ================ R_PORT0 ================ */ /* =========================================================================================================================== */ /** - * @brief Quad Serial Peripheral Interface (R_QSPI) + * @brief I/O Ports (R_PORT0) */ -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ { union { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - - struct - { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; - }; - - union - { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - - struct - { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; - }; - - union - { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - - struct + union { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; - }; + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - union - { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; struct { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; - }; - - union - { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - struct - { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; - }; + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; - union - { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - struct - { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; }; union { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - - struct + union { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; - }; - __IM uint32_t RESERVED; + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - union - { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; struct { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; - }; + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - union - { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; - struct - { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; }; union { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - - struct + union { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; - }; - __IM uint32_t RESERVED1; + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ - union - { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; struct { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; }; union { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; struct { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; }; - __IM uint32_t RESERVED2[499]; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ -/* ================ R_RTC ================ */ +/* ================ R_PMISC ================ */ /* =========================================================================================================================== */ /** - * @brief Realtime Clock (R_RTC) + * @brief I/O Ports-MISC (R_PMISC) */ -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ { union { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; }; - __IM uint8_t RESERVED; + __IM uint8_t RESERVED[2]; union { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ - union + struct { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; }; __IM uint8_t RESERVED1; union { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ - union + struct { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; }; - __IM uint8_t RESERVED2; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; union { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - union + struct { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; }; - __IM uint8_t RESERVED3; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ union { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - union + struct { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; }; - __IM uint8_t RESERVED4; union { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; }; union { - union + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ - union + struct { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; }; - __IM uint8_t RESERVED7; + __IM uint32_t RESERVED; union { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ - union + struct { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; }; - __IM uint8_t RESERVED8; union { - union + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ - union + struct { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; }; - __IM uint8_t RESERVED9; + __IM uint32_t RESERVED1; union { - union + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - union + struct { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; - __IM uint8_t RESERVED10; + __IM uint32_t RESERVED2[499]; union { - union + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ +/** + * @brief Realtime Clock (R_RTC) + */ - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED; union { union { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; }; union { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; }; }; - __IM uint8_t RESERVED12; + __IM uint8_t RESERVED1; union { union { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ struct { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; }; union { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; }; }; + __IM uint8_t RESERVED2; union { union { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; }; union { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ struct { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; - }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; }; - __IM uint8_t RESERVED15; + __IM uint8_t RESERVED3; union { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct + union { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; - struct + union { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; }; - __IM uint8_t RESERVED18; + __IM uint8_t RESERVED4; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ union { union { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; }; union { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; }; }; + __IM uint8_t RESERVED7; union { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - struct + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; }; + __IM uint8_t RESERVED8; union { union { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; }; union { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; }; }; + __IM uint8_t RESERVED9; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - struct + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; }; + __IM uint8_t RESERVED10; union { union { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; }; union { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ struct { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; }; union { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; }; }; + __IM uint8_t RESERVED12; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct + union { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; - struct + union { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; }; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct + union { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; - struct + union { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; }; + __IM uint8_t RESERVED15; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ struct { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ struct { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; + __IM uint8_t RESERVED18; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; }; union { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ struct { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; }; union { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ struct { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; }; }; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct + union { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; - struct + union { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - struct + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; - struct + union { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; - }; + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - struct + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + } STCR_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; - __IM uint8_t RESERVED[3]; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; - __IM uint8_t RESERVED3[179]; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; + __IM uint8_t RESERVED[3]; union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED3[179]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; + __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED5[3]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ @@ -11396,7 +11582,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13126,14 +13323,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -13147,7 +13344,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -13261,7 +13487,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2_BASE 0x4009F200UL #define R_IWDT_BASE 0x40083200UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -13296,7 +13521,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TSN_BASE 0x407EC000UL #define R_USB_FS0_BASE 0x40090000UL @@ -13328,8 +13552,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -13375,7 +13598,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -13410,7 +13632,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TSN ((R_TSN_Type *) R_TSN_BASE) #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) @@ -13583,17 +13804,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -13610,6 +14005,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -13675,62 +14072,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ -/* ================ SMPU ================ */ +/* ================ GROUP ================ */ /* =========================================================================================================================== */ -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -13898,89 +14279,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -14759,10 +15057,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15316,6 +15624,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -16333,30 +16648,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -16735,17 +17066,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -17767,121 +18097,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -18315,6 +18530,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -19400,12 +19618,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h index a46997455..347d22c15 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -304,128 +302,695 @@ typedef struct union { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; union { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ union { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; + __IM uint16_t RESERVED; union { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; - } SDMOD_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; + __IM uint16_t RESERVED2; union { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; }; + __IM uint32_t RESERVED; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -453,8 +1018,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -1044,115 +1610,114 @@ typedef struct } R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not * stored. */ - } CTL_b; + } EN_b; }; __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint16_t RESERVED1; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) @@ -3355,16 +3920,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4403,7 +5029,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6696,46 +7337,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7232,10 +7908,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -8461,37 +9137,46 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -12701,7 +13386,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14588,14 +15284,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14609,7 +15305,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -15080,7 +15805,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -15201,7 +15925,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -15413,17 +16136,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -15440,6 +16337,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -15829,62 +16728,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -16830,10 +17713,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -17284,6 +18177,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -18341,30 +19241,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -19374,17 +20290,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -20874,6 +21789,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -22014,12 +22932,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h index 5e4ddae59..6c3e83dac 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -588,7 +1154,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -596,34 +1162,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2797,16 +3363,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3990,7 +4617,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6393,46 +7035,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6929,10 +7606,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -11516,7 +12193,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13353,17 +14041,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -13380,6 +14242,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -13445,19 +14309,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -14359,10 +15223,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15043,6 +15917,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -16140,30 +17021,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -18156,6 +19053,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h index 3398c90f9..cf6588d69 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,891 +400,1286 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CAN0_MB [MB] (Mailbox) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED1; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED2[3]; -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED4; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED5; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED7; -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ - - struct + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - union - { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; - struct + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED8; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED9; -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED10; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct + union { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { union { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { - __IM uint8_t RESERVED[389]; + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint8_t RESERVED1; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ union { - union + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; }; - __IM uint8_t RESERVED3[3]; union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; }; - __IM uint8_t RESERVED4; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_BUS_B_CSa [CSa] (CS Registers) + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; __IM uint16_t RESERVED; union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; } AGTMR1_b; }; @@ -3073,16 +3465,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4206,7 +4659,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6499,46 +6967,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7035,10 +7538,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -7127,37 +7630,46 @@ typedef struct /*!< (@ 0x40083200) R_IWDT Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8049,2490 +8561,2164 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure uint32_t : 2; __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + uint32_t : 27; + } SFMSPC_b; }; - __IM uint8_t RESERVED7; union { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - union + struct { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; - __IM uint8_t RESERVED8; + __IM uint32_t RESERVED2[499]; union { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - union + struct { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; }; - __IM uint8_t RESERVED9; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ union { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - union + struct { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; }; - __IM uint8_t RESERVED10; + __IM uint8_t RESERVED; union { union { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; }; union { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; }; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED1; union { union { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; }; union { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; }; }; - __IM uint8_t RESERVED12; + __IM uint8_t RESERVED2; union { union { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ struct { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; }; union { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; }; }; + __IM uint8_t RESERVED3; union { union { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; }; union { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ struct { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; }; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; + __IM uint8_t RESERVED4; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ union { union { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; }; union { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; }; }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; + __IM uint8_t RESERVED7; union { union { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; }; union { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; }; }; + __IM uint8_t RESERVED8; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct + union { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; - union - { union { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; }; + }; + __IM uint8_t RESERVED9; + union + { union { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ struct { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; }; union { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; }; }; + __IM uint8_t RESERVED10; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct + union { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; - struct + union { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct + union { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; }; + __IM uint8_t RESERVED12; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - struct + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; }; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - struct + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; }; + __IM uint8_t RESERVED15; union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ struct { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ struct { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - union + struct { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - union + struct { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; }; }; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct + union { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; - struct + union { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct + union { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; - struct + union { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; - struct + union { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct + union { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; - struct + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - struct + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; - __IM uint32_t RESERVED1; union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint32_t RESERVED5[2]; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint32_t RESERVED3[79]; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED4[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; - __IM uint8_t RESERVED3[179]; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED13; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; + __IM uint8_t RESERVED3[179]; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED4[11]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -12385,7 +12571,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14117,14 +14314,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14138,7 +14335,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -14254,7 +14480,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2_BASE 0x4009F200UL #define R_IWDT_BASE 0x40083200UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -14291,7 +14516,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -14326,8 +14550,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -14375,7 +14598,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -14412,7 +14634,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -14588,17 +14809,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -14615,6 +15010,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -14680,62 +15077,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -14903,89 +15284,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -15764,10 +16062,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16425,6 +16733,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -17482,30 +17797,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -17884,17 +18215,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -19153,121 +19483,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -19818,6 +20033,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -20909,12 +21127,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h index f4d79648b..7b2680b2b 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,891 +400,1286 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CAN0_MB [MB] (Mailbox) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED1; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED2[3]; -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED4; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED5; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED7; -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ - - struct + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; - }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - union - { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; - struct + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED8; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED9; -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED10; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct + union { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { union { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { - __IM uint8_t RESERVED[389]; + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint8_t RESERVED1; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ union { - union + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; }; - __IM uint8_t RESERVED3[3]; union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; }; - __IM uint8_t RESERVED4; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_BUS_B_CSa [CSa] (CS Registers) + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; __IM uint16_t RESERVED; union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; } AGTMR1_b; }; @@ -3073,16 +3465,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4206,7 +4659,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6499,46 +6967,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7035,10 +7538,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -7127,37 +7630,46 @@ typedef struct /*!< (@ 0x40083200) R_IWDT Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8049,2490 +8561,2164 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure uint32_t : 2; __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + uint32_t : 27; + } SFMSPC_b; }; - __IM uint8_t RESERVED7; union { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - union + struct { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; - __IM uint8_t RESERVED8; + __IM uint32_t RESERVED2[499]; union { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - union + struct { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; }; - __IM uint8_t RESERVED9; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ union { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - union + struct { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; }; - __IM uint8_t RESERVED10; + __IM uint8_t RESERVED; union { union { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; }; union { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; }; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED1; union { union { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; }; union { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; }; }; - __IM uint8_t RESERVED12; + __IM uint8_t RESERVED2; union { union { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ struct { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; }; union { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; }; }; + __IM uint8_t RESERVED3; union { union { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; }; union { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ struct { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; }; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; + __IM uint8_t RESERVED4; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ union { union { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; }; union { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; }; }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; + __IM uint8_t RESERVED7; union { union { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; }; union { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; }; }; + __IM uint8_t RESERVED8; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct + union { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; - union - { union { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; }; + }; + __IM uint8_t RESERVED9; + union + { union { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ struct { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; }; union { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; }; }; + __IM uint8_t RESERVED10; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct + union { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; - struct + union { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct + union { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; }; + __IM uint8_t RESERVED12; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - struct + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; }; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - struct + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; }; + __IM uint8_t RESERVED15; union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ struct { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ struct { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - union + struct { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - union + struct { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; }; }; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct + union { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; - struct + union { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct + union { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; - struct + union { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; - struct + union { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct + union { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; - struct + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - struct + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; - __IM uint32_t RESERVED1; union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint32_t RESERVED5[2]; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint32_t RESERVED3[79]; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED4[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; - __IM uint8_t RESERVED3[179]; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED13; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; + __IM uint8_t RESERVED3[179]; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED4[11]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -12385,7 +12571,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14220,14 +14417,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14241,7 +14438,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -14357,7 +14583,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2_BASE 0x4009F200UL #define R_IWDT_BASE 0x40083200UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -14394,7 +14619,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -14430,8 +14654,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -14479,7 +14702,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -14516,7 +14738,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -14693,17 +14914,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -14720,6 +15115,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -14785,62 +15182,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -15008,89 +15389,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -15869,10 +16167,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16530,6 +16838,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -17587,30 +17902,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -17989,17 +18320,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -19258,121 +19588,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -19923,6 +20138,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -21045,12 +21263,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h index d0ee3dd15..7297011a3 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4T1BB.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,9281 +400,9186 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - uint32_t : 3; - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - uint32_t : 4; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - uint32_t : 1; - } FDCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; + __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint32_t RESERVED[3]; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + __IM uint32_t RESERVED5; -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - uint32_t : 3; - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 23; - } P1_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED9; -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ union { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 6; - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct + union { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; - struct + union { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct + union { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; - struct + union { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; -} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ /** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct + union { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; - struct + union { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; -} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; -} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED[104]; -} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ typedef struct { union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ /** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) */ typedef struct { union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; }; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; }; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) */ typedef struct { union { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_RTC_RTCCR [RTCCR] (AGTIO I/O direction control register) + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) AGTIO I/O direction control register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ struct { - uint8_t : 7; - __IOM uint8_t TCEN : 1; /*!< [7..7] Select AGTIO I/O direction as input */ - } RTCCR_b; + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_BUS_B_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) - */ -typedef struct -{ union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; }; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) */ typedef struct { union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; }; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ - union - { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ - - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; - }; +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ + __IM uint16_t RESERVED2; -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ -/* =========================================================================================================================== */ -/* ================ R_ACMPHS0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief High-Speed Analog Comparator (R_ACMPHS0) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ - -typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +typedef struct { union { - __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ - __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ - __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ - __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ - __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ - __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ - } CMPCTL_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; - __IM uint8_t RESERVED[3]; + __IM uint16_t RESERVED; union { - __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ - uint8_t : 4; - } CMPSEL0_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; - __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ - uint8_t : 2; - } CMPSEL1_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; - __IM uint8_t RESERVED2[3]; union { - __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ - uint8_t : 7; - } CMPMON_b; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; - __IM uint8_t RESERVED3[3]; union { - __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ - uint8_t : 6; - __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ - } CPIOC_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +typedef struct { union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (AGTIO I/O direction control register) + */ +typedef struct +{ union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) AGTIO I/O direction control register */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + uint8_t : 7; + __IOM uint8_t TCEN : 1; /*!< [7..7] Select AGTIO I/O direction as input */ + } RTCCR_b; }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - union + struct { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +{ union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; }; + __IM uint8_t RESERVED[3]; union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; }; + __IM uint8_t RESERVED1[3]; union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; }; + __IM uint8_t RESERVED2[3]; union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - struct + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; - __IM uint8_t RESERVED7; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; - __IM uint8_t RESERVED11; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; + __IM uint8_t RESERVED5; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; - __IM uint8_t RESERVED14; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED10; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; union { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; - __IM uint32_t RESERVED23[3]; union { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint16_t RESERVED24; union { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; union { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ struct { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; union { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - uint32_t : 1; - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; union { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; - } PSARD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; union { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; - } MSSAR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; union { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; + __IM uint8_t RESERVED14; union { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; - }; - - union - { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ - - struct - { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; union { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; union { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED; + __IM uint32_t RESERVED23[3]; union { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - uint32_t : 3; - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ struct { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 4; - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - uint32_t : 15; - } CFDGCTR_b; + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; }; union { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ struct { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; union { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ struct { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - uint32_t : 12; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - uint32_t : 15; - } CFDGERFL_b; + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; union { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; union { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; union { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register - * 0 */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; }; union { - __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ struct { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; }; union { - __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ struct { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; }; union { - __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration - * Register */ + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ struct { - __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ - } CFDRMIEC_b; + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; }; union { - __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - uint32_t : 16; - } CFDRFCC_b[2]; + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; }; union { - __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - uint32_t : 16; - } CFDRFSTS_b[2]; + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[2]; + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[1]; + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; }; union { - __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - uint32_t : 16; - } CFDCFSTS_b[1]; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[1]; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; union { - __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; - struct + union + { + union { - __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ - uint32_t : 6; - __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ - uint32_t : 23; - } CFDFESTS_b; + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ }; + __IM uint32_t RESERVED5[46]; union { - __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ struct { - __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ - uint32_t : 6; - __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ - uint32_t : 23; - } CFDFFSTS_b; + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; union { - __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; - struct - { - __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ - uint32_t : 6; - __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ - uint32_t : 23; - } CFDFMSTS_b; + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ union { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 31; - } CFDRFISTS_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; union { - __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[4]; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; union { - __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ struct { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[4]; + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; }; union { - __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status - * Register */ + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ struct { - __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ - uint32_t : 28; - } CFDTMTRSTS_b[1]; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request - * Status Register */ + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ struct { - __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 28; - } CFDTMTARSTS_b[1]; + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; }; + __IM uint8_t RESERVED; union { - __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status - * Register */ + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ struct { - __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 28; - } CFDTMTCSTS_b[1]; + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; }; union { - __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ struct { - __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ - uint32_t : 28; - } CFDTMTASTS_b[1]; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; union { - __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration - * Register */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ - uint32_t : 28; - } CFDTMIEC_b[1]; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; union { - __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ - uint32_t : 22; - } CFDTXQCC0_b[1]; + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; }; union { - __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 18; - } CFDTXQSTS0_b[1]; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; }; union { - __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[1]; + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; }; union { - __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ struct { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - uint32_t : 21; - } CFDTHLCC_b[1]; + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; }; union { - __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ struct { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[1]; + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; }; union { - __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ struct { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[1]; + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; }; union { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ struct { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - uint32_t : 27; - } CFDGTINTSTS0_b; + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; }; union { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ struct { - uint32_t : 16; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; }; union { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ struct { - uint32_t : 2; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; }; union { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ struct { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; }; - __IM uint32_t RESERVED1; union { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ struct { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ struct { - __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ - uint32_t : 27; - } CFDGAFLIGNENT_b; + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; }; union { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ struct { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; }; union { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ struct { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - uint32_t : 23; - } CFDCDTCT_b; + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; }; union { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ struct { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - uint32_t : 23; - } CFDCDTSTS_b; + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; }; - __IM uint32_t RESERVED3[2]; union { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ struct { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; }; - __IM uint32_t RESERVED4[9]; - __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED5[24]; union { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ struct { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; }; - __IM uint32_t RESERVED6[104]; - __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ - __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ - __IM uint32_t RESERVED7[3]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ - __IM uint32_t RESERVED8[118]; - __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ -} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ union { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ struct { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; }; union { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ struct { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; }; - __IM uint16_t RESERVED; union { - union + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 31; + } CFDRFISTS_b; + }; - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ - union + struct { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; }; union { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ - union + struct { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; }; union { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ struct { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ union { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ struct { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; }; union { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ struct { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; }; union { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ struct { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; }; union { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ struct { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; }; union { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ struct { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; }; union { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ struct { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; }; union { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; }; - __IM uint16_t RESERVED[9]; union { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ struct { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ struct { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ union { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ struct { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ struct { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 14; - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller Common (R_DMA) - */ -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ union { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ struct { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; union { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ struct { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; }; - __IM uint32_t RESERVED3[15]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ - -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief DMA Controller (R_DMAC0) - */ + __IM uint32_t RESERVED1; -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ union { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ struct { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ struct { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; }; union { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ struct { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; }; union { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ struct { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; }; union { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ struct { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; }; - __IM uint8_t RESERVED; + __IM uint32_t RESERVED3[2]; union { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ struct { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; union { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ struct { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ - } DMAMD_b; + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; }; - __IM uint16_t RESERVED1; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ union { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ struct { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address update mode for transfer source or destination. */ - } DMOFR_b; + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; }; union { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ struct { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - struct + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; }; union { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - struct + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ struct { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ union { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ struct { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; }; union { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ struct { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ union { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ struct { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ struct { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; }; union { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ struct { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ -/** - * @brief Data Transfer Controller (R_DTC) - */ + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ union { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ struct { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; + __IM uint16_t RESERVED[9]; union { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ - } DTCVBR_b; + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; }; - __IM uint32_t RESERVED2; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; union { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ union { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ struct { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; }; + __IM uint32_t RESERVED[3]; union { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; - } DTCCR_SEC_b; + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; + __IM uint32_t RESERVED1[123]; union { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ struct { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ -/* ================ R_ELC ================ */ +/* ================ R_DMA ================ */ /* =========================================================================================================================== */ /** - * @brief Event Link Controller (R_ELC) + * @brief DMA Controller Common (R_DMA) */ -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ { union { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ struct { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; union { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ struct { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; }; - __IM uint16_t RESERVED3; + __IM uint32_t RESERVED3[15]; union { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ struct { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; - }; - __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ +} R_DMA_Type; /*!< Size = 160 (0xa0) */ /* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ +/* ================ R_DMAC0 ================ */ /* =========================================================================================================================== */ /** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + * @brief DMA Controller (R_DMAC0) */ -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ { union { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; union { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; union { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; union { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ struct { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ struct { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ struct { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; }; - __IM uint32_t RESERVED8[3]; union { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ struct { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10[12]; + __IM uint16_t RESERVED1; union { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ struct { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; }; - __IM uint16_t RESERVED11; union { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ struct { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; }; - __IM uint16_t RESERVED12; union { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ struct { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; }; union { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ struct { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ struct { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[4]; union { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ struct { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[11]; union { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ struct { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - union - { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; - }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; +/** + * @brief Data Operation Circuit (R_DOC) + */ +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ union { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ struct { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; }; + __IM uint8_t RESERVED; union { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ struct { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; }; union { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ struct { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; }; - __IM uint16_t RESERVED23; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ union { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ struct { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; }; - __IM uint16_t RESERVED24; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; union { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ struct { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; }; - __IM uint16_t RESERVED25; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; + __IM uint32_t RESERVED2; union { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ struct { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; }; - __IM uint16_t RESERVED1; + __IM uint8_t RESERVED3; union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ - uint16_t : 15; - } FCACHEIV_b; + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; }; - __IM uint16_t RESERVED2[11]; union { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ struct { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; - } FSAR_b; + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ +} R_DTC_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ +/* ================ R_ELC ================ */ /* =========================================================================================================================== */ /** - * @brief General PWM Timer (R_GPT0) + * @brief Event Link Controller (R_ELC) */ -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ { union { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ struct { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; union { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ struct { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; }; + __IM uint16_t RESERVED3; union { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ struct { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; }; + __IM uint16_t RESERVED4; union { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ struct { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ union { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - struct - { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; union { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ struct { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; union { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ struct { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ struct { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; }; union { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ struct { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; }; + __IM uint32_t RESERVED8[3]; union { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ struct { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; - } GTICASR_b; + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; union { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ struct { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; - } GTICBSR_b; + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; }; + __IM uint16_t RESERVED11; union { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ struct { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; }; + __IM uint16_t RESERVED12; union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - } GTUDDTYC_b; + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; }; union { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ struct { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; union { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ struct { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; - }; - - union - { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ - - struct - { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; - }; - - union - { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ - - struct - { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[11]; union { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ struct { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ struct { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; union { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ struct { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; }; union { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ struct { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; }; union { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ struct { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; }; + __IM uint16_t RESERVED23; union { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ struct { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ struct { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; }; + __IM uint16_t RESERVED25; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - union - { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ - - struct - { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; - }; +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ +/** + * @brief Flash Memory Cache (R_FCACHE) + */ - struct - { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; - }; +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; union { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ struct { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; }; + __IM uint16_t RESERVED2[11]; union { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ struct { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; union { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - union - { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; - }; +/** + * @brief General PWM Timer (R_GPT0) + */ +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ union { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; }; union { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ struct { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; - }; - - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ - - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; - - union - { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ - - struct - { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; - }; - - union - { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ - - struct - { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; - }; - - union - { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ - - struct - { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; }; union { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ struct { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; }; union { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ struct { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; }; union { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ struct { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; }; - __IM uint32_t RESERVED[4]; union { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ struct { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; }; union { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ struct { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; }; - __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ struct { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; }; union { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ struct { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ struct { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ union { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ struct { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ union { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; }; - __IM uint32_t RESERVED[60]; union { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ struct { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; union { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; + uint32_t : 8; + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; union { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ struct { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ struct { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ struct { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; }; union { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ struct { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; }; - __IM uint32_t RESERVED10[6]; union { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ struct { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; union { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ struct { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; }; - __IM uint32_t RESERVED16[24]; union { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ struct { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ -/** - * @brief I2C Bus Interface (R_IIC0) - */ - -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ union { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ struct { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; }; union { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ struct { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; }; union { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ struct { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; }; union { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ struct { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; }; union { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ struct { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; }; union { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ struct { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; }; union { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ struct { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; }; union { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ struct { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; }; union { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ struct { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; }; union { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ struct { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ struct { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; }; union { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ struct { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; }; union { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ struct { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; }; union { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ struct { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ struct { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; }; union { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ - -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ union { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ struct { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ struct { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; }; union { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ struct { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; }; union { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ struct { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; }; - __IM uint8_t RESERVED1; + __IM uint32_t RESERVED[4]; union { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ struct { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ union { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ struct { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; }; - __IM uint32_t RESERVED[3]; + __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ struct { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; }; union { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ struct { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ struct { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; }; - __IM uint32_t RESERVED1; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ union { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; }; - __IM uint32_t RESERVED2[2]; + __IM uint32_t RESERVED[15]; union { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ struct { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ struct { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ union { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ struct { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; }; + __IM uint32_t RESERVED[60]; union { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ struct { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; }; - __IM uint32_t RESERVED3; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; union { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ struct { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; }; - __IM uint32_t RESERVED4[4]; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; union { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ struct { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; }; - __IM uint32_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; union { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ struct { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ struct { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; - } SVCTL_b; + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; }; - __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ struct { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; }; + __IM uint32_t RESERVED10[6]; union { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ struct { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; union { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ struct { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; union { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ struct { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; + __IM uint32_t RESERVED16[24]; union { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ struct { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ - union - { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; - }; +/** + * @brief I2C Bus Interface (R_IIC0) + */ +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ union { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ struct { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; }; union { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ struct { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; }; union { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ struct { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; }; - __IM uint32_t RESERVED7; union { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ struct { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; }; - __IM uint32_t RESERVED8; union { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ struct { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; }; union { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ struct { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; }; - __IM uint32_t RESERVED9[2]; union { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ struct { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; }; - __IM uint32_t RESERVED10[3]; union { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ struct { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; }; - __IM uint32_t RESERVED11[31]; union { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ struct { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; }; - __IM uint32_t RESERVED12[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; union { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ struct { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ struct { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; }; - __IM uint32_t RESERVED15[10]; union { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ struct { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; }; - __IM uint32_t RESERVED16[3]; union { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ struct { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; - } BST_b; + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; }; union { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ struct { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; - } BSTE_b; + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; }; + __IM uint8_t RESERVED[2]; union { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ struct { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; - } BIE_b; + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; }; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; - } BSTFC_b; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ union { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ struct { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ struct { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; }; union { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ struct { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; }; union { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ struct { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; }; - __IM uint32_t RESERVED17[8]; + __IM uint8_t RESERVED1; union { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ struct { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ +typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ +{ union { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ struct { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; - } SVST_b; + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; }; + __IM uint32_t RESERVED[3]; union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; }; - __IM uint32_t RESERVED18[2]; union { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; }; - __IM uint32_t RESERVED19; union { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; }; - __IM uint32_t RESERVED20; + __IM uint32_t RESERVED1; union { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; }; - __IM uint32_t RESERVED21; union { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; }; - __IM uint32_t RESERVED22[24]; + __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ struct { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; }; - __IM uint32_t RESERVED23[3]; union { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; }; union { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; }; union { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; }; - __IM uint32_t RESERVED24[5]; + __IM uint32_t RESERVED3; union { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ uint32_t : 16; - } MSDCT1_b; + } BFCTL_b; }; union { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; }; + __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT3_b; + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; }; - __IM uint32_t RESERVED25[16]; union { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ struct { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ uint32_t : 2; - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED26; union { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ struct { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; }; - __IM uint32_t RESERVED27[7]; union { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ struct { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ - uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; }; union { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ struct { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; }; union { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ struct { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; }; union { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ struct { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; }; union { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ struct { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; }; union { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ struct { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ - uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ - uint32_t : 16; - } CGDVST_b; + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ struct { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ struct { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; }; union { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ struct { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; }; + __IM uint32_t RESERVED9[2]; union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; }; - __IM uint32_t RESERVED28[2]; + __IM uint32_t RESERVED10[3]; union { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ struct { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED11[31]; union { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ struct { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ struct { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ - uint32_t : 16; - } NDBSTLV0_b; + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; }; - __IM uint32_t RESERVED30[9]; union { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ struct { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; }; - __IM uint32_t RESERVED31[2]; + __IM uint32_t RESERVED15[10]; union { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ struct { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; }; + __IM uint32_t RESERVED16[3]; union { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ struct { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ - -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ -/** - * @brief System-Module Stop (R_MSTP) - */ - -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ union { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ struct { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; }; union { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; }; union { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ struct { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; }; union { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ struct { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; }; union { - union + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; - union - { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ -/** - * @brief I/O Ports (R_PORT0) - */ + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ union { - union + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ struct { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; }; + __IM uint32_t RESERVED21; union { - union + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ struct { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; }; union { - union + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ struct { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; }; union { - union + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ struct { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ -/** - * @brief I/O Ports-PFS (R_PFS) - */ + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ union { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ -/** - * @brief I/O Ports-MISC (R_PMISC) - */ + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ union { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ struct { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ struct { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; }; - __IM uint8_t RESERVED1; union { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ struct { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; union { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ struct { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ -/** - * @brief Reset Control (R_RTC) - */ + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - __IM uint8_t RESERVED[34]; - __IOM uint8_t RCR1; /*!< (@ 0x00000022) Reset Control Register 1 */ - __IM uint8_t RESERVED1; + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; union { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) Reset Control Register 2 */ + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ struct { - uint8_t : 1; - __IOM uint8_t RESET : 1; /*!< [1..1] Software Reset */ - uint8_t : 6; - } RCR2_b; + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; }; - __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) Reset Control Register 4 */ + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ struct { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 7; - } RCR4_b; + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; }; - __IM uint8_t RESERVED3[23]; - __IOM R_RTC_RTCCR_Type RTCCR[2]; /*!< (@ 0x00000040) AGTIO I/O direction control register */ -} R_RTC_Type; /*!< Size = 68 (0x44) */ -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ -/** - * @brief Serial Communications Interface (R_SCI0) - */ + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ union { - union + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ - union + struct { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; }; union { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ struct { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; }; + __IM uint32_t RESERVED30[9]; union { - union + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ - union + struct { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; }; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ struct { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ union { - union + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ - union + struct { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ struct { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; }; union { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ struct { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; }; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ struct { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; }; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ struct { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; }; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct + union { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; - struct + union { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; +/** + * @brief I/O Ports (R_PORT0) + */ +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct + union { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; }; union { union { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ struct { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; }; struct { union { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ struct { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; }; union { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ struct { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; }; }; }; @@ -9686,1114 +9588,1398 @@ typedef struct /*!< (@ 0x40118000) R_SCI0 Structure { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ struct { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; }; + }; + union + { union { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ struct { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; }; struct { union { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ struct { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; }; union { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ struct { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; }; }; }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ struct { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Reset Control (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + __IM uint8_t RESERVED[34]; + __IOM uint8_t RCR1; /*!< (@ 0x00000022) Reset Control Register 1 */ + __IM uint8_t RESERVED1; union { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) Reset Control Register 2 */ struct { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + uint8_t : 1; + __IOM uint8_t RESET : 1; /*!< [1..1] Software Reset */ + uint8_t : 6; + } RCR2_b; }; + __IM uint8_t RESERVED2[3]; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) Reset Control Register 4 */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 7; + } RCR4_b; }; + __IM uint8_t RESERVED3[23]; + __IOM R_RTC_RTCCR_Type RTCCR[2]; /*!< (@ 0x00000040) AGTIO I/O direction control register */ +} R_RTC_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - struct + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; }; union { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - struct + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - struct + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct + union { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ uint8_t : 2; - } SPPCR_b; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ uint8_t : 3; - } SPCR3_b; + } PCR_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; - __IM uint8_t RESERVED[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; - __IM uint8_t RESERVED3[179]; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ -/** - * @brief Bus Interface (R_BUS_B) - */ + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED13; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; + __IM uint8_t RESERVED3[179]; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED4[11]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ @@ -12444,7 +12630,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13262,14 +13459,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -13283,7 +13480,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -13474,7 +13700,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -13508,7 +13733,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TRNG_BASE 0x40162000UL #define R_TSN_CAL_BASE 0x407FB17CUL @@ -13549,8 +13773,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) @@ -13600,7 +13823,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -13634,7 +13856,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TRNG ((R_TRNG_Type *) R_TRNG_BASE) #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) @@ -13810,17 +14031,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -13837,6 +14232,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -14226,62 +14623,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -14399,89 +14780,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ CTRL ================ */ /* =========================================================================================================================== */ @@ -15279,10 +15577,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -15733,6 +16041,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -16790,30 +17105,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -17823,17 +18154,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -18600,121 +18930,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -19148,6 +19363,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -19735,12 +19953,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h index b26edf589..b39d62851 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -588,7 +1154,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -596,34 +1162,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2797,16 +3363,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3990,7 +4617,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6393,46 +7035,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6929,10 +7606,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -11352,7 +12029,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13187,17 +13875,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -13214,6 +14076,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -13279,19 +14143,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -14193,10 +15057,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -14877,6 +15751,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -15974,30 +16855,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -17888,6 +18785,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h index 295f3cee3..e00a40a4a 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,2105 +400,2500 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CAN0_MB [MB] (Mailbox) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED1; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED2[3]; -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED4; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED5; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED7; -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED8; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED9; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED10; -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED11; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct + union { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - union + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - union - { - struct - { - __IM uint16_t RESERVED; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { - __IM uint8_t RESERVED[389]; - union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_CAN0_MB [MB] (Mailbox) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; }; - __IM uint8_t RESERVED1; union { - union + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; }; - __IM uint8_t RESERVED3[3]; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; - __IM uint8_t RESERVED4; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_BUS_B_CSa [CSa] (CS Registers) + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_B_CSb [CSb] (CS Registers) - */ -typedef struct -{ __IM uint16_t RESERVED; union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) - */ -typedef struct -{ union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; - }; - - union - { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ - - struct - { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; union { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - - struct + union { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; - }; + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - union - { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; - }; + union + { + struct + { + __IM uint16_t RESERVED; - union - { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - struct - { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; - }; + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; - union - { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; - struct - { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + * @brief R_PFS_PORT [PORT] (Port [0..14]) */ typedef struct { - union - { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - struct - { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + * @brief R_RTC_CP [CP] (Capture registers) */ typedef struct { + __IM uint8_t RESERVED[2]; + union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - struct + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; }; + __IM uint8_t RESERVED1; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - struct + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; }; + __IM uint8_t RESERVED2; union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - struct + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ -/** @} */ /* End of group Device_Peripheral_clusters */ + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ -/** - * @brief A/D Converter (R_ADC0) - */ + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ struct { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; }; union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ - union + struct { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - struct + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; - __IM uint8_t RESERVED5; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; - __IM uint8_t RESERVED7; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED5; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + union { __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ @@ -3073,33 +3465,94 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; - struct - { + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ uint8_t : 7; } CACR0_b; @@ -3963,7 +4416,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6928,46 +7396,81 @@ typedef struct /*!< (@ 0x40169000) R_GPT0 Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7464,10 +7967,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -7556,37 +8059,46 @@ typedef struct /*!< (@ 0x40083200) R_IWDT Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9216,1752 +9728,1426 @@ typedef struct /*!< (@ 0x40118000) R_SCI0 Structure * be 0 without simple I2C mode and asynchronous mode.)In * asynchronous mode, for RXDn input only. In simple I2C mode, * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; - }; - - union - { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ - - struct - { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; - }; - - union - { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ - - struct - { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; - __IM uint32_t RESERVED1; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; + __IM uint32_t RESERVED; union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; }; - __IM uint32_t RESERVED5[2]; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[79]; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint32_t RESERVED4[3]; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; - __IM uint8_t RESERVED3[179]; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; + __IM uint8_t RESERVED[3]; union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED3[179]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; + __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED5[3]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -12814,7 +13000,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14603,14 +14800,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14624,7 +14821,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -14740,7 +14966,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2_BASE 0x4009F200UL #define R_IWDT_BASE 0x40083200UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -14777,7 +15002,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -14811,8 +15035,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -14860,7 +15083,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -14897,7 +15119,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -15072,17 +15293,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -15099,6 +15494,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -15164,62 +15561,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -15387,89 +15768,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -16248,10 +16546,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16805,6 +17113,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -18116,30 +18431,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -18518,17 +18849,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -19787,121 +20117,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -20452,6 +20667,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -21556,12 +21774,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h index 1abd45f0b..b82cde00e 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -304,128 +302,695 @@ typedef struct union { - __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ - uint8_t : 7; - } SDICR_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; union { - __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ - __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ - __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles - * ) */ - uint16_t : 5; - } SDIR_b; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[6]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ union { - __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ - uint8_t : 6; - } SDADR_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; - __IM uint8_t RESERVED10; - __IM uint16_t RESERVED11; + __IM uint16_t RESERVED; union { - __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ - uint32_t : 5; - __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ - __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ - __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ - uint32_t : 2; - __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ - uint32_t : 13; - } SDTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; - } SDMOD_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13; + __IM uint16_t RESERVED2; union { - __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ - uint8_t : 2; - __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ - __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ - uint8_t : 3; - } SDSR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; - __IM uint8_t RESERVED14; - __IM uint16_t RESERVED15; -} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ - - struct - { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; }; + __IM uint32_t RESERVED; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - - struct - { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -453,8 +1018,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -1044,115 +1610,114 @@ typedef struct } R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not * stored. */ - } CTL_b; + } EN_b; }; __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint16_t RESERVED1; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) @@ -3355,16 +3920,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4403,7 +5029,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6696,46 +7337,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7232,10 +7908,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -8461,37 +9137,46 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -12905,7 +13590,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14792,14 +15488,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14813,7 +15509,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -15284,7 +16009,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -15406,7 +16130,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -15619,17 +16342,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -15646,6 +16543,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -16035,62 +16934,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -17036,10 +17919,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -17490,6 +18383,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -18547,30 +19447,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -19580,17 +20496,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -21162,6 +22077,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -22302,12 +23220,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h index 8dc1ba551..18245deb9 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; } STAT_b; }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -616,7 +1182,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -624,34 +1190,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2811,16 +3377,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3944,7 +4571,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6285,46 +6927,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6821,10 +7498,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -12086,7 +12763,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14936,17 +15624,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -14963,6 +15825,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -15039,19 +15903,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -15921,10 +16785,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16582,6 +17456,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -17658,30 +18539,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -20016,6 +20913,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h index 6ad11b9fa..135b666ce 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -616,7 +1182,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -624,34 +1190,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2811,16 +3377,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3944,7 +4571,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -7013,46 +7655,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7549,10 +8226,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -14067,7 +14744,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -16927,17 +17615,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -16954,6 +17816,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -17030,19 +17894,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -17912,10 +18776,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -18573,6 +19447,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -19943,30 +20824,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -23000,6 +23897,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h index be2fe3faf..296d63e0b 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -1526,7 +2092,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -1534,34 +2100,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -3721,16 +4287,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4854,7 +5481,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -10286,46 +10928,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -10822,10 +11499,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -16725,7 +17402,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -19597,17 +20285,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -19624,6 +20486,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -20054,19 +20918,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -20936,10 +21800,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -21597,6 +22471,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -24027,30 +24908,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -26635,6 +27532,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h index acbd8a509..67a5899ac 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,877 +400,1272 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CAN0_MB [MB] (Mailbox) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED1; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED2[3]; -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED4; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED5; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED7; -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED8; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED9; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED10; -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED11; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct + union { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - union + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - union - { - struct - { - __IM uint16_t RESERVED; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { - __IM uint8_t RESERVED[389]; - union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_CAN0_MB [MB] (Mailbox) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; }; - __IM uint8_t RESERVED1; union { - union + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; }; - __IM uint8_t RESERVED3[3]; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; - __IM uint8_t RESERVED4; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_BUS_B_CSa [CSa] (CS Registers) + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_B_CSb [CSb] (CS Registers) - */ -typedef struct -{ __IM uint16_t RESERVED; union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; - __IM uint8_t RESERVED; __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) - */ -typedef struct -{ union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ union { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; }; union @@ -3108,16 +3500,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -4241,7 +4694,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -7262,46 +7730,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7798,10 +8301,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -7890,37 +8393,46 @@ typedef struct /*!< (@ 0x40083200) R_IWDT Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -8812,2490 +9324,2164 @@ typedef struct /*!< (@ 0x64000000) R_QSPI Structure uint32_t : 2; __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; - - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - - struct - { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; - }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ - -/* =========================================================================================================================== */ -/* ================ R_RTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Realtime Clock (R_RTC) - */ - -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ -{ - union - { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - - struct - { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; - }; - __IM uint8_t RESERVED; - - union - { - union - { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; - - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; - }; - __IM uint8_t RESERVED1; - - union - { - union - { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; - - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; - }; - __IM uint8_t RESERVED2; - - union - { - union - { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; - - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; - }; - __IM uint8_t RESERVED3; - - union - { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; - - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; - }; - - union - { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; - - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + uint32_t : 27; + } SFMSPC_b; }; - __IM uint8_t RESERVED7; union { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ - union + struct { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; - __IM uint8_t RESERVED8; + __IM uint32_t RESERVED2[499]; union { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ - union + struct { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; }; - __IM uint8_t RESERVED9; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ union { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ - union + struct { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; }; - __IM uint8_t RESERVED10; + __IM uint8_t RESERVED; union { union { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; }; union { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; }; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED1; union { union { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; }; union { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; }; }; - __IM uint8_t RESERVED12; + __IM uint8_t RESERVED2; union { union { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ struct { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; }; union { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; }; }; + __IM uint8_t RESERVED3; union { union { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ struct { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; }; union { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ struct { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; }; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; - - union - { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ - - struct - { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; - }; - __IM uint8_t RESERVED15; - - union - { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - - struct - { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; - }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; - - union - { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ - - struct - { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; - }; - __IM uint8_t RESERVED18; + __IM uint8_t RESERVED4; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ -{ union { union { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; }; union { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; }; }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; - }; + __IM uint8_t RESERVED7; union { union { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; }; union { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; }; }; + __IM uint8_t RESERVED8; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct + union { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; - union - { union { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; }; + }; + __IM uint8_t RESERVED9; + union + { union { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ struct { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; }; union { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; }; }; + __IM uint8_t RESERVED10; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct + union { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; - struct + union { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct + union { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; }; + __IM uint8_t RESERVED12; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - struct + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; }; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - struct + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; }; + __IM uint8_t RESERVED15; union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ struct { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ struct { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ - union + struct { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - union + struct { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; }; }; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct + union { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; - struct + union { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct + union { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; - struct + union { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; - struct + union { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ - - struct + union { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; - }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - union - { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; - struct + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - struct + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; - }; + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - union - { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; - __IM uint32_t RESERVED1; union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint32_t RESERVED5[2]; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ - -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint32_t RESERVED3[79]; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED4[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; - __IM uint8_t RESERVED3[179]; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ - - struct - { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED13; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; + __IM uint8_t RESERVED3[179]; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED4[11]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -13148,7 +13334,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14983,14 +15180,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -15004,7 +15201,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -16434,7 +16660,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2_BASE 0x4009F200UL #define R_IWDT_BASE 0x40083200UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -16471,7 +16696,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -16509,8 +16733,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -16560,7 +16783,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -16597,7 +16819,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -16776,17 +16997,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -16803,6 +17198,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -16868,62 +17265,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -17091,89 +17472,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -17965,10 +18263,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -18626,6 +18934,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -19977,30 +20292,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -20379,17 +20710,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -21648,121 +21978,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -22313,6 +22528,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -23435,12 +23653,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h index f95845729..ba02afdc9 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,11558 +400,11600 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ - } FDCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; + __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint32_t RESERVED; + __IM uint32_t RESERVED5; union { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + __IM uint32_t RESERVED7; -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; + __IM uint32_t RESERVED9; union { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; - } P1_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED11; -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ union { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ /** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) */ typedef struct { union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct + union { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; - struct + union { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; + __IM uint32_t RESERVED1; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - - struct - { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct - { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; + __IM uint16_t RESERVED2; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ union { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ typedef struct { union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ + __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ + __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; }; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) */ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; }; - __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ + } FDCFG_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) - */ -typedef struct -{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + __IM uint32_t RESERVED; -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ + uint32_t : 23; + } BLCT_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ + } BLSTS_b; }; - __IM uint16_t RESERVED; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; }; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; }; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; }; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) */ typedef struct { union { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ /** - * @brief R_PFS_PORT [PORT] (Port [0..14]) + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) */ typedef struct { - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; -/** - * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) - */ -typedef struct -{ union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ - __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ - uint8_t : 1; - __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ - uint8_t : 1; - __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ - } RTCCR_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ /** - * @brief R_RTC_CP [CP] (Capture registers) + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) */ typedef struct { - __IM uint8_t RESERVED[2]; - union { - union - { - __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - - struct - { - __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of - * seconds */ - __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of - * seconds */ - uint8_t : 1; - } RSEC_b; - }; + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ - union + struct { - __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ - - struct - { - __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 - * value when a time capture event is detected. */ - } BCNT0_b; - }; + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; }; - __IM uint8_t RESERVED1; union { - union - { - __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - - struct - { - __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - uint8_t : 1; - } RMIN_b; - }; + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - union + struct { - __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ - - struct - { - __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 - * value when a time capture event is detected. */ - } BCNT1_b; - }; + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; }; - __IM uint8_t RESERVED2; union { - union - { - __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - - struct - { - __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of - * minutes */ - __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of - * minutes */ - __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ - uint8_t : 1; - } RHR_b; - }; + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ - union + struct { - __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ - - struct - { - __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 - * value when a time capture event is detected. */ - } BCNT2_b; - }; + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; }; - __IM uint8_t RESERVED3[3]; union { - union - { - __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - - struct - { - __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ - __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ - uint8_t : 2; - } RDAY_b; - }; + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ - union + struct { - __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ - - struct - { - __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 - * value when a time capture event is detected. */ - } BCNT3_b; - }; + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED4; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ union { - __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ struct { - __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ - __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of - * months */ - uint8_t : 3; - } RMON_b; + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; }; - __IM uint8_t RESERVED5[3]; -} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_BUS_B_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) - */ -typedef struct -{ union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; }; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ /** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) */ typedef struct { union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows - * clearing the transaction counter to 0. */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction - * counter function. */ - uint16_t : 6; - } E_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number - * of total packets (number of transactions) to be received - * by the relevant PIPE.When read from: When TRENB = 0: Indicate - * the specified number of transactions.When TRENB = 1: Indicate - * the number of currently counted transactions. */ - } N_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; -} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ - - struct + union { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; - }; + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - union - { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + * @brief R_PFS_PORT [PORT] (Port [0..14]) */ typedef struct { - union - { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - struct - { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; - }; +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; - }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_RTC_CP [CP] (Capture registers) */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +typedef struct { + __IM uint8_t RESERVED[2]; + union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ - struct + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; }; + __IM uint8_t RESERVED1; union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ - struct + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; }; + __IM uint8_t RESERVED2; union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ - struct + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ - struct + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; }; + __IM uint8_t RESERVED4; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; }; union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ - union + struct { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; - __IM uint8_t RESERVED7; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; - __IM uint8_t RESERVED11; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; + __IM uint8_t RESERVED5; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; - __IM uint8_t RESERVED14; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED10; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; - __IM uint8_t RESERVED21; - __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; union { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; - __IM uint32_t RESERVED23[3]; union { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint16_t RESERVED24; union { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ - uint8_t : 7; - } ADPGADBS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; union { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ struct { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; }; - __IM uint16_t RESERVED25; - __IM uint32_t RESERVED26[10]; union { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Peripheral Security Control Unit (R_PSCU) - */ - -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ -{ - __IM uint32_t RESERVED; union { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - uint32_t : 1; - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; union { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; union { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; - } PSARD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; union { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; - } MSSAR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; union { - __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - uint32_t : 15; - __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - uint32_t : 10; - __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; + __IM uint8_t RESERVED14; union { - __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - uint32_t : 10; - __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; union { - __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - uint32_t : 13; - __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; union { - __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - uint32_t : 10; - __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; union { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; - __IM uint8_t RESERVED; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; }; + __IM uint32_t RESERVED23[3]; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; + __IM uint16_t RESERVED24; union { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ struct { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; }; union { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ struct { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; union { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ struct { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; union { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; union { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; union { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; }; union { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ struct { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; }; - __IM uint32_t RESERVED1[3]; union { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ struct { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; }; union { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ struct { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; }; - __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; }; union { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; }; - __IM uint32_t RESERVED3[18]; union { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; - __IM uint32_t RESERVED4[18]; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; - __IM uint32_t RESERVED5[18]; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; union { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ - - struct - { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ }; - __IM uint32_t RESERVED6[18]; + __IM uint32_t RESERVED4[58]; union { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ - - struct + union { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ }; + __IM uint32_t RESERVED5[46]; union { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ - - struct - { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ }; + __IM uint32_t RESERVED6[33]; union { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ struct { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; union { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ - - struct - { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ }; + __IM uint32_t RESERVED9[28]; union { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ - - struct - { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ union { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; union { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; union { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ struct { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; }; union { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ struct { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ struct { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; }; - __IM uint32_t RESERVED7[2]; + __IM uint8_t RESERVED; union { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ struct { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; }; - __IM uint32_t RESERVED8[288]; union { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ struct { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; - __IM uint32_t RESERVED9[288]; union { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; - __IM uint32_t RESERVED10[36]; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED[25]; union { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ struct { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; }; - __IM uint32_t RESERVED11[36]; union { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ struct { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 2; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ + uint32_t : 14; + } CFDGCTR_b; }; - __IM uint32_t RESERVED12[36]; union { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ struct { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; }; - __IM uint32_t RESERVED13[36]; union { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ struct { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ + __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + uint32_t : 1; + __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ + __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ + uint32_t : 6; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; }; - __IM uint32_t RESERVED14[40]; union { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; }; - __IM uint32_t RESERVED15[6]; union { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; }; - __IM uint32_t RESERVED16[6]; union { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; }; - __IM uint32_t RESERVED17[6]; + __IM uint32_t RESERVED1[3]; union { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; }; - __IM uint32_t RESERVED18[6]; union { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; }; - __IM uint32_t RESERVED19[6]; + __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; }; - __IM uint32_t RESERVED20[6]; union { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; }; - __IM uint32_t RESERVED21[6]; union { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; }; - __IM uint32_t RESERVED22[6]; union { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; }; - __IM uint32_t RESERVED23[6]; + __IM uint32_t RESERVED3[18]; union { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement + * Registers */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; }; - __IM uint32_t RESERVED24[6]; + __IM uint32_t RESERVED4[18]; union { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; }; - __IM uint32_t RESERVED25[6]; + __IM uint32_t RESERVED5[18]; union { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ + __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; }; - __IM uint32_t RESERVED26[6]; + __IM uint32_t RESERVED6[18]; union { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ struct { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ + uint32_t : 18; + } CFDFESTS_b; }; union { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ struct { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ + uint32_t : 18; + } CFDFFSTS_b; }; union { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ struct { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; }; - __IM uint32_t RESERVED27; union { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ struct { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; }; union { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ struct { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; }; union { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ struct { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; }; union { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ struct { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; }; - __IM uint32_t RESERVED28[24]; union { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ struct { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; }; - __IM uint32_t RESERVED29[6]; union { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ struct { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ + uint32_t : 26; + } CFDCFMOWSTS_b; }; - __IM uint32_t RESERVED30[6]; union { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ struct { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ + uint32_t : 18; + } CFDFFFSTS_b; }; - __IM uint32_t RESERVED31[46]; + __IM uint32_t RESERVED7[2]; union { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ struct { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; }; - __IM uint32_t RESERVED32; + __IM uint32_t RESERVED8[288]; union { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ struct { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; }; + __IM uint32_t RESERVED9[288]; union { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register */ struct { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; + __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ + uint32_t : 24; + } CFDTMTRSTS_b[4]; }; - __IM uint32_t RESERVED33; + __IM uint32_t RESERVED10[36]; union { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register */ struct { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; + __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 24; + } CFDTMTARSTS_b[4]; }; - __IM uint32_t RESERVED34; + __IM uint32_t RESERVED11[36]; union { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register */ struct { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; + __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 24; + } CFDTMTCSTS_b[4]; }; + __IM uint32_t RESERVED12[36]; union { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ struct { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; + __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ + uint32_t : 24; + } CFDTMTASTS_b[4]; }; + __IM uint32_t RESERVED13[36]; union { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration + * Register */ struct { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; + __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ + uint32_t : 24; + } CFDTMIEC_b[4]; }; + __IM uint32_t RESERVED14[40]; union { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ struct { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; - }; - __IM uint32_t RESERVED35; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; union { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ struct { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS0_b[2]; }; + __IM uint32_t RESERVED16[6]; union { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ struct { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; }; - __IM uint32_t RESERVED36[2]; + __IM uint32_t RESERVED17[6]; union { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ struct { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; }; + __IM uint32_t RESERVED18[6]; union { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ struct { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS1_b[2]; }; - __IM uint32_t RESERVED37[2]; + __IM uint32_t RESERVED19[6]; union { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ + __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ struct { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; }; - __IM uint32_t RESERVED38[10]; + __IM uint32_t RESERVED20[6]; union { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ struct { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; }; - __IM uint32_t RESERVED39[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED40[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED41[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED42[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED43[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED44[252]; + __IM uint32_t RESERVED21[6]; union { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ struct { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS2_b[2]; }; - __IM uint32_t RESERVED45[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ - -/* =========================================================================================================================== */ -/* ================ R_CRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) - */ + __IM uint32_t RESERVED22[6]; -typedef struct /*!< (@ 0x40108000) R_CRC Structure */ -{ union { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ struct { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; }; + __IM uint32_t RESERVED23[6]; union { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ struct { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; }; - __IM uint16_t RESERVED; + __IM uint32_t RESERVED24[6]; union { - union + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + + struct { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 13; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; + union + { + __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ - union + struct { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; }; + __IM uint32_t RESERVED26[6]; union { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ - union + struct { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; }; union { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ struct { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU) - */ -typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ -{ union { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ struct { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; }; + __IM uint32_t RESERVED27; union { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ struct { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; }; union { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ struct { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; }; union { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ struct { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 25; + } CFDTXQOFRISTS_b; }; union { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ struct { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; }; + __IM uint32_t RESERVED28[24]; union { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ struct { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; }; + __IM uint32_t RESERVED29[6]; union { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; }; + __IM uint32_t RESERVED30[6]; union { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; }; + __IM uint32_t RESERVED31[46]; union { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ struct { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; }; + __IM uint32_t RESERVED32; union { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ struct { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; + __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; }; union { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ struct { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; }; + __IM uint32_t RESERVED33; union { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ struct { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; }; + __IM uint32_t RESERVED34; union { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ struct { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; }; union { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ struct { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; + __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ + uint32_t : 7; + __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ + __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ + __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ + __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ + uint32_t : 16; + } CFDGLOTB_b; }; union { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ struct { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; + __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ + uint32_t : 7; + __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ + uint32_t : 13; + } CFDGAFLIGNENT_b; }; union { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ struct { - __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ - __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ - __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ - uint16_t : 2; - __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ - __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ - uint16_t : 7; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; }; - __IM uint16_t RESERVED; - __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_CTSU_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ + __IM uint32_t RESERVED35; -typedef struct /*!< (@ 0x40171000) R_DAC Structure */ -{ union { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ struct { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; }; union { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ struct { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; }; + __IM uint32_t RESERVED36[2]; union { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ struct { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; }; union { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ struct { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; }; + __IM uint32_t RESERVED37[2]; union { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ struct { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; }; + __IM uint32_t RESERVED38[10]; union { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ struct { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; }; + __IM uint32_t RESERVED39[31]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED40[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED41[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED42[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED43[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED44[252]; union { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; }; - __IM uint16_t RESERVED[9]; + __IM uint32_t RESERVED45[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ union { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ struct { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ struct { - __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [0] to 1 to - * select unit 0 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 6; - } DAADUSR_b; + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + __IM uint16_t RESERVED; -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ - -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ union { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ - - struct + union { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; - }; - __IM uint32_t RESERVED[3]; + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - union - { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; - struct + union { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 14; - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ - } DBGSTOPCR_b; - }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_DMA ================ */ -/* =========================================================================================================================== */ + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ -/** - * @brief DMA Controller Common (R_DMA) - */ + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ -{ union { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - struct + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[15]; + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - union - { - __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; - struct + union { - __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ - uint32_t : 5; - __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ - uint32_t : 7; - __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ - uint32_t : 15; - } DMECHR_b; + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; }; - __IM uint32_t RESERVED3[15]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; }; -} R_DMA_Type; /*!< Size = 160 (0xa0) */ + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ +/* ================ R_CTSU ================ */ /* =========================================================================================================================== */ /** - * @brief DMA Controller (R_DMAC0) + * @brief Capacitive Touch Sensing Unit (R_CTSU) */ -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ { union { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ struct { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; }; union { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ struct { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; }; union { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ struct { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; }; union { - __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ struct { - __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block - * transfer counter. */ - __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; }; union { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ struct { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ - uint16_t : 1; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; }; - __IM uint8_t RESERVED; union { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ struct { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; }; union { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ struct { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ - } DMAMD_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; }; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ struct { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address update mode for transfer source or destination. */ - } DMOFR_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; }; union { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ struct { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; }; union { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ struct { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; - }; - - union - { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ - - struct - { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; }; - __IM uint8_t RESERVED2; - __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ - __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ struct { - __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMSBS_b; + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; }; union { - __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ struct { - __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer - * mode */ - __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer - * mode */ - } DMDBS_b; + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; }; union { - __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ struct { - __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ - uint8_t : 7; - } DMBWR_b; + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_DOC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Operation Circuit (R_DOC) - */ -typedef struct /*!< (@ 0x40109000) R_DOC Structure */ -{ union { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ struct { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ struct { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; }; union { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ struct { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_DTC ================ */ +/* ================ R_DAC ================ */ /* =========================================================================================================================== */ /** - * @brief Data Transfer Controller (R_DTC) + * @brief D/A Converter (R_DAC) */ -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ { union { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ struct { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ - } DTCVBR_b; + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ struct { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ uint8_t : 7; - } DTCST_b; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; }; - __IM uint8_t RESERVED3; union { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ struct { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; }; union { - __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ struct { - uint8_t : 4; - __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ - uint8_t : 3; - } DTCCR_SEC_b; + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; - __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ - __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ struct { - __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ - __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ - uint32_t : 7; - __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ - uint32_t : 15; - } DTEVR_b; + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; }; -} R_DTC_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ -/** - * @brief Event Link Controller (R_ELC) - */ - -typedef struct /*!< (@ 0x40082000) R_ELC Structure */ -{ union { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ struct { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ - __IM uint16_t RESERVED2[4]; + __IM uint16_t RESERVED[9]; union { - __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register - * A */ + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ struct { - __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ - __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security - * Attribution */ - __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security - * Attribution */ - uint16_t : 13; - } ELCSARA_b; + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; }; - __IM uint16_t RESERVED3; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; union { - __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register - * B */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ - __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ - __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ - __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ - __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ - __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ - __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ - __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ - __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ - __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ - __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ - __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ - __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ - __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ - __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ - __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ - } ELCSARB_b; + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; }; + __IM uint8_t RESERVED3; __IM uint16_t RESERVED4; - - union - { - __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register - * C */ - - struct - { - __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ - __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ - __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ - uint16_t : 13; - } ELCSARC_b; - }; -} R_ELC_Type; /*!< Size = 126 (0x7e) */ +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ +/* ================ R_DEBUG ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet MAC Controller (R_ETHERC0) + * @brief Debug Function (R_DEBUG) */ -typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ { union { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ struct { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; }; - __IM uint32_t RESERVED; + __IM uint32_t RESERVED[3]; union { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ struct { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; }; - __IM uint32_t RESERVED1; + __IM uint32_t RESERVED1[123]; union { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ struct { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; }; - __IM uint32_t RESERVED2; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ union { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ struct { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; }; - __IM uint32_t RESERVED3; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; union { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ struct { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; }; - __IM uint32_t RESERVED4; + __IM uint32_t RESERVED3[15]; union { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ struct { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; - __IM uint32_t RESERVED5[5]; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ union { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ struct { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; }; - __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ struct { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; }; union { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ struct { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; }; union { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ struct { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; }; - __IM uint32_t RESERVED7; union { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ struct { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ struct { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; - }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ - - union - { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ - - struct - { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; }; - __IM uint32_t RESERVED8[20]; union { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ struct { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; }; - __IM uint32_t RESERVED9; + __IM uint16_t RESERVED1; union { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ struct { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; }; - __IM uint32_t RESERVED10; union { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ struct { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ union { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ struct { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; }; union { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ struct { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; }; - __IM uint32_t RESERVED11; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ struct { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; }; union { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ struct { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; }; union { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ struct { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ union { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ struct { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ struct { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; }; union { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ struct { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ +} R_DOC_Type; /*!< Size = 6 (0x6) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ +/* ================ R_DTC ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + * @brief Data Transfer Controller (R_DTC) */ -typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ { union { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ struct { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; }; - __IM uint32_t RESERVED; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; union { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ struct { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; }; - __IM uint32_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ struct { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; }; - __IM uint32_t RESERVED2; + __IM uint8_t RESERVED3; union { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ struct { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; }; - __IM uint32_t RESERVED3; union { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ struct { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; }; - __IM uint32_t RESERVED4; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; union { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ struct { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; }; - __IM uint32_t RESERVED5; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ union { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ struct { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; }; - __IM uint32_t RESERVED6; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; union { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ struct { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; }; - __IM uint32_t RESERVED7; + __IM uint16_t RESERVED3; union { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ struct { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; }; - __IM uint32_t RESERVED8; + __IM uint16_t RESERVED4; union { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ struct { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; }; - __IM uint32_t RESERVED9; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ +{ union { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ struct { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; }; - __IM uint32_t RESERVED10; + __IM uint32_t RESERVED; union { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ struct { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; }; - __IM uint32_t RESERVED11[2]; + __IM uint32_t RESERVED1; union { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ struct { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ struct { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ struct { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ struct { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; }; - __IM uint32_t RESERVED12; + __IM uint32_t RESERVED5[5]; union { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ struct { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ struct { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ uint32_t : 27; - } TRIMD_b; + } IPGR_b; }; - __IM uint32_t RESERVED13[18]; union { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ struct { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; }; union { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ struct { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; }; - __IM uint32_t RESERVED14; + __IM uint32_t RESERVED7; union { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ struct { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; }; union { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ struct { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ union { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ -/* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; -/** - * @brief Flash Application Command Interface (R_FACI_HP) - */ + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ -{ - __IM uint32_t RESERVED[4]; + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; union { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ union { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ struct { - uint8_t : 3; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; union { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ struct { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; + __IM uint32_t RESERVED11; union { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ struct { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FSADDR_b; + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; }; union { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ struct { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in 'Blank Check' command. These - * bits can be written when FRDY bit of FSTATR register is - * '1'. Writing to these bits in FRDY = '0' is ignored. */ - } FEADDR_b; + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; }; - __IM uint32_t RESERVED8[3]; union { - __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ struct { - __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY bits is D9h.Written values - * are not retained by these bits (always read as 0x00).Only - * secure access can write to this register. Both secure access - * and non-secure read access are allowed. Non-secure writeaccess - * is denied, but TrustZo */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FMEPROT_b; + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10[12]; union { - __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ struct { - __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be - * written when the FRDY bit in the FSTATR register is 1. - * Writing to this bit is ignored when the FRDY bit is 0.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0x78.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT0_b; + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; }; - __IM uint16_t RESERVED11; union { - __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ struct { - __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit - * is only possible when the FRDY bit in the FSTATR register - * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing - * to this bit is only possible when 16 bits are written and - * the value written to the KEY[7:0] bits is 0xB1.Written - * values are not retained by these bits (always read as 0x00). */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FBPROT1_b; + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; }; - __IM uint16_t RESERVED12; union { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ struct { - uint32_t : 6; - __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ - uint32_t : 1; - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - uint32_t : 4; - __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ - __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ - __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ - __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ - uint32_t : 8; - } FSTATR_b; + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ +typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ +{ union { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ struct { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is '1'. Writing to this bit - * in FRDY = '0' is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; + __IM uint32_t RESERVED; union { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ struct { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[4]; + __IM uint32_t RESERVED1; union { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ struct { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; }; - __IM uint16_t RESERVED17; - __IM uint32_t RESERVED18[11]; + __IM uint32_t RESERVED2; union { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ struct { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; + __IM uint32_t RESERVED3; union { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ struct { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; }; - __IM uint8_t RESERVED21; - __IM uint16_t RESERVED22; + __IM uint32_t RESERVED4; union { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ struct { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in 'Blank Check' - * command execution. */ - uint32_t : 13; - } FPSADDR_b; + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; }; + __IM uint32_t RESERVED5; union { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ struct { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and 'Config Clear' - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; }; + __IM uint32_t RESERVED6; union { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ struct { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; }; - __IM uint16_t RESERVED23; + __IM uint32_t RESERVED7; union { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ struct { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is '1'. - * Writing to this bit in FRDY = '0' is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; }; - __IM uint16_t RESERVED24; + __IM uint32_t RESERVED8; union { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ struct { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is '1'. Writing to this bit in FRDY - * = '0' is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; }; - __IM uint16_t RESERVED25; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; + __IM uint32_t RESERVED9; union { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ struct { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; }; - __IM uint16_t RESERVED1; + __IM uint32_t RESERVED10; union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ - uint16_t : 15; - } FCACHEIV_b; + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; }; - __IM uint16_t RESERVED2[11]; + __IM uint32_t RESERVED11[2]; union { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ struct { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4[17]; union { - __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ struct { - __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ - uint16_t : 7; - __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ - uint16_t : 7; - } FSAR_b; + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; }; -} R_FCACHE_Type; /*!< Size = 322 (0x142) */ -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ -/** - * @brief General PWM Timer (R_GPT0) - */ + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; -typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ -{ union { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ struct { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ - __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ - __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ - __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ - uint32_t : 3; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ struct { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - } GTSTR_b; + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; }; union { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ struct { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - } GTSTP_b; + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; }; + __IM uint32_t RESERVED13[18]; union { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ struct { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ - __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ - __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ - __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ - __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ - __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ - __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ - __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ - __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ - __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ - __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ - __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ - __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ - __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ - __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ - __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ - __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ - __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ - } GTCLR_b; + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; }; union { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ struct { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; }; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ struct { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; }; union { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ struct { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing - * Source Counter Clear Enable. */ - __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear - * Enable (This bit is only available in GPT324 to GPT329. - * In GPT320 to GPT323, this bit is read as 0. The write value - * should be 0.) */ - uint32_t : 3; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ union { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ - struct - { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ - uint32_t : 4; - } GTUPSR_b; - }; +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ - struct - { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ - uint32_t : 4; - } GTDNSR_b; - }; +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; union { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ struct { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; - } GTICASR_b; + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; union { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ struct { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; - } GTICBSR_b; + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; union { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ struct { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 7; - __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ - __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ - __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ - __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ - uint32_t : 2; - __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ - __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ - uint32_t : 3; - __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ - __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ - uint32_t : 3; - } GTCR_b; + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - } GTUDDTYC_b; + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; }; union { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ struct { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous - * Clear Disable.(This bit is only available in GPT324 to - * GPT329. In GPT320 to GPT323, this bit is read as 0. The - * write value should be 0.) */ - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This - * bit is only available in GPT324 to GPT329. In GPT320 to - * GPT323, this bit is read as 0. The write value should be - * 0.) */ - uint32_t : 1; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; }; + __IM uint32_t RESERVED8[3]; union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ struct { - uint32_t : 8; - __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous - * Clear Enable */ - __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source - * Synchronous Clear Enable */ - __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ - __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ - __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion - * Start Request Enable */ - __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D - * Conversion Start Request Enable */ - uint32_t : 4; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ - } GTINTAD_b; + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; union { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ struct { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ - } GTST_b; + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; }; + __IM uint16_t RESERVED11; union { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ struct { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 4; - __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 1; - __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ - uint32_t : 5; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; }; + __IM uint16_t RESERVED12; union { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ struct { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; }; union { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ struct { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ struct { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; union { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ struct { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[11]; union { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ struct { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; union { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ struct { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; union { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ struct { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; }; union { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ struct { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; }; union { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ struct { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; }; + __IM uint16_t RESERVED23; union { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ struct { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ struct { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; }; + __IM uint16_t RESERVED25; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - union - { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ - - struct - { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; - }; +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ - union - { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ +/** + * @brief Flash Memory Cache (R_FCACHE) + */ - struct - { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; - }; +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; union { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; }; + __IM uint16_t RESERVED2[11]; union { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; union { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ - union - { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; - }; +/** + * @brief General PWM Timer (R_GPT0) + */ +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ union { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ struct { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; }; union { - __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request - * Signal Monitoring Register */ + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ struct { - __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output - * Enabling */ - uint32_t : 7; - __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ - uint32_t : 6; - __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output - * Enabling */ - uint32_t : 7; - } GTADSMR_b; + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; }; union { - __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping - * Counter Control Register */ + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ struct { - __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ - uint32_t : 2; - __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ - uint32_t : 4; - __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ - __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source - * select */ - uint32_t : 2; - __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ - __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ - __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ - } GTEITC_b; - }; - - union - { - __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping - * Setting Register 1 */ - - struct - { - __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt - * Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ - uint32_t : 1; - } GTEITLI1_b; - }; - - union - { - __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping - * Setting Register 2 */ - - struct - { - __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 1; - __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended - * Skipping Function Select */ - uint32_t : 25; - } GTEITLI2_b; + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; }; union { - __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping - * Setting Register */ + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ struct { - __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 5; - __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping - * Function Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function - * Select */ - uint32_t : 1; - } GTEITLB_b; + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; }; union { - __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation - * Function Setting Register */ + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ struct { - __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ - uint32_t : 6; - __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ - uint32_t : 1; - __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ - uint32_t : 6; - } GTICLF_b; + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; }; union { - __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ struct { - __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ - uint32_t : 7; - __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ - uint32_t : 7; - __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ - uint32_t : 4; - } GTPC_b; + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; }; - __IM uint32_t RESERVED[4]; union { - __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous - * Control Channel Select Register */ + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ struct { - __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel - * Select */ - __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel - * Select */ - uint32_t : 22; - } GTSECSR_b; + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; }; union { - __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous - * Control Register */ + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ struct { - __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ - __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ - uint32_t : 4; - __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ - __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ - uint32_t : 4; - __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ - __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ - uint32_t : 6; - __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ - __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ - uint32_t : 6; - } GTSECR_b; + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; }; - __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ struct { - __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ - __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer - * Disable */ - uint32_t : 2; - __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer - * Enable */ - uint32_t : 1; - __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer - * Disable */ - __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer - * Transfer Disable */ - uint32_t : 2; - __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ - __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ - __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ - __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ - uint32_t : 2; - } GTBER2_b; + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; }; union { - __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ struct { - __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ - uint32_t : 11; - __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ - uint32_t : 11; - } GTOLBR_b; - }; - __IM uint32_t RESERVED2; - - union - { - __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input - * Capture Control Register */ - - struct - { - __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other - * Channel GTCCRA Input Capture Source Enable */ - __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture - * Source Enable */ - __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ - __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture - * to Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to - * Other Channel GTCCRb Input Capture Source Enable */ - __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to - * Other Channel GTCCRB Input Capture Source Enable */ - __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture - * Source Enable */ - __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input - * Capture Source Enable */ - __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input - * Capture Source Enable */ - uint32_t : 5; - __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ - } GTICCR_b; - }; -} R_GPT0_Type; /*!< Size = 240 (0xf0) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ - -typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ -{ - union - { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ - - struct - { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ -{ union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Interrupt Controller Unit (R_ICU) - */ -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ union { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ struct { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; }; - __IM uint32_t RESERVED[60]; union { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ struct { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; union { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ struct { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ - uint16_t : 1; - __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ - } NMIER_b; + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; union { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ struct { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ - uint16_t : 1; - __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ - } NMICLR_b; + uint32_t : 8; + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ struct { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ - uint16_t : 1; - __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ - } NMISR_b; + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ struct { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; }; union { - __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ struct { - __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ - __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable - * bit */ - __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable - * bit */ - uint32_t : 29; - } WUPEN1_b; + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; }; - __IM uint32_t RESERVED10[6]; union { - __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ struct { - __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit - * = 1) */ - __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when - * LPOPTEN bit = 1) */ - uint8_t : 6; - } IELEN_b; + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - __IM uint32_t RESERVED13[15]; union { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ struct { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; }; - __IM uint16_t RESERVED14; - __IM uint32_t RESERVED15[31]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; }; - __IM uint32_t RESERVED16[24]; union { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ struct { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ - -/* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I2C Bus Interface (R_IIC0) - */ -typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ -{ union { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ struct { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; }; union { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ struct { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; }; union { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ struct { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; }; union { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ struct { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; }; union { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ struct { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; }; union { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ struct { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; }; union { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ struct { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; }; union { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ struct { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; }; union { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ struct { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; }; union { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ struct { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ struct { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; }; union { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ struct { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; }; union { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ struct { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; }; union { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ struct { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ struct { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; }; union { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ -/* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Independent Watchdog Timer (R_IWDT) - */ - -typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ -{ union { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ struct { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ struct { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } IWDTCR_b; + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; }; union { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ struct { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; }; union { - __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ struct { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } IWDTRCR_b; + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; }; - __IM uint8_t RESERVED1; union { - __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ struct { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } IWDTCSTPR_b; + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_IWDT_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_I3C0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I3C Bus Interface (R_I3C0) - */ + __IM uint32_t RESERVED[4]; -typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ -{ union { - __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ struct { - __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ - uint32_t : 31; - } PRTS_b; + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ struct { - __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ - uint32_t : 31; - } CECTL_b; + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; }; + __IM uint32_t RESERVED1[2]; union { - __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ struct { - __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ - uint32_t : 6; - __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ - __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ - uint32_t : 20; - __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ - __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ - __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ - } BCTL_b; + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; }; union { - __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ struct { - uint32_t : 16; - __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ - uint32_t : 8; - __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ - } MSDVAD_b; + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; }; - __IM uint32_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ struct { - __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ - __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ - __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ - __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ - __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ - __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ - __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ - uint32_t : 9; - __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ - uint32_t : 15; - } RSTCTL_b; + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ union { - __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ struct { - uint32_t : 2; - __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ - uint32_t : 1; - __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ - uint32_t : 2; - __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ - uint32_t : 24; - } PRSST_b; + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; }; - __IM uint32_t RESERVED2[2]; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ union { - __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - uint32_t : 10; - __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ - uint32_t : 21; - } INST_b; + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; }; + __IM uint32_t RESERVED[15]; union { - __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ struct { - uint32_t : 10; - __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ - uint32_t : 21; - } INSTE_b; + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ struct { - uint32_t : 10; - __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ - uint32_t : 21; - } INIE_b; + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ union { - __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ struct { - uint32_t : 10; - __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ - uint32_t : 21; - } INSTFC_b; + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; }; - __IM uint32_t RESERVED3; + __IM uint32_t RESERVED[60]; union { - __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ struct { - uint32_t : 19; - __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ - uint32_t : 8; - } DVCT_b; + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; }; - __IM uint32_t RESERVED4[4]; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; union { - __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ struct { - __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ - __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ - uint32_t : 1; - __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ - uint32_t : 28; - } IBINCTL_b; + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; }; - __IM uint32_t RESERVED5; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; union { - __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ struct { - __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ - __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ - uint32_t : 5; - __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ - uint32_t : 3; - __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ - uint32_t : 1; - __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ - __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ - uint32_t : 16; - } BFCTL_b; + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; union { - __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ struct { - __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ - uint32_t : 4; - __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ - __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ - uint32_t : 8; - __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ - __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ - uint32_t : 15; - } SVCTL_b; - }; - __IM uint32_t RESERVED6[2]; - - union - { - __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ - - struct - { - __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ - uint32_t : 29; - } REFCKCTL_b; + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; union { - __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ struct { - __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ - __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ - __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ - uint32_t : 1; - __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ - } STDBR_b; + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; }; union { - __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ struct { - __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ - __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ - __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ - uint32_t : 2; - } EXTBR_b; + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; }; + __IM uint32_t RESERVED10[6]; union { - __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ struct { - __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ - uint32_t : 23; - } BFRECDT_b; + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; union { - __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ struct { - __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ - uint32_t : 23; - } BAVLCDT_b; + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; union { - __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ struct { - __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ - uint32_t : 14; - } BIDLCDT_b; + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; }; + __IM uint32_t RESERVED16[24]; union { - __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ struct { - __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ - __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ - __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ - uint32_t : 1; - __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ - uint32_t : 3; - __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ - uint32_t : 4; - __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ - uint32_t : 16; - } OUTCTL_b; + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ union { - __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ struct { - __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ - __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ - uint32_t : 27; - } INCTL_b; + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; }; union { - __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ struct { - __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ - uint32_t : 2; - __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ - __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ - __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ - uint32_t : 24; - } TMOCTL_b; + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; }; - __IM uint32_t RESERVED7; union { - __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ struct { - __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ - uint32_t : 3; - __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ - uint32_t : 1; - __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ - __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ - uint32_t : 24; - } WUCTL_b; + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; }; - __IM uint32_t RESERVED8; union { - __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ struct { - __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ - __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ - __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ - uint32_t : 29; - } ACKCTL_b; + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; }; union { - __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ struct { - __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ - __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ - uint32_t : 30; - } SCSTRCTL_b; + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; }; - __IM uint32_t RESERVED9[2]; union { - __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ struct { - __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ - uint32_t : 12; - __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ - __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ - __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ - __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ - } SCSTLCTL_b; + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; }; - __IM uint32_t RESERVED10[3]; union { - __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ struct { - uint32_t : 16; - __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ - } SVTDLG0_b; + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; }; - __IM uint32_t RESERVED11[31]; union { - __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ struct { - __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ - __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ - __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ - uint32_t : 29; - } CNDCTL_b; + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; }; - __IM uint32_t RESERVED12[3]; - __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ - __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ - __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ - __IM uint32_t RESERVED13[8]; - __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ - __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ - __IM uint32_t RESERVED14[3]; union { - __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ struct { - __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ - __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ - __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ - __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ - } NQTHCTL_b; + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; }; union { - __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control - * Register 0 */ + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ struct { - __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ - uint32_t : 5; - __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ - uint32_t : 5; - __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ - uint32_t : 5; - } NTBTHCTL0_b; + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; }; - __IM uint32_t RESERVED15[10]; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control - * Register */ + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ struct { - __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ - uint32_t : 24; - } NRQTHCTL_b; + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; }; - __IM uint32_t RESERVED16[3]; union { - __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ struct { - __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ - __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ - __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ - uint32_t : 1; - __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ - uint32_t : 3; - __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ - uint32_t : 7; - __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ - uint32_t : 3; - __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ - uint32_t : 11; - } BST_b; + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; }; union { - __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ struct { - __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ - __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ - __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ - uint32_t : 1; - __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ - uint32_t : 3; - __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ - uint32_t : 7; - __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ - uint32_t : 3; - __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ - uint32_t : 11; - } BSTE_b; + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; }; union { - __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ struct { - __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ - __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ - __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ - uint32_t : 7; - __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ - uint32_t : 11; - } BIE_b; + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; }; + __IM uint8_t RESERVED[2]; union { - __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ struct { - __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ - __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ - __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ - uint32_t : 1; - __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ - uint32_t : 3; - __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ - uint32_t : 7; - __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ - uint32_t : 3; - __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ - uint32_t : 11; - } BSTFC_b; + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; }; union { - __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ struct { - __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ - __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ - __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ - __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ - __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ - __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ - uint32_t : 3; - __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ - uint32_t : 10; - __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ - uint32_t : 11; - } NTST_b; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ union { - __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ struct { - __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ - __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ - __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ - __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ - __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ - __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ - uint32_t : 3; - __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ - uint32_t : 10; - __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ - uint32_t : 11; - } NTSTE_b; + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ struct { - __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ - __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ - __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ - __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ - __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ - __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ - uint32_t : 3; - __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ - uint32_t : 10; - __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ - uint32_t : 11; - } NTIE_b; + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; }; union { - __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ struct { - __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ - __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ - __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ - __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ - __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ - __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ - uint32_t : 3; - __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ - uint32_t : 10; - __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ - uint32_t : 11; - } NTSTFC_b; + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; }; - __IM uint32_t RESERVED17[8]; union { - __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ struct { - __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ - __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ - __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ - uint32_t : 29; - } BCST_b; + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; }; + __IM uint8_t RESERVED1; union { - __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ struct { - __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ - uint32_t : 4; - __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ - __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ - uint32_t : 8; - __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ - __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ - uint32_t : 15; - } SVST_b; + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ +typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ +{ union { - __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ struct { - __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ - uint32_t : 31; - } WUST_b; + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; }; - __IM uint32_t RESERVED18[2]; + __IM uint32_t RESERVED[3]; union { - __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS0_b; + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; }; - __IM uint32_t RESERVED19; union { - __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS1_b; + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; }; - __IM uint32_t RESERVED20; union { - __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS2_b; + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; }; - __IM uint32_t RESERVED21; + __IM uint32_t RESERVED1; union { - __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ struct { - __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ - uint32_t : 5; - __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ - __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ - __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ - __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ - __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ - __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ - } DATBAS3_b; + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; }; - __IM uint32_t RESERVED22[24]; union { - __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ struct { - __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ - uint32_t : 9; - __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ - uint32_t : 5; - __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ - __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ - } EXDATBAS_b; + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; }; - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS0_b; + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; }; union { - __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS1_b; + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; }; union { - __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ struct { - __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ - __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ - uint32_t : 1; - __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ - uint32_t : 3; - __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ - uint32_t : 9; - } SDATBAS2_b; + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; }; - __IM uint32_t RESERVED24[5]; union { - __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT0_b; + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT1_b; + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; }; + __IM uint32_t RESERVED4[4]; union { - __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } MSDCT2_b; + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ struct { - uint32_t : 8; - __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ uint32_t : 16; - } MSDCT3_b; + } BFCTL_b; }; - __IM uint32_t RESERVED25[16]; union { - __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ struct { - __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ - __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ - __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ - __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ - __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ - uint32_t : 2; - __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ - uint32_t : 16; - } SVDCT_b; + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; }; - __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional - * ID Low Register */ - __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional - * ID High Register */ - __IM uint32_t RESERVED26; + __IM uint32_t RESERVED6[2]; union { - __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ struct { - uint32_t : 16; - __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ - uint32_t : 1; - __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ - uint32_t : 2; - __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ - __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ - } SVDVAD0_b; + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; }; - __IM uint32_t RESERVED27[7]; union { - __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ struct { - __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ - __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ uint32_t : 1; - __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ - uint32_t : 28; - } CSECMD_b; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; }; union { - __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ struct { - __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ - uint32_t : 28; - } CEACTST_b; + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; }; union { - __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ struct { - __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ - uint32_t : 16; - } CMWLG_b; + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; }; union { - __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ struct { - __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ - __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ - uint32_t : 8; - } CMRLG_b; + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; }; union { - __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ struct { - __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ - uint32_t : 24; - } CETSTMD_b; + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; }; union { - __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ struct { - __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ uint32_t : 1; - __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ - __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ - __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ uint32_t : 16; - } CGDVST_b; + } OUTCTL_b; }; union { - __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ struct { - __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ - uint32_t : 29; - } CMDSPW_b; + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; }; union { - __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ struct { - __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ - __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ - uint32_t : 26; - } CMDSPR_b; + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ struct { - __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ - uint32_t : 7; - __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ - } CMDSPT_b; + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) - * Register */ + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ struct { - uint32_t : 8; - __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ - __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ - uint32_t : 8; - } CETSM_b; + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; }; - __IM uint32_t RESERVED28[2]; union { - __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ struct { - __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ - uint32_t : 2; - __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ - uint32_t : 24; - } BITCNT_b; + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; }; - __IM uint32_t RESERVED29[4]; + __IM uint32_t RESERVED9[2]; union { - __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ struct { - __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ - __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ - __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ - __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ - uint32_t : 3; - } NQSTLV_b; + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; }; + __IM uint32_t RESERVED10[3]; union { - __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ struct { - __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ - __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ uint32_t : 16; - } NDBSTLV0_b; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; }; - __IM uint32_t RESERVED30[9]; + __IM uint32_t RESERVED11[31]; union { - __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ struct { - __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ - uint32_t : 24; - } NRSQSTLV_b; + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; }; - __IM uint32_t RESERVED31[2]; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; union { - __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ struct { - __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ - __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ - __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ - __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ - uint32_t : 28; - } PRSTDBG_b; + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; }; union { - __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ struct { - __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ - uint32_t : 24; - } MSERRCNT_b; - }; -} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ -/** - * @brief System-Module Stop (R_MSTP) - */ + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; -typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ -{ union { - __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ struct { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRA_b; + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; }; union { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ struct { - __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRB_b; + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; }; union { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ struct { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRC_b; + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; }; union { - __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ struct { - __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRD_b; + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; }; union { - union + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct { - __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; - struct - { - __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ - __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ - __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ - __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ - __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ - __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ - __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ - __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ - __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ - __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ - __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for - * usage. */ - __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for - * usage. */ - } MSTPCRE_b; - }; + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ - union + struct { - __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - - struct - { - __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ - __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ - __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ - uint16_t : 4; - __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ - __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ - } LSMRWDIS_b; - }; + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; }; -} R_MSTP_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED23[3]; -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ -/** - * @brief I/O Ports (R_PORT0) - */ + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; -typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ -{ union { - union + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ struct { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; }; union { - union + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ struct { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; union { - union + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; - struct - { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; - }; + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ struct { - union - { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - - struct - { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; - }; + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; - union - { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ - struct - { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; - }; - }; + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; }; union { - union + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; - struct - { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; - }; + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ struct { - union - { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - - struct - { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; - }; + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; - union - { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ - struct - { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; - }; - }; + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ -/** - * @brief I/O Ports-PFS (R_PFS) - */ + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ -{ union { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ - __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; }; -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ -/** - * @brief I/O Ports-MISC (R_PMISC) - */ + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; -typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ -{ union { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ struct { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ struct { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; }; - __IM uint8_t RESERVED1; + __IM uint32_t RESERVED28[2]; union { - __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ struct { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPRS_b; + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; }; - __IM uint16_t RESERVED2[4]; - __IM uint8_t RESERVED3; + __IM uint32_t RESERVED29[4]; union { - __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ struct { - __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ - uint8_t : 6; - } PRWCNTR_b; + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; }; - __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ -} R_PMISC_Type; /*!< Size = 40 (0x28) */ -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ - -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ union { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ struct { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; }; + __IM uint32_t RESERVED30[9]; union { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ struct { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; }; + __IM uint32_t RESERVED31[2]; union { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ struct { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; }; union { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ struct { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ union { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ struct { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; - }; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ union { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ struct { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ struct { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; }; union { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ struct { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; }; union { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ struct { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; }; - __IM uint32_t RESERVED1; union { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ - - struct + union { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; - }; + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ - union - { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; - struct + union { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; - }; - __IM uint32_t RESERVED2[499]; - - union - { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ - struct - { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ +} R_MSTP_Type; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ -/* ================ R_RTC ================ */ +/* ================ R_PORT0 ================ */ /* =========================================================================================================================== */ /** - * @brief Realtime Clock (R_RTC) + * @brief I/O Ports (R_PORT0) */ -typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ { union { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; }; - __IM uint8_t RESERVED; union { union { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ struct { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; }; - union + struct { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - struct + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; }; }; - __IM uint8_t RESERVED1; union { union { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ struct { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; }; - union + struct { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ - struct + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; }; }; - __IM uint8_t RESERVED2; union { union { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ struct { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; }; - union + struct { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ - struct + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; }; }; - __IM uint8_t RESERVED3; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ union { - union - { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; - }; - __IM uint8_t RESERVED4; +/** + * @brief I/O Ports-MISC (R_PMISC) + */ +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ union { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; }; - __IM uint8_t RESERVED5; + __IM uint8_t RESERVED[2]; union { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; }; - __IM uint8_t RESERVED6; + __IM uint8_t RESERVED1; union { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; union { - union - { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ - union + struct { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; }; - __IM uint8_t RESERVED7; - - union - { - union - { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; - }; - __IM uint8_t RESERVED8; +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ union { - union - { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ - union + struct { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; }; - __IM uint8_t RESERVED9; union { - union - { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ - union + struct { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; }; - __IM uint8_t RESERVED10; union { - union - { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ - union + struct { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; }; - __IM uint8_t RESERVED11; union { - union - { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ - union + struct { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; }; - __IM uint8_t RESERVED12; union { - union - { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ - union + struct { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; }; union { - union + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ - union + struct { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; + __IM uint32_t RESERVED; union { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ struct { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; }; - __IM uint8_t RESERVED15; union { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ struct { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; union { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ struct { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; }; - __IM uint8_t RESERVED18; + __IM uint32_t RESERVED1; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; }; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; + __IM uint32_t RESERVED2[499]; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ /* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ +/* ================ R_RTC ================ */ /* =========================================================================================================================== */ /** - * @brief Serial Communications Interface (R_SCI0) + * @brief Realtime Clock (R_RTC) */ -typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ { + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + union { union { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; }; union { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ struct { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; - }; - - union - { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ - - struct - { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; }; + __IM uint8_t RESERVED1; union { union { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; }; union { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ struct { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; }; }; + __IM uint8_t RESERVED2; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ - - struct + union { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; - }; + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; - union - { union { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; }; + }; + __IM uint8_t RESERVED3; + union + { union { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ struct { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; }; union { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ struct { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; }; }; + __IM uint8_t RESERVED4; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct + union { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; - struct + union { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; }; + __IM uint8_t RESERVED7; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - struct + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; }; + __IM uint8_t RESERVED8; union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - struct + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; }; + __IM uint8_t RESERVED9; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - struct + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; }; + __IM uint8_t RESERVED10; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - struct + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; }; + __IM uint8_t RESERVED11; union { union { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ struct { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; }; union { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ struct { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; }; + }; + __IM uint8_t RESERVED12; - struct + union + { + union { - union + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - union + struct { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; }; }; @@ -11962,1602 +12001,1749 @@ typedef struct /*!< (@ 0x40118000) R_SCI0 Structure { union { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ struct { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; }; union { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ struct { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; + __IM uint8_t RESERVED18; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ struct { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; }; union { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - struct + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - struct + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; union { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; union { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - struct + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; - }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ -typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ - uint32_t : 22; - } SD_SIZE_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; - __IM uint32_t RESERVED1; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; + __IM uint32_t RESERVED; union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; }; - __IM uint32_t RESERVED5[2]; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[79]; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint32_t RESERVED4[3]; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; - __IM uint8_t RESERVED[3]; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; - __IM uint8_t RESERVED3[179]; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ - - struct - { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ - - struct - { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; + __IM uint8_t RESERVED[3]; union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED3[179]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; + __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED5[3]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -15410,7 +15596,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -17245,14 +17442,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -17266,7 +17463,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -19051,7 +19277,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -19088,7 +19313,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -19127,8 +19351,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) @@ -19179,7 +19402,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -19216,7 +19438,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -19396,17 +19617,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -19423,6 +19818,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -19838,62 +20235,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -20061,89 +20442,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -20935,10 +21233,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -21805,6 +22113,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -23156,30 +23471,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -24189,17 +24520,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -25458,121 +25788,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -26123,6 +26338,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -27245,12 +27463,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h index 8fa2520db..d1ae1eefa 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h @@ -135,16 +135,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -360,9 +358,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -386,7 +383,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -396,29 +393,597 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; } STAT_b; }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { @@ -446,8 +1011,9 @@ typedef struct struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ uint16_t : 10; } CNT_b; }; @@ -616,7 +1182,7 @@ typedef struct { union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { @@ -624,34 +1190,34 @@ typedef struct __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ uint16_t : 13; - } C_b; + } AC_b; }; __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ } S_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ } E_b; }; __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ /** * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) @@ -2588,16 +3154,77 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -3478,7 +4105,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -5819,46 +6461,81 @@ typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -6355,10 +7032,10 @@ typedef struct /*!< (@ 0x40053000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -10265,7 +10942,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -11043,17 +11731,191 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -11070,6 +11932,8 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ MB ================ */ @@ -11146,19 +12010,19 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ /* =========================================================================================================================== */ /* ================ MMPU ================ */ @@ -11944,10 +12808,20 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -12501,6 +13375,13 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -13577,30 +14458,46 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -15326,6 +16223,9 @@ typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h index 1e904b693..b60578487 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,2699 +400,3094 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - uint32_t : 3; - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - uint32_t : 4; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - uint32_t : 1; - } FDCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; + __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint32_t RESERVED[3]; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + __IM uint32_t RESERVED5; -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - uint32_t : 3; - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 23; - } P1_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED9; -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ union { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 6; - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct + union { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; - struct + union { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct + union { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; - struct + union { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; -} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ /** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct + union { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; - struct + union { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; -} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; -} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED[104]; -} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..29]) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ typedef struct { union { - __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ - - struct - { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } A_b; - }; - - union - { - __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } B_b; + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; }; -} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) - */ -typedef struct -{ union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; }; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers) + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) */ typedef struct { - __OM uint32_t INP; /*!< (@ 0x00000000) Channel Input Register */ - __IM uint32_t OUT; /*!< (@ 0x00000004) Channel Output Register */ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; union { - __IOM uint32_t CNT; /*!< (@ 0x00000008) Channel Control Register */ + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ struct { - __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit */ - } CNT_b; + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; }; union { - __IOM uint8_t INT; /*!< (@ 0x0000000C) Channel Interrupt Enable Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ struct { - uint8_t : 1; - __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit */ - __IOM uint8_t ORDYIE : 1; /*!< [2..2] Output data preparation completion interrupt enable bit */ - __IOM uint8_t CERRIE : 1; /*!< [3..3] Operation error interrupt enable bit */ - uint8_t : 4; - } INT_b; + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; }; union { - __IM uint8_t STS; /*!< (@ 0x0000000D) Channel Status Register */ + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ struct { - __IM uint8_t CPRCS : 1; /*!< [0..0] Channel processing status flag */ - __IM uint8_t CPRCFF : 1; /*!< [1..1] Channel processing completion flag */ - __IM uint8_t ORDYF : 1; /*!< [2..2] Output data preparation completion flag */ - __IM uint8_t CERRF : 1; /*!< [3..3] Operation error flag */ - uint8_t : 4; - } STS_b; + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; }; union { - __OM uint8_t FCLR; /*!< (@ 0x0000000E) Channel Flag Clear Register */ + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ struct { - uint8_t : 1; - __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit */ - uint8_t : 1; - __OM uint8_t CERRFCLR : 1; /*!< [3..3] Operation error flag clear bit */ - uint8_t : 4; - } FCLR_b; + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; }; - __IM uint8_t RESERVED; -} R_IIRFA_IIRCH_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ /** - * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers) + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) */ typedef struct { - __IOM uint32_t B0; /*!< (@ 0x00000000) Stage Coefficient b0 Register */ - __IOM uint32_t B1; /*!< (@ 0x00000004) Stage Coefficient b1 Register */ - __IOM uint32_t B2; /*!< (@ 0x00000008) Stage Coefficient b2 Register */ - __IOM uint32_t A1; /*!< (@ 0x0000000C) Stage Coefficient a1 Register */ - __IOM uint32_t A2; /*!< (@ 0x00000010) Stage Coefficient a2 Register */ - __IOM uint32_t D0; /*!< (@ 0x00000014) Stage Delay Data D0 Register */ - __IOM uint32_t D1; /*!< (@ 0x00000018) Stage Delay Data D1 Register */ - __IM uint32_t RESERVED; -} R_IIRFA_IIRSTG_Type; /*!< Size = 32 (0x20) */ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; }; - __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ /** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) */ typedef struct { union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ union { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - uint32_t : 1; - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ - union + struct { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - uint16_t : 1; - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ - union + struct { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - uint8_t : 1; - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) */ typedef struct { - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ - __IM uint16_t RESERVED; -} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ -/** - * @brief R_BUS_B_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) - */ -typedef struct -{ union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; }; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ /** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) */ typedef struct { union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..29]) + */ +typedef struct +{ union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) */ typedef struct { union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers) + */ +typedef struct +{ + __OM uint32_t INP; /*!< (@ 0x00000000) Channel Input Register */ + __IM uint32_t OUT; /*!< (@ 0x00000004) Channel Output Register */ union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Channel Control Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit */ + } CNT_b; }; union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + __IOM uint8_t INT; /*!< (@ 0x0000000C) Channel Interrupt Enable Register */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + uint8_t : 1; + __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit */ + __IOM uint8_t ORDYIE : 1; /*!< [2..2] Output data preparation completion interrupt enable bit */ + __IOM uint8_t CERRIE : 1; /*!< [3..3] Operation error interrupt enable bit */ + uint8_t : 4; + } INT_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + __IM uint8_t STS; /*!< (@ 0x0000000D) Channel Status Register */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IM uint8_t CPRCS : 1; /*!< [0..0] Channel processing status flag */ + __IM uint8_t CPRCFF : 1; /*!< [1..1] Channel processing completion flag */ + __IM uint8_t ORDYF : 1; /*!< [2..2] Output data preparation completion flag */ + __IM uint8_t CERRF : 1; /*!< [3..3] Operation error flag */ + uint8_t : 4; + } STS_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + __OM uint8_t FCLR; /*!< (@ 0x0000000E) Channel Flag Clear Register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + uint8_t : 1; + __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit */ + uint8_t : 1; + __OM uint8_t CERRFCLR : 1; /*!< [3..3] Operation error flag clear bit */ + uint8_t : 4; + } FCLR_b; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + __IM uint8_t RESERVED; +} R_IIRFA_IIRCH_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers) + */ +typedef struct +{ + __IOM uint32_t B0; /*!< (@ 0x00000000) Stage Coefficient b0 Register */ + __IOM uint32_t B1; /*!< (@ 0x00000004) Stage Coefficient b1 Register */ + __IOM uint32_t B2; /*!< (@ 0x00000008) Stage Coefficient b2 Register */ + __IOM uint32_t A1; /*!< (@ 0x0000000C) Stage Coefficient a1 Register */ + __IOM uint32_t A2; /*!< (@ 0x00000010) Stage Coefficient a2 Register */ + __IOM uint32_t D0; /*!< (@ 0x00000014) Stage Delay Data D0 Register */ + __IOM uint32_t D1; /*!< (@ 0x00000018) Stage Delay Data D1 Register */ + __IM uint32_t RESERVED; +} R_IIRFA_IIRSTG_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) */ typedef struct { union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) */ typedef struct { union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ + __IM uint16_t RESERVED2; -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ACMPHS0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief High-Speed Analog Comparator (R_ACMPHS0) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ - -typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +typedef struct { union { - __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ - __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ - __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ - __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ - __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ - __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ - } CMPCTL_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; - __IM uint8_t RESERVED[3]; + __IM uint16_t RESERVED; union { - __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ - uint8_t : 4; - } CMPSEL0_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; - __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ - uint8_t : 2; - } CMPSEL1_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; - __IM uint8_t RESERVED2[3]; union { - __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ - uint8_t : 7; - } CMPMON_b; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; - __IM uint8_t RESERVED3[3]; union { - __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ - uint8_t : 6; - __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ - } CPIOC_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct { union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ struct { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - union + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; +/** @} */ /* End of group Device_Peripheral_clusters */ - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +{ union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; }; + __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; }; + __IM uint8_t RESERVED2[3]; union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; }; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - struct + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; - __IM uint8_t RESERVED7; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; - __IM uint8_t RESERVED11; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; + __IM uint8_t RESERVED5; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED10; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; - __IM uint8_t RESERVED14; + __IM uint8_t RESERVED11; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint8_t RESERVED21; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; __IM uint32_t RESERVED22[41]; union @@ -3485,30 +3877,91 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { @@ -4533,7 +4986,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6843,46 +7311,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7379,10 +7882,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -8810,37 +9313,46 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9688,1318 +10200,992 @@ typedef struct /*!< (@ 0x40118000) R_SCI0 Structure __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct + union { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ uint8_t : 2; - } SPPCR_b; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ uint8_t : 3; - } SPCR3_b; + } PCR_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; - __IM uint8_t RESERVED[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; - __IM uint8_t RESERVED3[179]; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS_B) - */ + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED13; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; + __IM uint8_t RESERVED[3]; union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED3[179]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; + __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED5[3]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ @@ -12650,7 +12836,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -13416,14 +13613,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -13437,7 +13634,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -19304,7 +19530,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x4001F000UL @@ -19337,7 +19562,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TSN_CAL_BASE 0x407FB17CUL #define R_TSN_CTRL_BASE 0x400F3000UL @@ -19387,8 +19611,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) @@ -19442,7 +19665,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -19475,7 +19697,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) @@ -19660,17 +19881,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -19687,6 +20082,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -20130,62 +20527,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -20281,89 +20662,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= PMSAR ========================================================= */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ CTRL ================ */ /* =========================================================================================================================== */ @@ -21161,10 +21459,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -21615,6 +21923,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -22692,30 +23007,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -23815,17 +24146,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -24573,121 +24903,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -25121,6 +25336,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -25690,12 +25908,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h index 80b68273a..a581aa01a 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T3BB.h @@ -142,16 +142,14 @@ typedef struct struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; } WCR1_b; }; @@ -367,9 +365,8 @@ typedef struct struct { - __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register - * set command is issued. */ - uint16_t : 1; + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; } SDMOD_b; }; __IM uint16_t RESERVED12; @@ -393,7 +390,7 @@ typedef struct } R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ /** - * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) */ typedef struct { @@ -403,2663 +400,3058 @@ typedef struct struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ } ADD_b; }; union { - __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ - struct + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union { - __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 6; - __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ - } STAT_b; + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; }; __IM uint8_t RESERVED; __IM uint16_t RESERVED1; __IM uint32_t RESERVED2[2]; -} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ struct { - uint16_t : 15; - __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ - } CNT_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) - */ -typedef struct -{ union { - __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ struct { - uint16_t : 4; - __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ - uint16_t : 10; - } CNT_b; + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; }; - __IM uint16_t RESERVED; -} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) */ typedef struct { union { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ struct { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; }; + __IM uint8_t RESERVED[7]; union { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ struct { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - uint32_t : 3; - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; union { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ struct { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; }; + __IM uint8_t RESERVED1[7]; union { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ struct { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; }; -} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ /** - * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) */ typedef struct { + __IM uint32_t RESERVED[2]; + union { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - uint32_t : 4; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - uint32_t : 1; - } FDCFG_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; }; + __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; }; - __IM uint32_t RESERVED[3]; -} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + __IM uint32_t RESERVED5; -/** - * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) - */ -typedef struct -{ union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - uint32_t : 3; - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ - struct + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union { - __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 23; - } P1_b; + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + __IM uint32_t RESERVED9; -/** - * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) - */ -typedef struct -{ union { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ struct { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 6; - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ - - struct + union { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; - }; -} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ -/** - * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; - struct + union { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; }; + __IM uint32_t RESERVED11; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - - struct + union { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; - }; + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; - struct + union { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; }; + __IM uint32_t RESERVED12; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ struct { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; }; -} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ /** - * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ - - struct + union { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; - }; + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; - struct + union { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; }; + __IM uint32_t RESERVED[5]; union { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ struct { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ struct { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; }; -} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ /** - * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ - - struct - { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct - { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ struct { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; }; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ struct { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; }; -} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) */ typedef struct { union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ struct { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; }; + __IM uint16_t RESERVED; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ struct { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; }; + __IM uint16_t RESERVED1[5]; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ struct { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; }; + __IM uint16_t RESERVED2; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ struct { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; }; -} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ /** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) */ typedef struct { - __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED[104]; -} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ /** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) */ typedef struct { union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) */ typedef struct { union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; }; __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ typedef struct { union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ - - struct - { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; - }; - - union - { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ struct { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ -/** - * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) - */ -typedef struct -{ union { - __IOM uint16_t C; /*!< (@ 0x00000000) Access Control Register */ + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ - __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ - __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ - uint16_t : 13; - } C_b; + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ struct { - __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE: - * The low-order 2 bits are fixed to 0. */ - } S_b; + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; }; union { - __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ struct { - __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region - * end, for use in region determination.NOTE: The low-order - * 2 bits are fixed to 1. */ - } E_b; + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; }; - __IM uint32_t RESERVED1; -} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) */ typedef struct { union { - __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } CTL_b; + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[63]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; }; - __IM uint32_t RESERVED3[63]; - __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ -} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ -/** - * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) - */ -typedef struct -{ union { - __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ struct { - uint16_t : 2; - __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ - __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ - __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ - __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ - __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ - __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ - uint16_t : 4; - __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ - __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit - * is read as 1. The write value should be 1.) */ - __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ - __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ - } R_b; + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; }; - __IM uint16_t RESERVED; -} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ /** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) */ typedef struct { union { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ struct { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; }; union { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ struct { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; }; union { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ union { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ struct { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ /** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) */ typedef struct { union { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ struct { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ -/** - * @brief R_PFS_VLSEL [VLSEL] (VLSEL) - */ -typedef struct -{ - __IM uint8_t RESERVED[389]; + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; union { - __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ struct { - __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ - uint8_t : 7; - } VL1SEL_b; + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; }; -} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ -} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_RTC_RTCCR [RTCCR] (AGTIO I/O direction control register) + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) */ typedef struct { union { - __IOM uint8_t RTCCR; /*!< (@ 0x00000000) AGTIO I/O direction control register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ struct { - uint8_t : 7; - __IOM uint8_t TCEN : 1; /*!< [7..7] Select AGTIO I/O direction as input */ - } RTCCR_b; + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; }; - __IM uint8_t RESERVED; -} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_BUS_B_CSa [CSa] (CS Registers) - */ -typedef struct -{ - __IM uint16_t RESERVED; union { - __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ struct { - __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ - uint16_t : 2; - __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ - uint16_t : 4; - __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ - __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ - uint16_t : 5; - __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ - } MOD_b; + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ struct { - __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value - * is valid only when the PWENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value - * is valid only when the PRENB bit in CSnMOD is set to 1. */ - uint32_t : 5; - __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ - uint32_t : 3; - __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ - uint32_t : 3; - } WCR1_b; + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ struct { - __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ - uint32_t : 1; - __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ - uint32_t : 2; - __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ - uint32_t : 1; - __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ - uint32_t : 1; - __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ - uint32_t : 1; - } WCR2_b; + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; }; - __IM uint32_t RESERVED1; -} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_BUS_B_CSb [CSb] (CS Registers) + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) */ typedef struct { - __IM uint16_t RESERVED; - union { - __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ struct { - __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ - uint16_t : 3; - __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ - uint16_t : 2; - __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ - uint16_t : 3; - __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ - uint16_t : 3; - } CR_b; + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; }; - __IM uint16_t RESERVED1[3]; union { - __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ struct { - __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ - uint16_t : 4; - __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ - uint16_t : 4; - } REC_b; + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint16_t RESERVED2[2]; -} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) - */ -typedef struct -{ union { - __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ struct { - __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores - * an error address. */ - } ADD_b; + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; }; union { - __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ struct { - __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ - uint8_t : 7; - } ERRRW_b; + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) */ typedef struct { union { - __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ struct { - __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, - * It stores an error address. */ - } TZFADD_b; + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; }; union { - __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the - * time of the error */ - uint8_t : 7; - } TZFERRRW_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[2]; -} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ -/** - * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) - */ -typedef struct -{ union { - __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ struct { - uint16_t : 8; - __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ - __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ - uint16_t : 6; - } E_b; + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ - } N_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; -} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) */ typedef struct { union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ union { - __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_ALT_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ struct { - __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ - uint8_t : 2; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; }; -} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + __IM uint16_t RESERVED; -/** - * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) - */ -typedef struct -{ union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; }; + __IM uint16_t RESERVED1; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; }; + __IM uint16_t RESERVED2; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; }; - __IM uint16_t RESERVED; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ -} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ /** - * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, the 16-bit - * counter is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; - __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ -} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ -/* =========================================================================================================================== */ -/* ================ R_ACMPHS0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ -/** - * @brief High-Speed Analog Comparator (R_ACMPHS0) - */ + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; -typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ -{ union { - __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ - __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ - __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ - __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ - __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ - __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ - } CMPCTL_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; - __IM uint8_t RESERVED[3]; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ - uint8_t : 4; - } CMPSEL0_b; + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; - __IM uint8_t RESERVED1[3]; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; union { - __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ - uint8_t : 2; - } CMPSEL1_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; - __IM uint8_t RESERVED2[3]; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_RTC_RTCCR [RTCCR] (AGTIO I/O direction control register) + */ +typedef struct +{ union { - __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) AGTIO I/O direction control register */ struct { - __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ - uint8_t : 7; - } CMPMON_b; + uint8_t : 7; + __IOM uint8_t TCEN : 1; /*!< [7..7] Select AGTIO I/O direction as input */ + } RTCCR_b; }; - __IM uint8_t RESERVED3[3]; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ union { - __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ struct { - __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ - uint8_t : 6; - __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ - } CPIOC_b; + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ /** - * @brief A/D Converter (R_ADC0) + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +typedef struct { union { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ struct { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ struct { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ struct { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; union { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ struct { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; }; union { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ struct { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ struct { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ struct { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ struct { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ union { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ union { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ struct { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - union + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; +/** @} */ /* End of group Device_Peripheral_clusters */ - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +{ union { - __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ struct { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[29]; + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; - __IM uint16_t RESERVED3; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ struct { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; }; + __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ struct { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; }; + __IM uint8_t RESERVED2[3]; union { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ struct { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; }; + __IM uint8_t RESERVED3[3]; union { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ struct { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ union { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; + __IM uint8_t RESERVED; union { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; }; union { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ struct { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; - __IM uint16_t RESERVED4; union { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + union { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ struct { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; union { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; - __IM uint8_t RESERVED5; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - struct + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; }; union { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; union { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; - __IM uint8_t RESERVED6; union { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; - __IM uint8_t RESERVED7; union { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; union { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; union { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ struct { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; union { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ struct { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; - __IM uint8_t RESERVED10; union { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; - __IM uint8_t RESERVED11; union { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; - __IM uint8_t RESERVED12; - __IM uint16_t RESERVED13; union { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED6; union { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED7; union { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; union { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; union { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; union { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; union { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED10; union { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; + __IM uint8_t RESERVED11; union { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; - __IM uint8_t RESERVED14; union { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[2]; - __IM uint8_t RESERVED17; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; union @@ -3462,43 +3854,104 @@ typedef struct /*!< (@ 0x40003000) R_BUS Structure __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ } CSRECEN_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ - - struct - { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ }; + __IM uint32_t RESERVED4[58]; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ - - struct + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct { __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ @@ -4510,7 +4963,22 @@ typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ } DBGSTOPCR_b; }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -6803,46 +7271,81 @@ typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure * @brief Port Output Enable for GPT (R_GPT_POEG0) */ -typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ { union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ } POEGG_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -7339,10 +7842,10 @@ typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; } ICWUR2_b; }; } R_IIC0_Type; /*!< Size = 24 (0x18) */ @@ -8568,37 +9071,46 @@ typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure * @brief Bus Master MPU (R_MPU_MMPU) */ -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ { - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; - }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -9509,1320 +10021,994 @@ typedef struct /*!< (@ 0x40118000) R_SCI0 Structure __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; - }; - - union - { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ - - struct - { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; - }; - - union - { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ - - struct - { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; - }; - - union - { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ - - struct - { - __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in - * asynchronous mode). */ - __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous - * mode). */ - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; - }; - - union - { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ - - struct - { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; - }; - - union - { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ - - struct - { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; - }; - - union - { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ - - struct - { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; - }; - - union - { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ - - struct - { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; - }; - - union - { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ - - struct - { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; - }; - - union - { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ - - struct - { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; - }; - - union - { - union - { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; - - union - { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; - - struct - { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ - - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; - - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ - - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; - }; - - union - { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; - - union - { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ - - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; - - struct - { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; - - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ - - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; - }; - - union - { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ - - struct - { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; - }; - - union - { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ - - struct - { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; - }; - - union - { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ - - struct - { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; - }; - - union - { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ - - struct - { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; - }; - - union - { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ - - struct - { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; - }; - - union - { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ - - struct - { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; - }; - - union - { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ - - struct - { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 1; - __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ - __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ - __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ - __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ - } SPTR_b; - }; - - union - { - __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ - - struct - { - __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ - __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ - __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ - __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ - } ACTR_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ - - struct - { - __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ - uint8_t : 7; - } ESMER_b; + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; }; union { - __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - uint8_t : 1; - __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ - __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ - __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ - uint8_t : 4; - } CR0_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ - __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ - __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ - __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ - __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ - } CR1_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ - uint8_t : 1; - __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ - __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ - } CR2_b; + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ - uint8_t : 7; - } CR3_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ - __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ - uint8_t : 2; - __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ - uint8_t : 3; - } PCR_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ - __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ - __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ - __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ - __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ - __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ - uint8_t : 2; - } ICR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ - __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ - __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ - __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ - __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ - __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ - uint8_t : 2; - } STR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; union { - __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ - __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ - __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ - __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ - __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ - __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ - uint8_t : 2; - } STCR_b; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; - __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ struct { - __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ - __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ - } CF0CR_b; + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; - __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ - __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ - __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ - struct + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union { - __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ - __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ - __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ - __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ - __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ - __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ - __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ - __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ - } CF1CR_b; - }; - __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; struct { - __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ - uint8_t : 7; - } TCR_b; + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; }; union { - __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ - - struct + union { - __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ - uint8_t : 1; - __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ - __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ - uint8_t : 1; - } TMR_b; - }; - __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ - __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ -} R_SCI0_Type; /*!< Size = 52 (0x34) */ + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ -typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ -{ - union - { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; }; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ - __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ - __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ - __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ - } SSLP_b; + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ uint8_t : 2; - } SPPCR_b; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; - }; - - union - { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; }; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; }; union { - __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ struct { - __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ - uint8_t : 1; - __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ - uint8_t : 1; - } SPSSR_b; + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; }; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ - } SPCR2_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ uint8_t : 3; - } SPCR3_b; + } PCR_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; - __IM uint8_t RESERVED[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; - __IM uint8_t RESERVED3[179]; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; }; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; }; - __IM uint8_t RESERVED4[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; - __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; }; - __IM uint8_t RESERVED6[3]; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ -/** - * @brief Bus Interface (R_BUS_B) - */ + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ -typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ -{ - __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[543]; union { - __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFHBIU_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; - __IM uint16_t RESERVED3; union { - __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTFLBIU_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[2]; union { - __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTS0BIU_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; union { - __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPSBIU_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[3]; union { - __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPLBIU_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ - uint16_t : 15; - } BUSSCNTPHBIU_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[2]; union { - __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEQBIU_b; + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; }; - __IM uint16_t RESERVED13; union { - __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTEOBIU_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; - __IM uint16_t RESERVED14; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ - uint16_t : 14; - } BUSSCNTECBIU_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[429]; - __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ - __IM uint32_t RESERVED17[48]; - __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ - __IM uint32_t RESERVED18[48]; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS1ERRSTAT_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; - __IM uint32_t RESERVED21; + __IM uint8_t RESERVED[3]; union { - __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS1ERRCLR_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; union { - __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS2ERRSTAT_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; - __IM uint8_t RESERVED25; - __IM uint16_t RESERVED26; - __IM uint32_t RESERVED27; + __IM uint8_t RESERVED3[179]; union { - __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS2ERRCLR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint8_t RESERVED28; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30; union { - __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS3ERRSTAT_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED31; - __IM uint16_t RESERVED32; union { - __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ - uint8_t : 7; - } DMACDTCERRSTAT_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED33; - __IM uint16_t RESERVED34; union { - __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS3ERRCLR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED35; - __IM uint16_t RESERVED36; union { - __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ - uint8_t : 7; - } DMACDTCERRCLR_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint8_t RESERVED37; - __IM uint16_t RESERVED38; + __IM uint8_t RESERVED4[11]; union { - __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ - __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ - uint8_t : 1; - __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ - __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ - uint8_t : 3; - } BUS4ERRSTAT_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; - __IM uint8_t RESERVED39; - __IM uint16_t RESERVED40; - __IM uint32_t RESERVED41; + __IM uint8_t RESERVED5[3]; union { - __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ - __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ - uint8_t : 1; - __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ - __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ - uint8_t : 3; - } BUS4ERRCLR_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; - __IM uint8_t RESERVED42; - __IM uint16_t RESERVED43; -} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ @@ -12473,7 +12659,18 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED52; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED52; __IM uint32_t RESERVED53[3]; union @@ -14360,14 +14557,14 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure union { - __IOM uint32_t DMASARA; /*!< (@ 0x000001A0) ICU Security Attribution Register C */ + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ struct { - __IOM uint32_t DMASARAn : 8; /*!< [7..0] Security attributes of output and registers for DMAC - * channel */ + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ uint32_t : 24; - } DMASARA_b; + } DMACCHSAR_b; }; __IM uint32_t RESERVED7[3]; @@ -14381,7 +14578,36 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure uint32_t : 31; } CPUDSAR_b; }; - __IM uint32_t RESERVED8[275]; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; union { @@ -14572,7 +14798,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0_BASE 0x4011F000UL #define R_I3C1_BASE 0x4011F400UL #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL #define R_MPU_SPMON_BASE 0x40000D00UL #define R_MSTP_BASE 0x40084000UL #define R_PORT0_BASE 0x40080000UL @@ -14606,7 +14831,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL - #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TRNG_BASE 0x40162000UL #define R_TSN_CAL_BASE 0x407FB17CUL @@ -14648,8 +14872,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) - -/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) @@ -14699,7 +14922,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) @@ -14733,7 +14955,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TRNG ((R_TRNG_Type *) R_TRNG_BASE) #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) @@ -14910,17 +15131,191 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ -/* ================ BUSERR ================ */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ /* =========================================================================================================================== */ /* ========================================================== ADD ========================================================== */ - #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + /* ========================================================= STAT ========================================================== */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ - #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ - #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ BUSM ================ */ @@ -14937,6 +15332,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== CNT ========================================================== */ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ CFDC ================ */ @@ -15326,62 +15723,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ REGION ================ */ /* =========================================================================================================================== */ -/* =========================================================== C =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos (2UL) /*!< WP (Bit 2) */ - #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos (1UL) /*!< RP (Bit 1) */ - #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* =========================================================== S =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos (0UL) /*!< MMPUSmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ /* =========================================================== E =========================================================== */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos (0UL) /*!< MMPUEmn (Bit 0) */ - #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff) */ - -/* =========================================================================================================================== */ -/* ================ MMPU ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CTL ========================================================== */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ - #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ - #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================== PT =========================================================== */ - #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ - #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ SMPU ================ */ -/* =========================================================================================================================== */ - -/* =========================================================== R =========================================================== */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ - #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ - #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ - #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ - #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ - #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ - #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ - #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ - #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ - #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ - #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SP ================ */ @@ -15499,89 +15880,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ -/* =========================================================================================================================== */ -/* ================ CSa ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MOD ========================================================== */ - #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ - #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ - #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ - #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ - #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ - #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ -/* ========================================================= WCR1 ========================================================== */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ - #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ - #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ - #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ - #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ -/* ========================================================= WCR2 ========================================================== */ - #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ - #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ - #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ - #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ - #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ - #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ - #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ - #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ - #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ - -/* =========================================================================================================================== */ -/* ================ CSb ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CR =========================================================== */ - #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ - #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ - #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ - #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ - #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ - #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ -/* ========================================================== REC ========================================================== */ - #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ - #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ - #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ - #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ BUSERR ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ADD ========================================================== */ - #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ - #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ERRRW ========================================================= */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ - #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ BUSTZFERR ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== TZFADD ========================================================= */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TZFERRRW ======================================================== */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ - #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -16392,10 +16690,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_CAC ================ */ @@ -16846,6 +17154,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ @@ -17903,30 +18218,46 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* =========================================================================================================================== */ /* ========================================================= POEGG ========================================================= */ - #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ - #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ - #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ - #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ - #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ - #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ - #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ - #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ - #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ - #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ - #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ - #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ - #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ - #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ - #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ICU ================ */ @@ -18936,17 +19267,16 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ R_MPU_MMPU ================ */ /* =========================================================================================================================== */ -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== SMPUCTL ======================================================== */ - #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ - #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ - #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_MPU_SPMON ================ */ @@ -19713,121 +20043,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ -/* =========================================================================================================================== */ -/* ================ R_BUS_B ================ */ -/* =========================================================================================================================== */ - -/* ===================================================== BUSSCNTFHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTFLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTS0BIU ====================================================== */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTPSBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPLBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTPHBIU ====================================================== */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ -/* ===================================================== BUSSCNTEQBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTEOBIU ====================================================== */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ===================================================== BUSSCNTECBIU ====================================================== */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ - #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ -/* ====================================================== BUS1ERRSTAT ====================================================== */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRSTAT ====================================================== */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRSTAT ====================================================== */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRSTAT ====================================================== */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ - #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ - #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ - #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ - #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS1ERRCLR ======================================================= */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS2ERRCLR ======================================================= */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS3ERRCLR ======================================================= */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ====================================================== BUS4ERRCLR ======================================================= */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ - #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ - #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ - #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ - #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ -/* ==================================================== DMACDTCERRSTAT ===================================================== */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ - #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ -/* ===================================================== DMACDTCERRCLR ===================================================== */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ - #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ -/* ======================================================== CSRECEN ======================================================== */ - #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ - #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ - #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ - #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -20261,6 +20476,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================= SOMCR ========================================================= */ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ /* ======================================================== LOCOCR ========================================================= */ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ @@ -21401,12 +21619,18 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= MMPUSARB ======================================================== */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ -/* ======================================================== DMASARA ======================================================== */ - #define R_CPSCU_DMASARA_DMASARAn_Pos (0UL) /*!< DMASARAn (Bit 0) */ - #define R_CPSCU_DMASARA_DMASARAn_Msk (0xffUL) /*!< DMASARAn (Bitfield-Mask: 0xff) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ /* ======================================================== CPUDSAR ======================================================== */ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ /* ======================================================== TEVTRCR ======================================================== */ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h new file mode 100644 index 000000000..08fa1c47d --- /dev/null +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h @@ -0,0 +1,32676 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file ./out/R7FA8M1AH.h + * @brief CMSIS HeaderFile + * @version 1.2 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA8M1AH + * @{ + */ + +#ifndef R7FA8M1AH_H + #define R7FA8M1AH_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */ + #define __CM85_REV 0x0000U /*!< CM85 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 1 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + #define __PMU_PRESENT 0 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 0 /*!< PMU Event Counters */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */ + #include "system.h" /*!< R7FA8M1AH System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits) + */ +typedef struct +{ + union + { + __IM uint32_t CFGD_L; /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word */ + + struct + { + __IM uint32_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK16 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK17 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK18 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK19 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK20 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK21 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK22 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK23 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK24 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK25 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK26 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK27 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK28 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK29 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK30 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK31 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_L_b; + }; + + union + { + __IM uint32_t CFGD_H; /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word */ + + struct + { + __IM uint32_t CDLK32 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK33 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK34 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK35 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK36 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK37 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK38 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK39 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK40 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK41 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK42 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK43 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK44 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK45 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK46 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK47 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK48 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK49 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK50 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK51 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK52 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK53 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK54 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK55 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK56 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK57 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK58 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK59 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK60 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK61 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK62 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK63 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_H_b; + }; +} R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits) + */ +typedef struct +{ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits */ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits */ + + union + { + __IM uint16_t CFGD2; /*!< (@ 0x00000010) Configuration Data 2 Lock Bit */ + + struct + { + __IM uint16_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint16_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint16_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint16_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint16_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint16_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint16_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint16_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint16_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint16_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint16_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint16_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint16_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint16_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint16_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint16_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + } CFGD2_b; + }; + __IM uint16_t RESERVED; +} R_OFS_DATAFLASH_CFGDLOCK_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40332000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 4; + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution */ + uint32_t : 3; + __IOM uint32_t PSARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution */ + uint32_t : 2; + __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution */ + uint32_t : 4; + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security + * Attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution */ + uint32_t : 5; + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security + * Attribution */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security + * Attribution */ + uint32_t : 2; + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution */ + uint32_t : 1; + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution */ + uint32_t : 9; + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security + * Attribution */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security + * Attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + uint32_t : 4; + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution */ + uint32_t : 5; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution */ + uint32_t : 3; + __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution */ + uint32_t : 4; + __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARE1 : 1; /*!< [1..1] WDT0 Security Attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Real Time Clock Security Attribution */ + uint32_t : 4; + __IOM uint32_t PSARE8 : 1; /*!< [8..8] ULPT1 Security Attribution */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] ULPT0 Security Attribution */ + uint32_t : 8; + __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution */ + uint32_t : 9; + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution */ + uint32_t : 1; + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution */ + uint32_t : 1; + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution */ + uint32_t : 6; + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution */ + uint32_t : 8; + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + uint32_t : 4; + __IOM uint32_t PPARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution */ + uint32_t : 3; + __IOM uint32_t PPARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution */ + uint32_t : 1; + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution */ + uint32_t : 2; + __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution */ + uint32_t : 1; + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution */ + uint32_t : 2; + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution */ + uint32_t : 4; + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege + * Attribution */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution */ + uint32_t : 5; + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege + * Attribution */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege + * Attribution */ + uint32_t : 2; + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution */ + uint32_t : 1; + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution */ + uint32_t : 9; + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege + * Attribution */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege + * Attribution */ + uint32_t : 3; + __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + uint32_t : 4; + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution */ + uint32_t : 5; + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution */ + uint32_t : 3; + __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution */ + uint32_t : 1; + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution */ + uint32_t : 4; + __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution */ + uint32_t : 3; + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + uint32_t : 1; + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Real Time Clock Privilege Attribution */ + uint32_t : 4; + __IOM uint32_t PPARE8 : 1; /*!< [8..8] ULPT1 Privilege Attribution */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] ULPT0 Privilege Attribution */ + uint32_t : 8; + __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + uint32_t : 31; + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[319]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED8[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED9[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED10[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED11[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 31; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40333000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[6]; + __IOM R_ELC_ELSR_Type ELSR[31]; /*!< (@ 0x00000020) Event Link Setting Register [0..30] */ + __IM uint32_t RESERVED3[17]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint32_t : 29; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + uint32_t : 1; + } ELCSARB_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x000000F0) Event Link Controller Priviledge Attribution + * Register A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Priviledge Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Priviledge + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Priviledge + * Attribution */ + uint32_t : 29; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x000000F4) Event Link Controller Priviledge Attribution + * Register B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Priviledge Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Priviledge Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Priviledge Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Priviledge Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Priviledge Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Priviledge Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Priviledge Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Priviledge Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Priviledge Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Priviledge Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Priviledge Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Priviledge Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Priviledge Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Priviledge Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Priviledge Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Priviledge Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Priviledge Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Priviledge Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Priviledge Attribution */ + uint32_t : 1; + } ELCPARB_b; + }; +} R_ELC_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40354100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x40100000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x4011E000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED25; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C100) R_FCACHE Structure */ +{ + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000000) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000004) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED1[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000001C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000040) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution */ + __IOM uint16_t FACITRSA : 1; /*!< [11..11] FACI transfer Security Attribution */ + uint16_t : 4; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 66 (0x42) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[6143]; + + union + { + __IOM uint8_t SWIRQ_S; /*!< (@ 0x00006010) Software Interrupt Request Register for Secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_S_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint8_t SWIRQ_NS; /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_NS_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[15]; + + union + { + __IOM uint16_t IENMIER; /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe + * for CPU */ + + struct + { + __IOM uint16_t CMEN : 1; /*!< [0..0] Integrated Common Memory error nmi Enable */ + __IOM uint16_t LMEN : 1; /*!< [1..1] Integrated Local Memory error nmi Enable */ + __IOM uint16_t BUSEN : 1; /*!< [2..2] Integrated BUS error nmi Enable */ + uint16_t : 13; + } IENMIER_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[39]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint16_t : 2; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint16_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + } NMIER_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint16_t : 2; + __IOM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint16_t : 4; + __IOM uint16_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint16_t CMCLR : 1; /*!< [13..13] CM Clear */ + uint16_t : 1; + __IOM uint16_t LUCLR : 1; /*!< [15..15] LU Clear */ + } NMICLR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint16_t : 2; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint16_t : 4; + __IM uint16_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint16_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + } NMISR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + uint32_t : 1; + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 3; + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t RIIC0WUPEN : 1; /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + uint32_t : 3; + __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 4; + __IOM uint32_t ULP0UWUPEN : 1; /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0AWUPEN : 1; /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0BWUPEN : 1; /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t I3CWUPEN : 1; /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1UWUPEN : 1; /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP1AWUPEN : 1; /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1BWUPEN : 1; /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + uint32_t : 17; + } WUPEN1_b; + }; + __IM uint32_t RESERVED17[86]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED30[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + uint8_t : 3; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] Wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for parity error detection */ + uint8_t : 7; + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM0 ECC Region Control Register */ + + struct + { + __IOM uint8_t ECCRGN : 2; /*!< [1..0] ECC Region */ + uint8_t : 6; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR1 : 1; /*!< [2..2] SRAM1 Parity Error Status */ + uint16_t : 11; + __IM uint16_t ERRS : 1; /*!< [14..14] Standby SRAM Parity Error status */ + uint16_t : 1; + } SRAMESR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __IOM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __IOM uint16_t CLR1 : 1; /*!< [2..2] SRAM1 Parity Error Status Clear */ + uint16_t : 11; + __IOM uint16_t CLRS : 1; /*!< [14..14] Standby SRAM Parity Error Status Clear */ + uint16_t : 1; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t SRAMEAR0; /*!< (@ 0x00000050) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR0_b; + }; + + union + { + __IM uint32_t SRAMEAR1; /*!< (@ 0x00000054) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR1_b; + }; + + union + { + __IM uint32_t SRAMEAR2; /*!< (@ 0x00000058) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR2_b; + }; + __IM uint32_t RESERVED17[45]; + + union + { + __IOM uint8_t STBRAMCR; /*!< (@ 0x00000110) Standby SRAM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection */ + uint8_t : 7; + } STBRAMCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[15]; + + union + { + __IM uint32_t STBRAMEAR; /*!< (@ 0x00000150) Standby SRAM Error Address Register */ + + struct + { + uint32_t : 2; + __IM uint32_t EA : 8; /*!< [9..2] SRAM Error Address */ + uint32_t : 22; + } STBRAMEAR_b; + }; +} R_SRAM_Type; /*!< Size = 340 (0x154) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IM uint8_t SS1RSF : 1; /*!< [0..0] Software Standby 1 regulator status flag */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t FLSCR; /*!< (@ 0x00000010) Flash Standby Control Register */ + + struct + { + __IOM uint8_t FLSWCF : 1; /*!< [0..0] Flash Stabilization wait completion flag */ + uint8_t : 7; + } FLSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] Flash IF Clock (FCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */ + uint8_t : 4; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLLMUL : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select */ + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLL2MUL : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select */ + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED20; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB clock Division control register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI clock Division control register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Core clock Division control register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 clock Division control register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB clock control register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI clock control register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Core clock control register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C clock control register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t I3CCKREQ : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT0 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT1 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT2 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED31; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED32; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 1. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 2. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 3. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 4. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 5. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 6. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 7. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 8. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 9. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 10. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 11. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 12. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 13. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 14. Enable IRQ pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 15. Enable IRQ pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17 Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22 Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23 Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24 Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25 Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28 Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29 Enable AGT1 compare match + * A snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30 Enable AGT1 compare match + * B snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED34; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED35[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED36[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED37; + __IM uint32_t RESERVED38[5]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 1; + __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 4; + __IOM uint32_t BUSRF : 1; /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint32_t : 2; + __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IOM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IOM uint8_t BUSY : 1; /*!< [0..0] Access Ready monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED40; + __IM uint16_t RESERVED41; + __IM uint32_t RESERVED42[4]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED43[3]; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED44; + __IM uint16_t RESERVED45; + __IM uint32_t RESERVED46[7]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) Graphics Power Domain Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED47; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[11]; + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + __IM uint8_t RESERVED50; + __IM uint32_t RESERVED51[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED52; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED53; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + uint32_t : 2; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + uint32_t : 1; + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + uint32_t : 5; + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + uint32_t : 28; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 00 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 03 */ + uint32_t : 4; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 08 */ + uint32_t : 7; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + uint32_t : 1; + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + uint32_t : 10; + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Programable Voltage Detection Security Attribution + * Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + uint32_t : 27; + } BBFSAR_b; + }; + __IM uint32_t RESERVED56; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + uint32_t : 29; + } PGCSAR_b; + }; + __IM uint32_t RESERVED57; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 1; + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + uint32_t : 1; + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + uint32_t : 1; + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + uint32_t : 14; + } RSCSAR_b; + }; + __IM uint32_t RESERVED58[4]; + __IM uint16_t RESERVED59; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED60; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED62; + __IM uint32_t RESERVED63[2]; + __IM uint16_t RESERVED64; + __IM uint8_t RESERVED65; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED66[380]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE */ + uint8_t : 1; + __IOM uint8_t SRKEEP : 1; /*!< [4..4] Standby RAM Retention */ + uint8_t : 1; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED67; + __IM uint16_t RESERVED68; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000A04) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 8; /*!< [7..0] Deep Software Wait Standby Time Setting Bit */ + } DPSWCR_b; + }; + __IM uint8_t RESERVED69; + __IM uint16_t RESERVED70; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ0-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ1-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ2-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ3-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ4-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ5-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ6-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ7-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED71; + __IM uint16_t RESERVED72; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ8-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ9-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED73; + __IM uint16_t RESERVED74; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + __IM uint8_t RESERVED75; + __IM uint16_t RESERVED76; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED77; + __IM uint16_t RESERVED78; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED79; + __IM uint16_t RESERVED80; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED81; + __IM uint16_t RESERVED82; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED83; + __IM uint16_t RESERVED84; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED85; + __IM uint16_t RESERVED86; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED87; + __IM uint16_t RESERVED88; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ8-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ9-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED89; + __IM uint16_t RESERVED90; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select */ + __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED91; + __IM uint16_t RESERVED92; + __IM uint32_t RESERVED93; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED94; + __IM uint16_t RESERVED95; + __IM uint32_t RESERVED96; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD3RF : 1; /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED97; + __IM uint16_t RESERVED98; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED99; + __IM uint16_t RESERVED100; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + uint8_t : 4; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent protection reset Detect Flag */ + uint8_t : 3; + } RSTSR3_b; + }; + __IM uint8_t RESERVED101; + __IM uint16_t RESERVED102; + __IM uint32_t RESERVED103; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED104; + __IM uint16_t RESERVED105; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000A54) Flash Write Erase Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programing and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED106; + __IM uint16_t RESERVED107; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + __IM uint32_t RESERVED112[4]; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED113; + __IM uint16_t RESERVED114; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED115; + __IM uint16_t RESERVED116; + __IM uint32_t RESERVED117[3]; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED120; + __IM uint16_t RESERVED121; + __IM uint32_t RESERVED122; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED123; + __IM uint16_t RESERVED124; + __IM uint32_t RESERVED125; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS1FR : 1; /*!< [0..0] Software Standby 1 Fast Return */ + uint8_t : 7; + } SSCR1_b; + }; + __IM uint8_t RESERVED126; + __IM uint16_t RESERVED127; + __IM uint32_t RESERVED128[5]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Power State Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + __IM uint32_t RESERVED131[7]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent watchdog timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local memory 0 error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common memory error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] BUS error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED132; + __IM uint16_t RESERVED133; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask */ + uint8_t : 2; + __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register2 */ + + struct + { + __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask */ + __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask */ + __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask */ + uint8_t : 3; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED136; + __IM uint16_t RESERVED137; + __IM uint32_t RESERVED138[10]; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED139; + __IM uint16_t RESERVED140; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + __IM uint32_t RESERVED145[4]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED146; + __IM uint16_t RESERVED147; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + __IM uint32_t RESERVED150[54]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-clock oscillator control register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED151; + __IM uint32_t RESERVED152[15]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED153; + __IM uint16_t RESERVED154; + __IM uint8_t RESERVED155; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED156; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED157; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED158; + __IM uint32_t RESERVED159[44]; + + union + { + __IOM uint8_t VBTBKR0; /*!< (@ 0x00000D00) VBATT Backup Register 0 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR0_b; + }; + + union + { + __IOM uint8_t VBTBKR1; /*!< (@ 0x00000D01) VBATT Backup Register 1 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR1_b; + }; + + union + { + __IOM uint8_t VBTBKR2; /*!< (@ 0x00000D02) VBATT Backup Register 2 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR2_b; + }; + + union + { + __IOM uint8_t VBTBKR3; /*!< (@ 0x00000D03) VBATT Backup Register 3 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR3_b; + }; + + union + { + __IOM uint8_t VBTBKR4; /*!< (@ 0x00000D04) VBATT Backup Register 4 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR4_b; + }; + + union + { + __IOM uint8_t VBTBKR5; /*!< (@ 0x00000D05) VBATT Backup Register 5 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR5_b; + }; + + union + { + __IOM uint8_t VBTBKR6; /*!< (@ 0x00000D06) VBATT Backup Register 6 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR6_b; + }; + + union + { + __IOM uint8_t VBTBKR7; /*!< (@ 0x00000D07) VBATT Backup Register 7 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR7_b; + }; + + union + { + __IOM uint8_t VBTBKR8; /*!< (@ 0x00000D08) VBATT Backup Register 8 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR8_b; + }; + + union + { + __IOM uint8_t VBTBKR9; /*!< (@ 0x00000D09) VBATT Backup Register 9 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR9_b; + }; + + union + { + __IOM uint8_t VBTBKR10; /*!< (@ 0x00000D0A) VBATT Backup Register 10 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR10_b; + }; + + union + { + __IOM uint8_t VBTBKR11; /*!< (@ 0x00000D0B) VBATT Backup Register 11 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR11_b; + }; + + union + { + __IOM uint8_t VBTBKR12; /*!< (@ 0x00000D0C) VBATT Backup Register 12 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR12_b; + }; + + union + { + __IOM uint8_t VBTBKR13; /*!< (@ 0x00000D0D) VBATT Backup Register 13 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR13_b; + }; + + union + { + __IOM uint8_t VBTBKR14; /*!< (@ 0x00000D0E) VBATT Backup Register 14 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR14_b; + }; + + union + { + __IOM uint8_t VBTBKR15; /*!< (@ 0x00000D0F) VBATT Backup Register 15 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR15_b; + }; + + union + { + __IOM uint8_t VBTBKR16; /*!< (@ 0x00000D10) VBATT Backup Register 16 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR16_b; + }; + + union + { + __IOM uint8_t VBTBKR17; /*!< (@ 0x00000D11) VBATT Backup Register 17 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR17_b; + }; + + union + { + __IOM uint8_t VBTBKR18; /*!< (@ 0x00000D12) VBATT Backup Register 18 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR18_b; + }; + + union + { + __IOM uint8_t VBTBKR19; /*!< (@ 0x00000D13) VBATT Backup Register 19 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR19_b; + }; + + union + { + __IOM uint8_t VBTBKR20; /*!< (@ 0x00000D14) VBATT Backup Register 20 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR20_b; + }; + + union + { + __IOM uint8_t VBTBKR21; /*!< (@ 0x00000D15) VBATT Backup Register 21 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR21_b; + }; + + union + { + __IOM uint8_t VBTBKR22; /*!< (@ 0x00000D16) VBATT Backup Register 22 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR22_b; + }; + + union + { + __IOM uint8_t VBTBKR23; /*!< (@ 0x00000D17) VBATT Backup Register 23 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR23_b; + }; + + union + { + __IOM uint8_t VBTBKR24; /*!< (@ 0x00000D18) VBATT Backup Register 24 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR24_b; + }; + + union + { + __IOM uint8_t VBTBKR25; /*!< (@ 0x00000D19) VBATT Backup Register 25 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR25_b; + }; + + union + { + __IOM uint8_t VBTBKR26; /*!< (@ 0x00000D1A) VBATT Backup Register 26 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR26_b; + }; + + union + { + __IOM uint8_t VBTBKR27; /*!< (@ 0x00000D1B) VBATT Backup Register 27 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR27_b; + }; + + union + { + __IOM uint8_t VBTBKR28; /*!< (@ 0x00000D1C) VBATT Backup Register 28 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR28_b; + }; + + union + { + __IOM uint8_t VBTBKR29; /*!< (@ 0x00000D1D) VBATT Backup Register 29 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR29_b; + }; + + union + { + __IOM uint8_t VBTBKR30; /*!< (@ 0x00000D1E) VBATT Backup Register 30 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR30_b; + }; + + union + { + __IOM uint8_t VBTBKR31; /*!< (@ 0x00000D1F) VBATT Backup Register 31 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR31_b; + }; + + union + { + __IOM uint8_t VBTBKR32; /*!< (@ 0x00000D20) VBATT Backup Register 32 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR32_b; + }; + + union + { + __IOM uint8_t VBTBKR33; /*!< (@ 0x00000D21) VBATT Backup Register 33 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR33_b; + }; + + union + { + __IOM uint8_t VBTBKR34; /*!< (@ 0x00000D22) VBATT Backup Register 34 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR34_b; + }; + + union + { + __IOM uint8_t VBTBKR35; /*!< (@ 0x00000D23) VBATT Backup Register 35 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR35_b; + }; + + union + { + __IOM uint8_t VBTBKR36; /*!< (@ 0x00000D24) VBATT Backup Register 36 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR36_b; + }; + + union + { + __IOM uint8_t VBTBKR37; /*!< (@ 0x00000D25) VBATT Backup Register 37 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR37_b; + }; + + union + { + __IOM uint8_t VBTBKR38; /*!< (@ 0x00000D26) VBATT Backup Register 38 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR38_b; + }; + + union + { + __IOM uint8_t VBTBKR39; /*!< (@ 0x00000D27) VBATT Backup Register 39 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR39_b; + }; + + union + { + __IOM uint8_t VBTBKR40; /*!< (@ 0x00000D28) VBATT Backup Register 40 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR40_b; + }; + + union + { + __IOM uint8_t VBTBKR41; /*!< (@ 0x00000D29) VBATT Backup Register 41 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR41_b; + }; + + union + { + __IOM uint8_t VBTBKR42; /*!< (@ 0x00000D2A) VBATT Backup Register 42 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR42_b; + }; + + union + { + __IOM uint8_t VBTBKR43; /*!< (@ 0x00000D2B) VBATT Backup Register 43 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR43_b; + }; + + union + { + __IOM uint8_t VBTBKR44; /*!< (@ 0x00000D2C) VBATT Backup Register 44 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR44_b; + }; + + union + { + __IOM uint8_t VBTBKR45; /*!< (@ 0x00000D2D) VBATT Backup Register 45 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR45_b; + }; + + union + { + __IOM uint8_t VBTBKR46; /*!< (@ 0x00000D2E) VBATT Backup Register 46 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR46_b; + }; + + union + { + __IOM uint8_t VBTBKR47; /*!< (@ 0x00000D2F) VBATT Backup Register 47 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR47_b; + }; + + union + { + __IOM uint8_t VBTBKR48; /*!< (@ 0x00000D30) VBATT Backup Register 48 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR48_b; + }; + + union + { + __IOM uint8_t VBTBKR49; /*!< (@ 0x00000D31) VBATT Backup Register 49 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR49_b; + }; + + union + { + __IOM uint8_t VBTBKR50; /*!< (@ 0x00000D32) VBATT Backup Register 50 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR50_b; + }; + + union + { + __IOM uint8_t VBTBKR51; /*!< (@ 0x00000D33) VBATT Backup Register 51 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR51_b; + }; + + union + { + __IOM uint8_t VBTBKR52; /*!< (@ 0x00000D34) VBATT Backup Register 52 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR52_b; + }; + + union + { + __IOM uint8_t VBTBKR53; /*!< (@ 0x00000D35) VBATT Backup Register 53 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR53_b; + }; + + union + { + __IOM uint8_t VBTBKR54; /*!< (@ 0x00000D36) VBATT Backup Register 54 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR54_b; + }; + + union + { + __IOM uint8_t VBTBKR55; /*!< (@ 0x00000D37) VBATT Backup Register 55 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR55_b; + }; + + union + { + __IOM uint8_t VBTBKR56; /*!< (@ 0x00000D38) VBATT Backup Register 56 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR56_b; + }; + + union + { + __IOM uint8_t VBTBKR57; /*!< (@ 0x00000D39) VBATT Backup Register 57 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR57_b; + }; + + union + { + __IOM uint8_t VBTBKR58; /*!< (@ 0x00000D3A) VBATT Backup Register 58 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR58_b; + }; + + union + { + __IOM uint8_t VBTBKR59; /*!< (@ 0x00000D3B) VBATT Backup Register 59 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR59_b; + }; + + union + { + __IOM uint8_t VBTBKR60; /*!< (@ 0x00000D3C) VBATT Backup Register 60 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR60_b; + }; + + union + { + __IOM uint8_t VBTBKR61; /*!< (@ 0x00000D3D) VBATT Backup Register 61 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR61_b; + }; + + union + { + __IOM uint8_t VBTBKR62; /*!< (@ 0x00000D3E) VBATT Backup Register 62 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR62_b; + }; + + union + { + __IOM uint8_t VBTBKR63; /*!< (@ 0x00000D3F) VBATT Backup Register 63 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR63_b; + }; + + union + { + __IOM uint8_t VBTBKR64; /*!< (@ 0x00000D40) VBATT Backup Register 64 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR64_b; + }; + + union + { + __IOM uint8_t VBTBKR65; /*!< (@ 0x00000D41) VBATT Backup Register 65 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR65_b; + }; + + union + { + __IOM uint8_t VBTBKR66; /*!< (@ 0x00000D42) VBATT Backup Register 66 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR66_b; + }; + + union + { + __IOM uint8_t VBTBKR67; /*!< (@ 0x00000D43) VBATT Backup Register 67 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR67_b; + }; + + union + { + __IOM uint8_t VBTBKR68; /*!< (@ 0x00000D44) VBATT Backup Register 68 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR68_b; + }; + + union + { + __IOM uint8_t VBTBKR69; /*!< (@ 0x00000D45) VBATT Backup Register 69 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR69_b; + }; + + union + { + __IOM uint8_t VBTBKR70; /*!< (@ 0x00000D46) VBATT Backup Register 70 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR70_b; + }; + + union + { + __IOM uint8_t VBTBKR71; /*!< (@ 0x00000D47) VBATT Backup Register 71 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR71_b; + }; + + union + { + __IOM uint8_t VBTBKR72; /*!< (@ 0x00000D48) VBATT Backup Register 72 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR72_b; + }; + + union + { + __IOM uint8_t VBTBKR73; /*!< (@ 0x00000D49) VBATT Backup Register 73 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR73_b; + }; + + union + { + __IOM uint8_t VBTBKR74; /*!< (@ 0x00000D4A) VBATT Backup Register 74 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR74_b; + }; + + union + { + __IOM uint8_t VBTBKR75; /*!< (@ 0x00000D4B) VBATT Backup Register 75 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR75_b; + }; + + union + { + __IOM uint8_t VBTBKR76; /*!< (@ 0x00000D4C) VBATT Backup Register 76 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR76_b; + }; + + union + { + __IOM uint8_t VBTBKR77; /*!< (@ 0x00000D4D) VBATT Backup Register 77 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR77_b; + }; + + union + { + __IOM uint8_t VBTBKR78; /*!< (@ 0x00000D4E) VBATT Backup Register 78 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR78_b; + }; + + union + { + __IOM uint8_t VBTBKR79; /*!< (@ 0x00000D4F) VBATT Backup Register 79 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR79_b; + }; + + union + { + __IOM uint8_t VBTBKR80; /*!< (@ 0x00000D50) VBATT Backup Register 80 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR80_b; + }; + + union + { + __IOM uint8_t VBTBKR81; /*!< (@ 0x00000D51) VBATT Backup Register 81 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR81_b; + }; + + union + { + __IOM uint8_t VBTBKR82; /*!< (@ 0x00000D52) VBATT Backup Register 82 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR82_b; + }; + + union + { + __IOM uint8_t VBTBKR83; /*!< (@ 0x00000D53) VBATT Backup Register 83 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR83_b; + }; + + union + { + __IOM uint8_t VBTBKR84; /*!< (@ 0x00000D54) VBATT Backup Register 84 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR84_b; + }; + + union + { + __IOM uint8_t VBTBKR85; /*!< (@ 0x00000D55) VBATT Backup Register 85 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR85_b; + }; + + union + { + __IOM uint8_t VBTBKR86; /*!< (@ 0x00000D56) VBATT Backup Register 86 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR86_b; + }; + + union + { + __IOM uint8_t VBTBKR87; /*!< (@ 0x00000D57) VBATT Backup Register 87 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR87_b; + }; + + union + { + __IOM uint8_t VBTBKR88; /*!< (@ 0x00000D58) VBATT Backup Register 88 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR88_b; + }; + + union + { + __IOM uint8_t VBTBKR89; /*!< (@ 0x00000D59) VBATT Backup Register 89 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR89_b; + }; + + union + { + __IOM uint8_t VBTBKR90; /*!< (@ 0x00000D5A) VBATT Backup Register 90 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR90_b; + }; + + union + { + __IOM uint8_t VBTBKR91; /*!< (@ 0x00000D5B) VBATT Backup Register 91 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR91_b; + }; + + union + { + __IOM uint8_t VBTBKR92; /*!< (@ 0x00000D5C) VBATT Backup Register 92 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR92_b; + }; + + union + { + __IOM uint8_t VBTBKR93; /*!< (@ 0x00000D5D) VBATT Backup Register 93 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR93_b; + }; + + union + { + __IOM uint8_t VBTBKR94; /*!< (@ 0x00000D5E) VBATT Backup Register 94 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR94_b; + }; + + union + { + __IOM uint8_t VBTBKR95; /*!< (@ 0x00000D5F) VBATT Backup Register 95 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR95_b; + }; + + union + { + __IOM uint8_t VBTBKR96; /*!< (@ 0x00000D60) VBATT Backup Register 96 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR96_b; + }; + + union + { + __IOM uint8_t VBTBKR97; /*!< (@ 0x00000D61) VBATT Backup Register 97 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR97_b; + }; + + union + { + __IOM uint8_t VBTBKR98; /*!< (@ 0x00000D62) VBATT Backup Register 98 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR98_b; + }; + + union + { + __IOM uint8_t VBTBKR99; /*!< (@ 0x00000D63) VBATT Backup Register 99 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR99_b; + }; + + union + { + __IOM uint8_t VBTBKR100; /*!< (@ 0x00000D64) VBATT Backup Register 100 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR100_b; + }; + + union + { + __IOM uint8_t VBTBKR101; /*!< (@ 0x00000D65) VBATT Backup Register 101 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR101_b; + }; + + union + { + __IOM uint8_t VBTBKR102; /*!< (@ 0x00000D66) VBATT Backup Register 102 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR102_b; + }; + + union + { + __IOM uint8_t VBTBKR103; /*!< (@ 0x00000D67) VBATT Backup Register 103 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR103_b; + }; + + union + { + __IOM uint8_t VBTBKR104; /*!< (@ 0x00000D68) VBATT Backup Register 104 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR104_b; + }; + + union + { + __IOM uint8_t VBTBKR105; /*!< (@ 0x00000D69) VBATT Backup Register 105 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR105_b; + }; + + union + { + __IOM uint8_t VBTBKR106; /*!< (@ 0x00000D6A) VBATT Backup Register 106 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR106_b; + }; + + union + { + __IOM uint8_t VBTBKR107; /*!< (@ 0x00000D6B) VBATT Backup Register 107 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR107_b; + }; + + union + { + __IOM uint8_t VBTBKR108; /*!< (@ 0x00000D6C) VBATT Backup Register 108 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR108_b; + }; + + union + { + __IOM uint8_t VBTBKR109; /*!< (@ 0x00000D6D) VBATT Backup Register 109 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR109_b; + }; + + union + { + __IOM uint8_t VBTBKR110; /*!< (@ 0x00000D6E) VBATT Backup Register 110 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR110_b; + }; + + union + { + __IOM uint8_t VBTBKR111; /*!< (@ 0x00000D6F) VBATT Backup Register 111 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR111_b; + }; + + union + { + __IOM uint8_t VBTBKR112; /*!< (@ 0x00000D70) VBATT Backup Register 112 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR112_b; + }; + + union + { + __IOM uint8_t VBTBKR113; /*!< (@ 0x00000D71) VBATT Backup Register 113 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR113_b; + }; + + union + { + __IOM uint8_t VBTBKR114; /*!< (@ 0x00000D72) VBATT Backup Register 114 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR114_b; + }; + + union + { + __IOM uint8_t VBTBKR115; /*!< (@ 0x00000D73) VBATT Backup Register 115 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR115_b; + }; + + union + { + __IOM uint8_t VBTBKR116; /*!< (@ 0x00000D74) VBATT Backup Register 116 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR116_b; + }; + + union + { + __IOM uint8_t VBTBKR117; /*!< (@ 0x00000D75) VBATT Backup Register 117 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR117_b; + }; + + union + { + __IOM uint8_t VBTBKR118; /*!< (@ 0x00000D76) VBATT Backup Register 118 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR118_b; + }; + + union + { + __IOM uint8_t VBTBKR119; /*!< (@ 0x00000D77) VBATT Backup Register 119 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR119_b; + }; + + union + { + __IOM uint8_t VBTBKR120; /*!< (@ 0x00000D78) VBATT Backup Register 120 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR120_b; + }; + + union + { + __IOM uint8_t VBTBKR121; /*!< (@ 0x00000D79) VBATT Backup Register 121 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR121_b; + }; + + union + { + __IOM uint8_t VBTBKR122; /*!< (@ 0x00000D7A) VBATT Backup Register 122 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR122_b; + }; + + union + { + __IOM uint8_t VBTBKR123; /*!< (@ 0x00000D7B) VBATT Backup Register 123 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR123_b; + }; + + union + { + __IOM uint8_t VBTBKR124; /*!< (@ 0x00000D7C) VBATT Backup Register 124 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR124_b; + }; + + union + { + __IOM uint8_t VBTBKR125; /*!< (@ 0x00000D7D) VBATT Backup Register 125 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR125_b; + }; + + union + { + __IOM uint8_t VBTBKR126; /*!< (@ 0x00000D7E) VBATT Backup Register 126 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR126_b; + }; + + union + { + __IOM uint8_t VBTBKR127; /*!< (@ 0x00000D7F) VBATT Backup Register 127 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR127_b; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x4011B17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40004000) R_TZF Structure */ +{ + __IM uint16_t RESERVED[8]; + + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000010) TrustZone Filter Operation After Detection register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000014) TrustZone Filter Protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } TZFPT_b; + }; +} R_TZF_Type; /*!< Size = 22 (0x16) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 3; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 4; + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[26]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED8[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED9[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + __IM uint32_t RESERVED[192]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x4011C000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH) + */ + +typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure */ +{ + __IM uint32_t RESERVED[32]; + + union + { + __IM uint32_t FSBLCTRL0; /*!< (@ 0x00000080) FSBL Control Register 0 */ + + struct + { + __IM uint32_t FSBLEN : 3; /*!< [2..0] FSBL Enable */ + __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset */ + __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset */ + __IM uint32_t FSBLCLK : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution */ + uint32_t : 20; + } FSBLCTRL0_b; + }; + + union + { + __IM uint32_t FSBLCTRL1; /*!< (@ 0x00000084) FSBL Control Register 1 */ + + struct + { + __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode */ + uint32_t : 30; + } FSBLCTRL1_b; + }; + + union + { + __IM uint32_t FSBLCTRL2; /*!< (@ 0x00000088) FSBL Control Register 2 */ + + struct + { + __IM uint32_t PORTPN : 4; /*!< [3..0] FSBL Error Notification Port Pin Number */ + __IM uint32_t PORTGN : 5; /*!< [8..4] FSBL Error Notification Port Group Name */ + uint32_t : 23; + } FSBLCTRL2_b; + }; + __IOM uint32_t SACC0; /*!< (@ 0x0000008C) Start Address of Code Certification 0 */ + __IOM uint32_t SACC1; /*!< (@ 0x00000090) Start Address of Code Certification 1 */ + __IOM uint32_t SAMR; /*!< (@ 0x00000094) Start Address of Measurement Report */ + __IM uint32_t RESERVED1[178]; + __IM uint32_t HOEMRTPK; /*!< (@ 0x00000360) Hask of OEM_ROOT_PK */ + __IM uint32_t RESERVED2[7]; + __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits */ + __IM uint32_t RESERVED3[11]; + + union + { + __IOM uint16_t ARCLS; /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting */ + + struct + { + __IOM uint16_t ARCS_LK : 1; /*!< [0..0] ARC_SEC Lock */ + __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock */ + __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock */ + uint16_t : 10; + } ARCLS_b; + }; + + union + { + __IOM uint16_t ARCCS; /*!< (@ 0x000003C2) ARCCS */ + + struct + { + __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC */ + uint16_t : 14; + } ARCCS_b; + }; + __IM uint32_t RESERVED4[291]; + + union + { + __IOM uint32_t ARC_SEC[2]; /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application + * n */ + + struct + { + __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC */ + } ARC_SEC_b[2]; + }; + + union + { + __IOM uint32_t ARC_NSEC[8]; /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application */ + + struct + { + __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application */ + } ARC_NSEC_b[8]; + }; + + union + { + __IOM uint32_t ARC_OEMBL[2]; /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL */ + + struct + { + __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application */ + } ARC_OEMBL_b[2]; + }; +} R_OFS_DATAFLASH_Type; /*!< Size = 2176 (0x880) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_ADC0_BASE (0x40332000UL + BASE_NS_OFFSET) + #define R_ADC1_BASE (0x40332200UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) + #define R_DAC1_BASE (0x40333100UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC0_BASE (0x40354100UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_FACI_HP_CMD_BASE (0x40100000UL + BASE_NS_OFFSET) + #define R_FACI_HP_BASE (0x4011E000UL + BASE_NS_OFFSET) + #define R_FCACHE_BASE (0x4001C100UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x4011B17CUL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_TZF_BASE (0x40004000UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) + #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI ((R_XSPI_Type *) R_XSPI_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFGD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFGD_L ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== CFGD_H ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CFGDLOCK ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CFGD2 ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC7_Pos (7UL) /*!< PSARC7 (Bit 7) */ + #define R_PSCU_PSARC_PSARC7_Msk (0x80UL) /*!< PSARC7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC11_Pos (11UL) /*!< PSARC11 (Bit 11) */ + #define R_PSCU_PSARC_PSARC11_Msk (0x800UL) /*!< PSARC11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC15_Pos (15UL) /*!< PSARC15 (Bit 15) */ + #define R_PSCU_PSARC_PSARC15_Msk (0x8000UL) /*!< PSARC15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC16_Pos (16UL) /*!< PSARC16 (Bit 16) */ + #define R_PSCU_PSARC_PSARC16_Msk (0x10000UL) /*!< PSARC16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */ + #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD4_Pos (4UL) /*!< PSARD4 (Bit 4) */ + #define R_PSCU_PSARD_PSARD4_Msk (0x10UL) /*!< PSARD4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD5_Pos (5UL) /*!< PSARD5 (Bit 5) */ + #define R_PSCU_PSARD_PSARD5_Msk (0x20UL) /*!< PSARD5 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE3_Pos (3UL) /*!< PSARE3 (Bit 3) */ + #define R_PSCU_PSARE_PSARE3_Msk (0x8UL) /*!< PSARE3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE8_Pos (8UL) /*!< PSARE8 (Bit 8) */ + #define R_PSCU_PSARE_PSARE8_Msk (0x100UL) /*!< PSARE8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE9_Pos (9UL) /*!< PSARE9 (Bit 9) */ + #define R_PSCU_PSARE_PSARE9_Msk (0x200UL) /*!< PSARE9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE18_Pos (18UL) /*!< PSARE18 (Bit 18) */ + #define R_PSCU_PSARE_PSARE18_Msk (0x40000UL) /*!< PSARE18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE19_Pos (19UL) /*!< PSARE19 (Bit 19) */ + #define R_PSCU_PSARE_PSARE19_Msk (0x80000UL) /*!< PSARE19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE20_Pos (20UL) /*!< PSARE20 (Bit 20) */ + #define R_PSCU_PSARE_PSARE20_Msk (0x100000UL) /*!< PSARE20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE21_Pos (21UL) /*!< PSARE21 (Bit 21) */ + #define R_PSCU_PSARE_PSARE21_Msk (0x200000UL) /*!< PSARE21 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR11_Pos (11UL) /*!< MSSAR11 (Bit 11) */ + #define R_PSCU_MSSAR_MSSAR11_Msk (0x800UL) /*!< MSSAR11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR13_Pos (13UL) /*!< MSSAR13 (Bit 13) */ + #define R_PSCU_MSSAR_MSSAR13_Msk (0x2000UL) /*!< MSSAR13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR15_Pos (15UL) /*!< MSSAR15 (Bit 15) */ + #define R_PSCU_MSSAR_MSSAR15_Msk (0x8000UL) /*!< MSSAR15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR22_Pos (22UL) /*!< MSSAR22 (Bit 22) */ + #define R_PSCU_MSSAR_MSSAR22_Msk (0x400000UL) /*!< MSSAR22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR31_Pos (31UL) /*!< MSSAR31 (Bit 31) */ + #define R_PSCU_MSSAR_MSSAR31_Msk (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB4_Pos (4UL) /*!< PPARB4 (Bit 4) */ + #define R_PSCU_PPARB_PPARB4_Msk (0x10UL) /*!< PPARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB8_Pos (8UL) /*!< PPARB8 (Bit 8) */ + #define R_PSCU_PPARB_PPARB8_Msk (0x100UL) /*!< PPARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB9_Pos (9UL) /*!< PPARB9 (Bit 9) */ + #define R_PSCU_PPARB_PPARB9_Msk (0x200UL) /*!< PPARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB11_Pos (11UL) /*!< PPARB11 (Bit 11) */ + #define R_PSCU_PPARB_PPARB11_Msk (0x800UL) /*!< PPARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB12_Pos (12UL) /*!< PPARB12 (Bit 12) */ + #define R_PSCU_PPARB_PPARB12_Msk (0x1000UL) /*!< PPARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB15_Pos (15UL) /*!< PPARB15 (Bit 15) */ + #define R_PSCU_PPARB_PPARB15_Msk (0x8000UL) /*!< PPARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB16_Pos (16UL) /*!< PPARB16 (Bit 16) */ + #define R_PSCU_PPARB_PPARB16_Msk (0x10000UL) /*!< PPARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB18_Pos (18UL) /*!< PPARB18 (Bit 18) */ + #define R_PSCU_PPARB_PPARB18_Msk (0x40000UL) /*!< PPARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB19_Pos (19UL) /*!< PPARB19 (Bit 19) */ + #define R_PSCU_PPARB_PPARB19_Msk (0x80000UL) /*!< PPARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB22_Pos (22UL) /*!< PPARB22 (Bit 22) */ + #define R_PSCU_PPARB_PPARB22_Msk (0x400000UL) /*!< PPARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB27_Pos (27UL) /*!< PPARB27 (Bit 27) */ + #define R_PSCU_PPARB_PPARB27_Msk (0x8000000UL) /*!< PPARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB28_Pos (28UL) /*!< PPARB28 (Bit 28) */ + #define R_PSCU_PPARB_PPARB28_Msk (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB29_Pos (29UL) /*!< PPARB29 (Bit 29) */ + #define R_PSCU_PPARB_PPARB29_Msk (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB30_Pos (30UL) /*!< PPARB30 (Bit 30) */ + #define R_PSCU_PPARB_PPARB30_Msk (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARB_PPARB31_Pos (31UL) /*!< PPARB31 (Bit 31) */ + #define R_PSCU_PPARB_PPARB31_Msk (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC0_Pos (0UL) /*!< PPARC0 (Bit 0) */ + #define R_PSCU_PPARC_PPARC0_Msk (0x1UL) /*!< PPARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC1_Pos (1UL) /*!< PPARC1 (Bit 1) */ + #define R_PSCU_PPARC_PPARC1_Msk (0x2UL) /*!< PPARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC7_Pos (7UL) /*!< PPARC7 (Bit 7) */ + #define R_PSCU_PPARC_PPARC7_Msk (0x80UL) /*!< PPARC7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC8_Pos (8UL) /*!< PPARC8 (Bit 8) */ + #define R_PSCU_PPARC_PPARC8_Msk (0x100UL) /*!< PPARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC11_Pos (11UL) /*!< PPARC11 (Bit 11) */ + #define R_PSCU_PPARC_PPARC11_Msk (0x800UL) /*!< PPARC11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC12_Pos (12UL) /*!< PPARC12 (Bit 12) */ + #define R_PSCU_PPARC_PPARC12_Msk (0x1000UL) /*!< PPARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC13_Pos (13UL) /*!< PPARC13 (Bit 13) */ + #define R_PSCU_PPARC_PPARC13_Msk (0x2000UL) /*!< PPARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC15_Pos (15UL) /*!< PPARC15 (Bit 15) */ + #define R_PSCU_PPARC_PPARC15_Msk (0x8000UL) /*!< PPARC15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC16_Pos (16UL) /*!< PPARC16 (Bit 16) */ + #define R_PSCU_PPARC_PPARC16_Msk (0x10000UL) /*!< PPARC16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC26_Pos (26UL) /*!< PPARC26 (Bit 26) */ + #define R_PSCU_PPARC_PPARC26_Msk (0x4000000UL) /*!< PPARC26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC27_Pos (27UL) /*!< PPARC27 (Bit 27) */ + #define R_PSCU_PPARC_PPARC27_Msk (0x8000000UL) /*!< PPARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARC_PPARC31_Pos (31UL) /*!< PPARC31 (Bit 31) */ + #define R_PSCU_PPARC_PPARC31_Msk (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD4_Pos (4UL) /*!< PPARD4 (Bit 4) */ + #define R_PSCU_PPARD_PPARD4_Msk (0x10UL) /*!< PPARD4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD5_Pos (5UL) /*!< PPARD5 (Bit 5) */ + #define R_PSCU_PPARD_PPARD5_Msk (0x20UL) /*!< PPARD5 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD11_Pos (11UL) /*!< PPARD11 (Bit 11) */ + #define R_PSCU_PPARD_PPARD11_Msk (0x800UL) /*!< PPARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD12_Pos (12UL) /*!< PPARD12 (Bit 12) */ + #define R_PSCU_PPARD_PPARD12_Msk (0x1000UL) /*!< PPARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD13_Pos (13UL) /*!< PPARD13 (Bit 13) */ + #define R_PSCU_PPARD_PPARD13_Msk (0x2000UL) /*!< PPARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD14_Pos (14UL) /*!< PPARD14 (Bit 14) */ + #define R_PSCU_PPARD_PPARD14_Msk (0x4000UL) /*!< PPARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD15_Pos (15UL) /*!< PPARD15 (Bit 15) */ + #define R_PSCU_PPARD_PPARD15_Msk (0x8000UL) /*!< PPARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD16_Pos (16UL) /*!< PPARD16 (Bit 16) */ + #define R_PSCU_PPARD_PPARD16_Msk (0x10000UL) /*!< PPARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD20_Pos (20UL) /*!< PPARD20 (Bit 20) */ + #define R_PSCU_PPARD_PPARD20_Msk (0x100000UL) /*!< PPARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD22_Pos (22UL) /*!< PPARD22 (Bit 22) */ + #define R_PSCU_PPARD_PPARD22_Msk (0x400000UL) /*!< PPARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD27_Pos (27UL) /*!< PPARD27 (Bit 27) */ + #define R_PSCU_PPARD_PPARD27_Msk (0x8000000UL) /*!< PPARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARD_PPARD28_Pos (28UL) /*!< PPARD28 (Bit 28) */ + #define R_PSCU_PPARD_PPARD28_Msk (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE1_Pos (1UL) /*!< PPARE1 (Bit 1) */ + #define R_PSCU_PPARE_PPARE1_Msk (0x2UL) /*!< PPARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE2_Pos (2UL) /*!< PPARE2 (Bit 2) */ + #define R_PSCU_PPARE_PPARE2_Msk (0x4UL) /*!< PPARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE3_Pos (3UL) /*!< PPARE3 (Bit 3) */ + #define R_PSCU_PPARE_PPARE3_Msk (0x8UL) /*!< PPARE3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE8_Pos (8UL) /*!< PPARE8 (Bit 8) */ + #define R_PSCU_PPARE_PPARE8_Msk (0x100UL) /*!< PPARE8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE9_Pos (9UL) /*!< PPARE9 (Bit 9) */ + #define R_PSCU_PPARE_PPARE9_Msk (0x200UL) /*!< PPARE9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE18_Pos (18UL) /*!< PPARE18 (Bit 18) */ + #define R_PSCU_PPARE_PPARE18_Msk (0x40000UL) /*!< PPARE18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE19_Pos (19UL) /*!< PPARE19 (Bit 19) */ + #define R_PSCU_PPARE_PPARE19_Msk (0x80000UL) /*!< PPARE19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE20_Pos (20UL) /*!< PPARE20 (Bit 20) */ + #define R_PSCU_PPARE_PPARE20_Msk (0x100000UL) /*!< PPARE20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE21_Pos (21UL) /*!< PPARE21 (Bit 21) */ + #define R_PSCU_PPARE_PPARE21_Msk (0x200000UL) /*!< PPARE21 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE22_Pos (22UL) /*!< PPARE22 (Bit 22) */ + #define R_PSCU_PPARE_PPARE22_Msk (0x400000UL) /*!< PPARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE23_Pos (23UL) /*!< PPARE23 (Bit 23) */ + #define R_PSCU_PPARE_PPARE23_Msk (0x800000UL) /*!< PPARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE24_Pos (24UL) /*!< PPARE24 (Bit 24) */ + #define R_PSCU_PPARE_PPARE24_Msk (0x1000000UL) /*!< PPARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE25_Pos (25UL) /*!< PPARE25 (Bit 25) */ + #define R_PSCU_PPARE_PPARE25_Msk (0x2000000UL) /*!< PPARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE26_Pos (26UL) /*!< PPARE26 (Bit 26) */ + #define R_PSCU_PPARE_PPARE26_Msk (0x4000000UL) /*!< PPARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE27_Pos (27UL) /*!< PPARE27 (Bit 27) */ + #define R_PSCU_PPARE_PPARE27_Msk (0x8000000UL) /*!< PPARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE28_Pos (28UL) /*!< PPARE28 (Bit 28) */ + #define R_PSCU_PPARE_PPARE28_Msk (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE29_Pos (29UL) /*!< PPARE29 (Bit 29) */ + #define R_PSCU_PPARE_PPARE29_Msk (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE30_Pos (30UL) /*!< PPARE30 (Bit 30) */ + #define R_PSCU_PPARE_PPARE30_Msk (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PPARE_PPARE31_Pos (31UL) /*!< PPARE31 (Bit 31) */ + #define R_PSCU_PPARE_PPARE31_Msk (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR31_Pos (31UL) /*!< MSPAR31 (Bit 31) */ + #define R_PSCU_MSPAR_MSPAR31_Msk (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCSARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCPARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCPARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCACHEENSA_Pos (1UL) /*!< FCACHEENSA (Bit 1) */ + #define R_FCACHE_FSAR_FCACHEENSA_Msk (0x2UL) /*!< FCACHEENSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACITRSA_Pos (11UL) /*!< FACITRSA (Bit 11) */ + #define R_FCACHE_FSAR_FACITRSA_Msk (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */ + #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */ + #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SWIRQ_S ======================================================== */ + #define R_ICU_SWIRQ_S_SWIRQS_Pos (0UL) /*!< SWIRQS (Bit 0) */ + #define R_ICU_SWIRQ_S_SWIRQS_Msk (0x1UL) /*!< SWIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= SWIRQ_NS ======================================================== */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Pos (0UL) /*!< SWIRQNS (Bit 0) */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Msk (0x1UL) /*!< SWIRQNS (Bitfield-Mask: 0x01) */ +/* ======================================================== IENMIER ======================================================== */ + #define R_ICU_IENMIER_CMEN_Pos (0UL) /*!< CMEN (Bit 0) */ + #define R_ICU_IENMIER_CMEN_Msk (0x1UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_LMEN_Pos (1UL) /*!< LMEN (Bit 1) */ + #define R_ICU_IENMIER_LMEN_Msk (0x2UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_BUSEN_Pos (2UL) /*!< BUSEN (Bit 2) */ + #define R_ICU_IENMIER_BUSEN_Msk (0x4UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN0_Pos (0UL) /*!< IRQWUPEN0 (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN0_Msk (0x1UL) /*!< IRQWUPEN0 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN1_Pos (1UL) /*!< IRQWUPEN1 (Bit 1) */ + #define R_ICU_WUPEN_IRQWUPEN1_Msk (0x2UL) /*!< IRQWUPEN1 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN2_Pos (2UL) /*!< IRQWUPEN2 (Bit 2) */ + #define R_ICU_WUPEN_IRQWUPEN2_Msk (0x4UL) /*!< IRQWUPEN2 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN3_Pos (3UL) /*!< IRQWUPEN3 (Bit 3) */ + #define R_ICU_WUPEN_IRQWUPEN3_Msk (0x8UL) /*!< IRQWUPEN3 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN4_Pos (4UL) /*!< IRQWUPEN4 (Bit 4) */ + #define R_ICU_WUPEN_IRQWUPEN4_Msk (0x10UL) /*!< IRQWUPEN4 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN5_Pos (5UL) /*!< IRQWUPEN5 (Bit 5) */ + #define R_ICU_WUPEN_IRQWUPEN5_Msk (0x20UL) /*!< IRQWUPEN5 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN6_Pos (6UL) /*!< IRQWUPEN6 (Bit 6) */ + #define R_ICU_WUPEN_IRQWUPEN6_Msk (0x40UL) /*!< IRQWUPEN6 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN7_Pos (7UL) /*!< IRQWUPEN7 (Bit 7) */ + #define R_ICU_WUPEN_IRQWUPEN7_Msk (0x80UL) /*!< IRQWUPEN7 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN8_Pos (8UL) /*!< IRQWUPEN8 (Bit 8) */ + #define R_ICU_WUPEN_IRQWUPEN8_Msk (0x100UL) /*!< IRQWUPEN8 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN9_Pos (9UL) /*!< IRQWUPEN9 (Bit 9) */ + #define R_ICU_WUPEN_IRQWUPEN9_Msk (0x200UL) /*!< IRQWUPEN9 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN10_Pos (10UL) /*!< IRQWUPEN10 (Bit 10) */ + #define R_ICU_WUPEN_IRQWUPEN10_Msk (0x400UL) /*!< IRQWUPEN10 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN11_Pos (11UL) /*!< IRQWUPEN11 (Bit 11) */ + #define R_ICU_WUPEN_IRQWUPEN11_Msk (0x800UL) /*!< IRQWUPEN11 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN12_Pos (12UL) /*!< IRQWUPEN12 (Bit 12) */ + #define R_ICU_WUPEN_IRQWUPEN12_Msk (0x1000UL) /*!< IRQWUPEN12 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN13_Pos (13UL) /*!< IRQWUPEN13 (Bit 13) */ + #define R_ICU_WUPEN_IRQWUPEN13_Msk (0x2000UL) /*!< IRQWUPEN13 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN14_Pos (14UL) /*!< IRQWUPEN14 (Bit 14) */ + #define R_ICU_WUPEN_IRQWUPEN14_Msk (0x4000UL) /*!< IRQWUPEN14 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN15_Pos (15UL) /*!< IRQWUPEN15 (Bit 15) */ + #define R_ICU_WUPEN_IRQWUPEN15_Msk (0x8000UL) /*!< IRQWUPEN15 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Pos (31UL) /*!< RIIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Msk (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos (3UL) /*!< COMPHS0WUPEN (Bit 3) */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk (0x8UL) /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Pos (8UL) /*!< ULP0UWUPEN (Bit 8) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Msk (0x100UL) /*!< ULP0UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Pos (9UL) /*!< ULP0AWUPEN (Bit 9) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Msk (0x200UL) /*!< ULP0AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Pos (10UL) /*!< ULP0BWUPEN (Bit 10) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Msk (0x400UL) /*!< ULP0BWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_I3CWUPEN_Pos (11UL) /*!< I3CWUPEN (Bit 11) */ + #define R_ICU_WUPEN1_I3CWUPEN_Msk (0x800UL) /*!< I3CWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Pos (12UL) /*!< ULP1UWUPEN (Bit 12) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Msk (0x1000UL) /*!< ULP1UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Pos (13UL) /*!< ULP1AWUPEN (Bit 13) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Msk (0x2000UL) /*!< ULP1AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Pos (14UL) /*!< ULP1BWUPEN (Bit 14) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Msk (0x4000UL) /*!< ULP1BWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x3UL) /*!< ECCRGN (Bitfield-Mask: 0x03) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR00_Pos (0UL) /*!< ERR00 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR00_Msk (0x1UL) /*!< ERR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR01_Pos (1UL) /*!< ERR01 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR01_Msk (0x2UL) /*!< ERR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (2UL) /*!< ERR1 (Bit 2) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x4UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERRS_Pos (14UL) /*!< ERRS (Bit 14) */ + #define R_SRAM_SRAMESR_ERRS_Msk (0x4000UL) /*!< ERRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR00_Pos (0UL) /*!< CLR00 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR00_Msk (0x1UL) /*!< CLR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR01_Pos (1UL) /*!< CLR01 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR01_Msk (0x2UL) /*!< CLR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (2UL) /*!< CLR1 (Bit 2) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x4UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLRS_Pos (14UL) /*!< CLRS (Bit 14) */ + #define R_SRAM_SRAMESCLR_CLRS_Msk (0x4000UL) /*!< CLRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR0 ======================================================== */ + #define R_SRAM_SRAMEAR0_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR0_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR1 ======================================================== */ + #define R_SRAM_SRAMEAR1_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR1_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR2 ======================================================== */ + #define R_SRAM_SRAMEAR2_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR2_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= STBRAMCR ======================================================== */ + #define R_SRAM_STBRAMCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_STBRAMCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMEAR ======================================================= */ + #define R_SRAM_STBRAMEAR_EA_Pos (2UL) /*!< EA (Bit 2) */ + #define R_SRAM_STBRAMEAR_EA_Msk (0x3fcUL) /*!< EA (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS1RSF_Pos (0UL) /*!< SS1RSF (Bit 0) */ + #define R_SYSTEM_SSCR2_SS1RSF_Msk (0x1UL) /*!< SS1RSF (Bitfield-Mask: 0x01) */ +/* ========================================================= FLSCR ========================================================= */ + #define R_SYSTEM_FLSCR_FLSWCF_Pos (0UL) /*!< FLSWCF (Bit 0) */ + #define R_SYSTEM_FLSCR_FLSWCF_Msk (0x1UL) /*!< FLSWCF (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0xff00UL) /*!< PLLMUL (Bitfield-Mask: 0xff) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0xff00UL) /*!< PLL2MUL (Bitfield-Mask: 0xff) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos (6UL) /*!< I3CCKREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk (0x40UL) /*!< I3CCKREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos (0UL) /*!< HOCOSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk (0x1UL) /*!< HOCOSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Pos (4UL) /*!< CLU0RF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Msk (0x10UL) /*!< CLU0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSRF_Pos (10UL) /*!< BUSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSRF_Msk (0x400UL) /*!< BUSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ +/* ======================================================= PDRAMSCR1 ======================================================= */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Pos (13UL) /*!< NONSEC13 (Bit 13) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Msk (0x2000UL) /*!< NONSEC13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Pos (24UL) /*!< NONSEC24 (Bit 24) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Msk (0x1000000UL) /*!< NONSEC24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Pos (25UL) /*!< NONSEC25 (Bit 25) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Msk (0x2000000UL) /*!< NONSEC25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Pos (26UL) /*!< NONSEC26 (Bit 26) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Msk (0x4000000UL) /*!< NONSEC26 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_PGCSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Pos (25UL) /*!< DPFSA25 (Bit 25) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Msk (0x2000000UL) /*!< DPFSA25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Pos (29UL) /*!< DPFSA29 (Bit 29) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Msk (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Pos (31UL) /*!< DPFSA31 (Bit 31) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Msk (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA0_Pos (0UL) /*!< RSCSA0 (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA0_Msk (0x1UL) /*!< RSCSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Pos (1UL) /*!< RSCSA1 (Bit 1) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Msk (0x2UL) /*!< RSCSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Pos (2UL) /*!< RSCSA2 (Bit 2) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Msk (0x4UL) /*!< RSCSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Pos (3UL) /*!< RSCSA3 (Bit 3) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Msk (0x8UL) /*!< RSCSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Pos (4UL) /*!< RSCSA4 (Bit 4) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Msk (0x10UL) /*!< RSCSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Pos (5UL) /*!< RSCSA5 (Bit 5) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Msk (0x20UL) /*!< RSCSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Pos (6UL) /*!< RSCSA6 (Bit 6) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Msk (0x40UL) /*!< RSCSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Pos (7UL) /*!< RSCSA7 (Bit 7) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Msk (0x80UL) /*!< RSCSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Pos (8UL) /*!< RSCSA8 (Bit 8) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Msk (0x100UL) /*!< RSCSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Pos (9UL) /*!< RSCSA9 (Bit 9) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Msk (0x200UL) /*!< RSCSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Pos (10UL) /*!< RSCSA10 (Bit 10) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Msk (0x400UL) /*!< RSCSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Pos (11UL) /*!< RSCSA11 (Bit 11) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Msk (0x800UL) /*!< RSCSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Pos (12UL) /*!< RSCSA12 (Bit 12) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Msk (0x1000UL) /*!< RSCSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Pos (13UL) /*!< RSCSA13 (Bit 13) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Msk (0x2000UL) /*!< RSCSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Pos (14UL) /*!< RSCSA14 (Bit 14) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Msk (0x4000UL) /*!< RSCSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Pos (16UL) /*!< RSCSA16 (Bit 16) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Msk (0x10000UL) /*!< RSCSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Pos (17UL) /*!< RSCSA17 (Bit 17) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Msk (0x20000UL) /*!< RSCSA17 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0x4UL) /*!< DCSSMODE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Pos (4UL) /*!< SRKEEP (Bit 4) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Msk (0x10UL) /*!< SRKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0xffUL) /*!< WTSTS (Bitfield-Mask: 0xff) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Pos (0UL) /*!< DIRQ0E (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Msk (0x1UL) /*!< DIRQ0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Pos (1UL) /*!< DIRQ1E (Bit 1) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Msk (0x2UL) /*!< DIRQ1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Pos (2UL) /*!< DIRQ2E (Bit 2) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Msk (0x4UL) /*!< DIRQ2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Pos (3UL) /*!< DIRQ3E (Bit 3) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Msk (0x8UL) /*!< DIRQ3E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Pos (4UL) /*!< DIRQ4E (Bit 4) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Msk (0x10UL) /*!< DIRQ4E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Pos (5UL) /*!< DIRQ5E (Bit 5) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Msk (0x20UL) /*!< DIRQ5E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Pos (6UL) /*!< DIRQ6E (Bit 6) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Msk (0x40UL) /*!< DIRQ6E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Pos (7UL) /*!< DIRQ7E (Bit 7) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Msk (0x80UL) /*!< DIRQ7E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Pos (0UL) /*!< DIRQ8E (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Msk (0x1UL) /*!< DIRQ8E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Pos (1UL) /*!< DIRQ9E (Bit 1) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Msk (0x2UL) /*!< DIRQ9E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Pos (2UL) /*!< DIRQ10E (Bit 2) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Msk (0x4UL) /*!< DIRQ10E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Pos (3UL) /*!< DIRQ11E (Bit 3) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Msk (0x8UL) /*!< DIRQ11E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Pos (4UL) /*!< DIRQ12E (Bit 4) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Msk (0x10UL) /*!< DIRQ12E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Pos (5UL) /*!< DIRQ13E (Bit 5) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Msk (0x20UL) /*!< DIRQ13E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Pos (6UL) /*!< DIRQ14E (Bit 6) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Msk (0x40UL) /*!< DIRQ14E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Pos (7UL) /*!< DIRQ15E (Bit 7) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Msk (0x80UL) /*!< DIRQ15E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos (0UL) /*!< DIRQ0F (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk (0x1UL) /*!< DIRQ0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos (1UL) /*!< DIRQ1F (Bit 1) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk (0x2UL) /*!< DIRQ1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos (2UL) /*!< DIRQ2F (Bit 2) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk (0x4UL) /*!< DIRQ2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos (3UL) /*!< DIRQ3F (Bit 3) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk (0x8UL) /*!< DIRQ3F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos (4UL) /*!< DIRQ4F (Bit 4) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk (0x10UL) /*!< DIRQ4F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos (5UL) /*!< DIRQ5F (Bit 5) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk (0x20UL) /*!< DIRQ5F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos (6UL) /*!< DIRQ6F (Bit 6) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk (0x40UL) /*!< DIRQ6F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos (7UL) /*!< DIRQ7F (Bit 7) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk (0x80UL) /*!< DIRQ7F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos (0UL) /*!< DIRQ8F (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk (0x1UL) /*!< DIRQ8F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos (1UL) /*!< DIRQ9F (Bit 1) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk (0x2UL) /*!< DIRQ9F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos (2UL) /*!< DIRQ10F (Bit 2) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk (0x4UL) /*!< DIRQ10F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos (3UL) /*!< DIRQ11F (Bit 3) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk (0x8UL) /*!< DIRQ11F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos (4UL) /*!< DIRQ12F (Bit 4) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk (0x10UL) /*!< DIRQ12F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos (5UL) /*!< DIRQ13F (Bit 5) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk (0x20UL) /*!< DIRQ13F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos (6UL) /*!< DIRQ14F (Bit 6) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk (0x40UL) /*!< DIRQ14F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos (7UL) /*!< DIRQ15F (Bit 7) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk (0x80UL) /*!< DIRQ15F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos (0UL) /*!< DIRQ0EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk (0x1UL) /*!< DIRQ0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos (1UL) /*!< DIRQ1EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk (0x2UL) /*!< DIRQ1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos (2UL) /*!< DIRQ2EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk (0x4UL) /*!< DIRQ2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos (3UL) /*!< DIRQ3EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk (0x8UL) /*!< DIRQ3EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos (4UL) /*!< DIRQ4EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk (0x10UL) /*!< DIRQ4EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos (5UL) /*!< DIRQ5EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk (0x20UL) /*!< DIRQ5EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos (6UL) /*!< DIRQ6EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk (0x40UL) /*!< DIRQ6EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos (7UL) /*!< DIRQ7EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk (0x80UL) /*!< DIRQ7EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos (0UL) /*!< DIRQ8EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk (0x1UL) /*!< DIRQ8EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos (1UL) /*!< DIRQ9EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk (0x2UL) /*!< DIRQ9EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos (2UL) /*!< DIRQ10EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk (0x4UL) /*!< DIRQ10EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos (3UL) /*!< DIRQ11EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk (0x8UL) /*!< DIRQ11EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos (4UL) /*!< DIRQ12EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk (0x10UL) /*!< DIRQ12EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos (5UL) /*!< DIRQ13EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk (0x20UL) /*!< DIRQ13EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos (6UL) /*!< DIRQ14EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk (0x40UL) /*!< DIRQ14EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos (7UL) /*!< DIRQ15EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk (0x80UL) /*!< DIRQ15EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos (0UL) /*!< DPVD1EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk (0x1UL) /*!< DPVD1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos (1UL) /*!< DPVD2EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk (0x2UL) /*!< DPVD2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Pos (4UL) /*!< LVD3RF (Bit 4) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Msk (0x10UL) /*!< LVD3RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x1fUL) /*!< LVD2LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS1FR_Pos (0UL) /*!< SS1FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS1FR_Msk (0x1UL) /*!< SS1FR (Bitfield-Mask: 0x01) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos (4UL) /*!< CLUP0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk (0x10UL) /*!< CLUP0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos (4UL) /*!< CLUP1MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk (0x10UL) /*!< CLUP1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk (0x80UL) /*!< NWMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos (0UL) /*!< LVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk (0x1UL) /*!< LVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos (1UL) /*!< LVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk (0x2UL) /*!< LVD2MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos (2UL) /*!< LVD3MASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk (0x4UL) /*!< LVD3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos (3UL) /*!< LVD4MASK (Bit 3) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk (0x8UL) /*!< LVD4MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos (4UL) /*!< LVD5MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk (0x10UL) /*!< LVD5MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR0 ======================================================== */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR1 ======================================================== */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR2 ======================================================== */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR3 ======================================================== */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR4 ======================================================== */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR5 ======================================================== */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR6 ======================================================== */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR7 ======================================================== */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR8 ======================================================== */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR9 ======================================================== */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR10 ======================================================== */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR11 ======================================================== */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR12 ======================================================== */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR13 ======================================================== */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR14 ======================================================== */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR15 ======================================================== */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR16 ======================================================== */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR17 ======================================================== */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR18 ======================================================== */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR19 ======================================================== */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR20 ======================================================== */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR21 ======================================================== */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR22 ======================================================== */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR23 ======================================================== */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR24 ======================================================== */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR25 ======================================================== */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR26 ======================================================== */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR27 ======================================================== */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR28 ======================================================== */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR29 ======================================================== */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR30 ======================================================== */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR31 ======================================================== */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR32 ======================================================== */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR33 ======================================================== */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR34 ======================================================== */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR35 ======================================================== */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR36 ======================================================== */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR37 ======================================================== */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR38 ======================================================== */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR39 ======================================================== */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR40 ======================================================== */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR41 ======================================================== */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR42 ======================================================== */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR43 ======================================================== */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR44 ======================================================== */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR45 ======================================================== */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR46 ======================================================== */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR47 ======================================================== */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR48 ======================================================== */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR49 ======================================================== */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR50 ======================================================== */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR51 ======================================================== */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR52 ======================================================== */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR53 ======================================================== */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR54 ======================================================== */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR55 ======================================================== */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR56 ======================================================== */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR57 ======================================================== */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR58 ======================================================== */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR59 ======================================================== */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR60 ======================================================== */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR61 ======================================================== */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR62 ======================================================== */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR63 ======================================================== */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR64 ======================================================== */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR65 ======================================================== */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR66 ======================================================== */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR67 ======================================================== */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR68 ======================================================== */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR69 ======================================================== */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR70 ======================================================== */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR71 ======================================================== */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR72 ======================================================== */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR73 ======================================================== */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR74 ======================================================== */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR75 ======================================================== */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR76 ======================================================== */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR77 ======================================================== */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR78 ======================================================== */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR79 ======================================================== */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR80 ======================================================== */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR81 ======================================================== */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR82 ======================================================== */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR83 ======================================================== */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR84 ======================================================== */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR85 ======================================================== */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR86 ======================================================== */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR87 ======================================================== */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR88 ======================================================== */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR89 ======================================================== */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR90 ======================================================== */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR91 ======================================================== */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR92 ======================================================== */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR93 ======================================================== */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR94 ======================================================== */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR95 ======================================================== */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR96 ======================================================== */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR97 ======================================================== */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR98 ======================================================== */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR99 ======================================================== */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR100 ======================================================= */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR101 ======================================================= */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR102 ======================================================= */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR103 ======================================================= */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR104 ======================================================= */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR105 ======================================================= */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR106 ======================================================= */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR107 ======================================================= */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR108 ======================================================= */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR109 ======================================================= */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR110 ======================================================= */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR111 ======================================================= */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR112 ======================================================= */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR113 ======================================================= */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR114 ======================================================= */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR115 ======================================================= */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR116 ======================================================= */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR117 ======================================================= */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR118 ======================================================= */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR119 ======================================================= */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR120 ======================================================= */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR121 ======================================================= */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR122 ======================================================= */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR123 ======================================================= */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR124 ======================================================= */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR125 ======================================================= */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR126 ======================================================= */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR127 ======================================================= */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLCTRL0 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos (0UL) /*!< FSBLEN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk (0x7UL) /*!< FSBLEN (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos (3UL) /*!< FSBLSKIPSW (Bit 3) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk (0x38UL) /*!< FSBLSKIPSW (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos (6UL) /*!< FSBLSKIPDS (Bit 6) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos (9UL) /*!< FSBLCLK (Bit 9) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= FSBLCTRL1 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos (0UL) /*!< FSBLEXMD (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk (0x3UL) /*!< FSBLEXMD (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLCTRL2 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos (0UL) /*!< PORTPN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk (0xfUL) /*!< PORTPN (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos (4UL) /*!< PORTGN (Bit 4) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f) */ +/* ========================================================= SACC0 ========================================================= */ +/* ========================================================= SACC1 ========================================================= */ +/* ========================================================= SAMR ========================================================== */ +/* ======================================================= HOEMRTPK ======================================================== */ +/* ========================================================= ARCLS ========================================================= */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos (0UL) /*!< ARCS_LK (Bit 0) */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk (0x1UL) /*!< ARCS_LK (Bitfield-Mask: 0x01) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos (1UL) /*!< ARCNS_LK (Bit 1) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk (0x1eUL) /*!< ARCNS_LK (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos (5UL) /*!< ARCBL_LK (Bit 5) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk (0x20UL) /*!< ARCBL_LK (Bitfield-Mask: 0x01) */ +/* ========================================================= ARCCS ========================================================= */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos (0UL) /*!< CNF_ARCNS (Bit 0) */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk (0x3UL) /*!< CNF_ARCNS (Bitfield-Mask: 0x03) */ +/* ======================================================== ARC_SEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos (0UL) /*!< ARC_SEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_NSEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos (0UL) /*!< ARC_NSEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_OEMBL ======================================================= */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos (0UL) /*!< ARC_OEMBL (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA8M1AH_H */ + +/** @} */ /* End of group R7FA8M1AH */ + +/** @} */ /* End of group Renesas */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h index cf586331f..f8083574f 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -39,8 +39,19 @@ extern "C" { #endif +/* Workaround for LLVM. __ARM_ARCH_8_1M_MAIN__ is defined for CM85 parts. But CMSIS_5 does not support this */ + #if defined(__llvm__) && !defined(__CLANG_TIDY__) && defined(__ARM_ARCH_8_1M_MAIN__) + #undef __ARM_ARCH_8_1M_MAIN__ + #define __ARM_ARCH_8M_MAIN__ 1 + #endif #include "cmsis_compiler.h" +/* Workaround for compilers that are not defining __ARM_ARCH_8_1M_MAIN__ for CM85 parts. */ + #if BSP_CFG_MCU_PART_SERIES == 8 + #undef __ARM_ARCH_8M_MAIN__ + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif + /** @addtogroup Configuration_of_CMSIS * @{ */ @@ -48,7 +59,7 @@ extern "C" { /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ -/* IRQn_Type is provided in bsp_arm_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ +/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -62,6 +73,8 @@ extern "C" { #include "R7FA2E1A9.h" #elif BSP_MCU_GROUP_RA2E2 #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2E3 + #include "R7FA2E307.h" #elif BSP_MCU_GROUP_RA2L1 #include "R7FA2L1AB.h" #elif BSP_MCU_GROUP_RA4E1 @@ -98,6 +111,8 @@ extern "C" { #include "R7FA6T2BD.h" #elif BSP_MCU_GROUP_RA6T3 #include "R7FA6T3BB.h" + #elif BSP_MCU_GROUP_RA8M1 + #include "R7FA8M1AH.h" #else #if __has_include("renesas_internal.h") #include "renesas_internal.h" diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index e1dfa0bc0..7caf7e3a9 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -27,6 +27,9 @@ * Includes , "Project Includes" **********************************************************************************************************************/ #include +#if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__) + #include +#endif #include "bsp_api.h" /*********************************************************************************************************************** @@ -50,6 +53,8 @@ #define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0]) #define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5) +#define ARMV8_MPU_REGION_MIN_SIZE (32U) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -81,6 +86,12 @@ extern uint32_t Image$$DTCM_DATA$$Base; extern uint32_t Image$$DTCM_BSS$$Base; extern uint32_t Image$$DTCM_BSS_PAD$$ZI$$Limit; #endif + #if BSP_CFG_DCACHE_ENABLED +extern uint32_t Image$$NOCACHE$$ZI$$Base; +extern uint32_t Image$$NOCACHE_PAD$$ZI$$Limit; +extern uint32_t Image$$NOCACHE_SDRAM$$ZI$$Base; +extern uint32_t Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit; + #endif #elif defined(__GNUC__) /* Generated by linker. */ @@ -91,6 +102,11 @@ extern uint32_t __bss_start__; extern uint32_t __bss_end__; extern uint32_t __StackLimit; extern uint32_t __StackTop; + +/* Nested in __GNUC__ because LLVM generates both __GNUC__ and __llvm__*/ + #if defined(__llvm__) && !defined(__CLANG_TIDY__) +extern uint32_t __tls_base; + #endif #if BSP_FEATURE_BSP_HAS_ITCM extern uint32_t __itcm_data_init_start; extern uint32_t __itcm_data_init_end; @@ -103,6 +119,12 @@ extern uint32_t __dtcm_data_start; extern uint32_t __dtcm_bss_start; extern uint32_t __dtcm_bss_end; #endif + #if BSP_CFG_DCACHE_ENABLED +extern uint32_t __nocache_start; +extern uint32_t __nocache_end; +extern uint32_t __nocache_sdram_start; +extern uint32_t __nocache_sdram_end; + #endif #elif defined(__ICCARM__) #pragma section=".bss" #pragma section=".data" @@ -120,6 +142,12 @@ extern uint32_t DTCM_DATA$$Base; extern uint32_t DTCM_BSS$$Base; extern uint32_t DTCM_BSS$$Limit; #endif + #if BSP_CFG_DCACHE_ENABLED +extern uint32_t NOCACHE$$Base; +extern uint32_t NOCACHE$$Limit; +extern uint32_t NOCACHE_SDRAM$$Base; +extern uint32_t NOCACHE_SDRAM$$Limit; + #endif #endif /* Initialize static constructors */ @@ -190,6 +218,11 @@ static void bsp_init_dtcm(void); #endif #endif +#if BSP_CFG_DCACHE_ENABLED +static void bsp_init_mpu(void); + +#endif + /*******************************************************************************************************************//** * Initialize the MCU and the runtime environment. **********************************************************************************************************************/ @@ -197,8 +230,9 @@ void SystemInit (void) { #if defined(RENESAS_CORTEX_M85) - /* Enable the ARM core instruction cache, branch prediction and low-overhead-branch extension. - * See Section 5.5 of the Cortex-M55 TRM and Section D1.2.9 in the ARMv8-M Architecture Reference Manual */ + /* Enable the instruction cache, branch prediction, and the branch cache (required for Low Overhead Branch (LOB) extension). + * See sections 6.5, 6.6, and 6.7 in the Arm Cortex-M85 Processor Technical Reference Manual (Document ID: 101924_0002_05_en, Issue: 05) + * See section D1.2.9 in the Armv8-M Architecture Reference Manual (Document number: DDI0553B.w, Document version: ID07072023) */ SCB->CCR = (uint32_t) CCR_CACHE_ENABLE; __DSB(); __ISB(); @@ -223,6 +257,9 @@ void SystemInit (void) #endif #if !BSP_TZ_NONSECURE_BUILD + #if BSP_FEATURE_BSP_SECURITY_PREINIT + R_BSP_SecurityPreinit(); + #endif /* VTOR is in undefined state out of RESET: * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en. @@ -306,14 +343,7 @@ void SystemInit (void) #endif #if BSP_FEATURE_TZ_HAS_TRUSTZONE - #if 33U == __CORTEX_M - - /* Use CM33 stack monitor. */ __set_MSPLIM(BSP_PRV_STACK_LIMIT); - #else - - /* CM85 stack monitor not yet supported. */ - #endif #endif #if BSP_CFG_C_RUNTIME_INIT @@ -359,6 +389,19 @@ void SystemInit (void) bsp_init_dtcm(); #endif + #if defined(RENESAS_CORTEX_M85) + + /* Invalidate I-Cache after initializing the .code_in_ram section. */ + SCB_InvalidateICache(); + #endif + + #if defined(__GNUC__) && defined(__llvm__) && !defined(__CLANG_TIDY__) && !(defined __ARMCC_VERSION) + + /* Initialize TLS memory. */ + _init_tls(&__tls_base); + _set_tls(&__tls_base); + #endif + /* Initialize static constructors */ #if defined(__ARMCC_VERSION) int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base; @@ -383,21 +426,25 @@ void SystemInit (void) #endif #endif // BSP_CFG_C_RUNTIME_INIT +#if BSP_FEATURE_BSP_POST_CRUNTIME_INIT + R_BSP_PostCRuntimeInit(); +#endif + /* Initialize SystemCoreClock variable. */ SystemCoreClockUpdate(); #if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */ - #if !BSP_TZ_NONSECURE_BUILD + #if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE /* Perform RTC reset sequence to avoid unintended operation. */ R_BSP_Init_RTC(); #endif #endif -#if !BSP_CFG_PFS_PROTECT - #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8) +#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC) + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled #else @@ -408,12 +455,16 @@ void SystemInit (void) #if FSP_PRIV_TZ_USE_SECURE_REGS - /* Ensure that the PMSAR registers are reset (Soft reset does not reset PMSAR). */ + /* Ensure that the PMSAR registers are set to their default value. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); - for (uint32_t i = 0; i < 9; i++) + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) { + #if BSP_FEATURE_TZ_VERSION == 2 + R_PMISC->PMSAR[i].PMSAR = 0U; + #else R_PMISC->PMSAR[i].PMSAR = UINT16_MAX; + #endif } R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); #endif @@ -424,16 +475,25 @@ void SystemInit (void) R_BSP_SecurityInit(); #endif -#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN +#if BSP_CFG_DCACHE_ENABLED + bsp_init_mpu(); - /* Turn on graphics power domain. - * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ - R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); - FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), - R_SYSTEM_PDCTRGD_PDPGSF_Msk); - R_SYSTEM->PDCTRGD = 0; - FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0); - R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + SCB_EnableDCache(); +#endif + +#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN + if ((((0 == R_SYSTEM->PGCSAR) && FSP_PRIV_TZ_USE_SECURE_REGS) || + ((1 == R_SYSTEM->PGCSAR) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD)) + { + /* Turn on graphics power domain. + * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + R_SYSTEM_PDCTRGD_PDPGSF_Msk); + R_SYSTEM->PDCTRGD = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } #endif /* Call Post C runtime initialization hook. */ @@ -695,4 +755,91 @@ static void bsp_init_dtcm (void) #endif +#if BSP_CFG_DCACHE_ENABLED + +/*******************************************************************************************************************//** + * Initialize MPU for Armv8-M devices. + **********************************************************************************************************************/ +static void bsp_init_mpu (void) +{ + uint32_t nocache_start; + uint32_t nocache_end; + uint32_t nocache_sdram_start; + uint32_t nocache_sdram_end; + + #if defined(__ARMCC_VERSION) + nocache_start = (uint32_t) &Image$$NOCACHE$$ZI$$Base; + nocache_end = (uint32_t) &Image$$NOCACHE_PAD$$ZI$$Limit; + nocache_sdram_start = (uint32_t) &Image$$NOCACHE_SDRAM$$ZI$$Base; + nocache_sdram_end = (uint32_t) &Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit; + #elif defined(__GNUC__) + nocache_start = (uint32_t) &__nocache_start; + nocache_end = (uint32_t) &__nocache_end; + nocache_sdram_start = (uint32_t) &__nocache_sdram_start; + nocache_sdram_end = (uint32_t) &__nocache_sdram_end; + #elif defined(__ICCARM__) + nocache_start = (uint32_t) &NOCACHE$$Base; + nocache_end = (uint32_t) &NOCACHE$$Limit; + nocache_sdram_start = (uint32_t) &NOCACHE_SDRAM$$Base; + nocache_sdram_end = (uint32_t) &NOCACHE_SDRAM$$Limit; + #endif + + /* Maximum of eight attributes. */ + const uint8_t bsp_mpu_mair_attributes[] = + { + /* Normal, Non-cacheable */ + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE) + }; + + /* Maximum of eight regions. */ + /* A region start address and end address must each be aligned to 32 bytes. A region must be a minimum of 32 bytes to be valid. */ + /* A region end address is inclusive. */ + const ARM_MPU_Region_t bsp_mpu_regions[] = + { + /* No-Cache Section */ + { + .RBAR = ARM_MPU_RBAR(nocache_start, ARM_MPU_SH_NON, 0U, 0U, 1U), + .RLAR = ARM_MPU_RLAR((nocache_end - ARMV8_MPU_REGION_MIN_SIZE), 0U) + }, + + /* SDRAM No-Cache Section */ + { + .RBAR = ARM_MPU_RBAR(nocache_sdram_start, ARM_MPU_SH_NON, 0U, 0U, 1U), + .RLAR = ARM_MPU_RLAR((nocache_sdram_end - ARMV8_MPU_REGION_MIN_SIZE), 0U) + } + }; + + /* Initialize MPU_MAIR0 and MPU_MAIR1 from attributes table. */ + uint8_t num_attr = (sizeof(bsp_mpu_mair_attributes) / sizeof(bsp_mpu_mair_attributes[0])); + for (uint8_t i = 0; i < num_attr; i++) + { + ARM_MPU_SetMemAttr(i, bsp_mpu_mair_attributes[i]); + } + + /* Initialize MPU from configuration table. */ + uint8_t num_regions = (sizeof(bsp_mpu_regions) / sizeof(bsp_mpu_regions[0])); + for (uint8_t i = 0; i < num_regions; i++) + { + uint32_t rbar = bsp_mpu_regions[i].RBAR; + uint32_t rlar = bsp_mpu_regions[i].RLAR; + + /* Only configure regions of non-zero size. */ + if ((((rlar & MPU_RLAR_LIMIT_Msk) >> MPU_RLAR_LIMIT_Pos) + ARMV8_MPU_REGION_MIN_SIZE) > + ((rbar & MPU_RBAR_BASE_Msk) >> MPU_RBAR_BASE_Pos)) + { + ARM_MPU_SetRegion(i, rbar, rlar); + } + } + + /* + * SHCSR.MEMFAULTENA is set inside ARM_MPU_Enable(). + * Leave SHPR1.PRI_4 at reset value of zero. + * Leave MPU_CTRL.HFNMIENA at reset value of zero. + * Provide MPU_CTRL_PRIVDEFENA_Msk to ARM_MPU_Enable() to set MPU_CTRL.PRIVDEFENA. + */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); +} + +#endif + /** @} (end addtogroup BSP_MCU) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index bcc2d98ec..ff9144daf 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -522,6 +522,7 @@ **********************************************************************************************************************/ static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz); static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state); +static void bsp_sosc_init(void); #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED #if defined(__ICCARM__) @@ -616,7 +617,7 @@ void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callb r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); } -#elif BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU +#elif BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 bsp_clock_update_callback_args_t g_callback_memory; #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD @@ -781,11 +782,21 @@ void bsp_prv_prepare_pll (uint32_t pll_freq_hz) **********************************************************************************************************************/ void SystemCoreClockUpdate (void) { - uint32_t clock_index = R_SYSTEM->SCKSCR; +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 + bool secure = !R_SYSTEM->CGFSAR_b.NONSEC00; +#endif + + uint32_t clock_index = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKSCR, secure); + #if !BSP_FEATURE_CGC_HAS_CPUCLK - SystemCoreClock = g_clock_freq[clock_index] >> R_SYSTEM->SCKDIVCR_b.ICK; + uint32_t ick = + (FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, secure) & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; + SystemCoreClock = g_clock_freq[clock_index] >> ick; #else - uint8_t cpuclk_div = R_SYSTEM->SCKDIVCR2_b.CPUCK; + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK_Pos; + uint8_t cpuclk_div = cpuck; + if (8U == cpuclk_div) { SystemCoreClock = g_clock_freq[clock_index] / 3U; @@ -942,6 +953,52 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) /* Switching to a faster source clock. */ if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR]) { +#if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + if ((clock_freq_hz_post_change > SystemCoreClock) && + ((clock_freq_hz_post_change - SystemCoreClock) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + if (iclk_div == sckdivcr2) + { + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + uint32_t new_div = BSP_CLOCKS_SYS_CLOCK_DIV_2; + if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + new_div = BSP_CLOCKS_SYS_CLOCK_DIV_4; + } + + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + } + else + { + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + if (BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = + (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + else + { + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + } + } + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + /* Continue and set clock to actual target speed. */ +#endif + /* Set the clock dividers before switching to the new clock source. */ prv_clock_dividers_set(sckdivcr, sckdivcr2); @@ -951,6 +1008,36 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) /* Switching to a slower source clock. */ else { +#if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + if ((SystemCoreClock > clock_freq_hz_post_change) && + ((SystemCoreClock - clock_freq_hz_post_change) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + uint32_t current_sckdivcr = R_SYSTEM->SCKDIVCR; + + /* Must first step CPUCLK down by factor of 2 or 3 if it is currently above threshold. */ + if (R_SYSTEM->SCKDIVCR2 == ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) + { + /* If ICLK and CPUCLK have same divider currently, move ICLK down 1 notch first. */ + uint32_t current_iclk_div = (current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF; + uint32_t new_div = current_iclk_div + 1; + if (current_iclk_div == 0) + { + /* Align with already selected divider for PCLKA because it must have one > 1 already. */ + new_div = + (current_sckdivcr & + (0x8 << R_SYSTEM_SCKDIVCR_PCKA_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + R_SYSTEM->SCKDIVCR = (current_sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + + SystemCoreClockUpdate(); + } + } + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); +#endif R_SYSTEM->SCKSCR = (uint8_t) clock; /* Set the clock dividers after switching to the new clock source. */ @@ -988,6 +1075,46 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2) #endif } +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE + +bool bsp_prv_clock_prepare_pre_sleep (void) +{ + /* Must wait before entering or exiting sleep modes. + * See Section 10.7.10 in RA8M1 manual R01UH0994EJ0100 */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Need to slow CPUCLK down before sleeping if it is above 240MHz. */ + bool cpuclk_slowed = false; + if (SystemCoreClock > BSP_MAX_CLOCK_CHANGE_THRESHOLD) + { + /* Reduce speed of CPUCLK to /2 or /3 of current, select which ones based on what ICLK divider is. */ + R_SYSTEM->SCKDIVCR2 = + (R_SYSTEM->SCKDIVCR & + (0x8 << R_SYSTEM_SCKDIVCR_ICK_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + cpuclk_slowed = true; + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + + return cpuclk_slowed; +} + +void bsp_prv_clock_prepare_post_sleep (bool cpuclk_slowed) +{ + /* Set CPUCLK back to original speed here if it was slowed down before sleeping (dropped to below 240MHz) + * Add delays as described in Section 10.7.10 of RA8M1 manual R01UH0994EJ0100 */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + if (cpuclk_slowed) + { + /* Set divider of CPUCLK back to /1. This is the only possible value for it to have been over 240MHz before sleeping. */ + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_1; + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } +} + +#endif + #if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET static void bsp_prv_clock_set_hard_reset (void) @@ -1039,18 +1166,60 @@ static void bsp_prv_clock_set_hard_reset (void) * then set the clock dividers before switching to the new source clock. */ #if BSP_MOCO_FREQ_HZ <= BSP_STARTUP_SOURCE_CLOCK_HZ #if BSP_FEATURE_CGC_HAS_CPUCLK - #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && (BSP_STARTUP_CPUCLK_HZ >= BSP_MAX_CLOCK_CHANGE_THRESHOLD) /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ - R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV + + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_4; + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + #endif + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Continue and set clock to actual target speed. */ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; #else + #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + #else /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif #endif #else R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; @@ -1098,7 +1267,8 @@ static void bsp_prv_clock_set_hard_reset (void) #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; - /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */ + /* Execute data memory barrier before and after setting the wait states, See Section 50.4.2 in the RA8M1 + * manual R01UH0994EJ0100 */ __DMB(); R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; __DMB(); @@ -1153,7 +1323,7 @@ static void bsp_clock_freq_var_init (void) #endif #endif -#if BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU +#if BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */ R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory); @@ -1342,7 +1512,11 @@ void bsp_soft_reset_prepare (void) void bsp_clock_init (void) { /* Unlock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#else R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#endif #if BSP_FEATURE_BSP_FLASH_CACHE #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM @@ -1398,56 +1572,8 @@ void bsp_clock_init (void) #endif #endif -#if BSP_FEATURE_CGC_HAS_SOSC - #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED - if (R_SYSTEM->SOSCCR || (BSP_CLOCK_CFG_SUBCLOCK_DRIVE != R_SYSTEM->SOMCR_b.SODRV)) - { - /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ - if (0U == R_SYSTEM->SOSCCR) - { - /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ - R_SYSTEM->SOSCCR = 1U; - - /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity - * and restarting Sub-Clock Oscillator. */ - R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); - - /* - * r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: - * When changing the value of the SOSTP bit, execute subsequent instructions - * only after reading the bit to check that the value is updated. - */ - FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); - } - - /* Configure the subclock drive as subclock is not running. */ - R_SYSTEM->SOMCR = ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); - - R_SYSTEM->SOSCCR = 0U; - - /* r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: - * After setting the SOSTP bit to 0, use the sub-clock only after the sub-clock - * oscillation stabilization time has elapsed. - */ - #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) - R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); - #endif - } - else - { - /* - * RA MCUs like RA6M5 requires to use sub-clock after oscillation stabilization time - * has elapsed on Power-On-Reset. But, POR is not well supported on EK boards, so BSP - * has to wait on any reset. Please override this function in application if waiting - * for stabilization is not required. - */ - R_BSP_SubClockStabilizeWaitAfterReset(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); - } - - #else - R_SYSTEM->SOSCCR = 1U; - #endif -#endif + /* Initialize the sub-clock according to the BSP configuration. */ + bsp_sosc_init(); #if BSP_FEATURE_CGC_HAS_HOCOWTCR #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY @@ -1802,13 +1928,24 @@ void bsp_clock_init (void) /* Set the SDADC clock if it exists on the MCU. */ #if BSP_FEATURE_BSP_HAS_SDADC_CLOCK && (BSP_CFG_SDADC_CLOCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + #if BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO + uint8_t sdadcckcr = 1U; + #elif BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL + uint8_t sdadcckcr = 2U; + #else /* BSP_CLOCK_SOURCE_CLOCK_MOSC */ + uint8_t sdadcckcr = 0U; + #endif /* SDADC isn't controlled like the other peripheral clocks so we cannot use the generic setter. */ - R_SYSTEM->SDADCCKCR = BSP_CFG_SDADC_CLOCK_SOURCE & R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk; + R_SYSTEM->SDADCCKCR = sdadcckcr & R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk; #endif /* Lock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_LOCK; +#else R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#endif #if BSP_FEATURE_BSP_FLASH_CACHE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM R_BSP_FlashCacheEnable(); @@ -1923,7 +2060,8 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; - /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */ + /* Execute data memory barrier before and after setting the wait states, See Section 50.4.2 in the RA8M1 + * manual R01UH0994EJ0100 */ __DMB(); R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; __DMB(); @@ -2079,7 +2217,8 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_ #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; - /* Execute data memory barrier before and after setting the wait states (MREF_INTERNAL_000). */ + /* Execute data memory barrier before and after setting the wait states,See Section 50.4.2 in the RA8M1 + * manual R01UH0994EJ0100*/ __DMB(); R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; __DMB(); @@ -2111,6 +2250,77 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_ #endif } +/*******************************************************************************************************************//** + * Initializes sub-clock according to the BSP configuration. + **********************************************************************************************************************/ +static void bsp_sosc_init (void) +{ +#if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #if BSP_FEATURE_RTC_IS_IRTC + #if ((BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)) + + /* If sub-clock is used as system clock source or HOCO FLL source, wait for VRTC-domain become valid */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VRTSR_b.VRTVLD, 1); + #else + + /* Check if VRTC-domain area is valid. */ + if (1U == R_SYSTEM->VRTSR_b.VRTVLD) + #endif + #endif + { + if (R_SYSTEM->SOSCCR || (BSP_CLOCK_CFG_SUBCLOCK_DRIVE != R_SYSTEM->SOMCR_b.SODRV)) + { + /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity + * and restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* + * r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: + * When changing the value of the SOSTP bit, execute subsequent instructions + * only after reading the bit to check that the value is updated. + */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } + + /* Configure the subclock drive as subclock is not running. */ + R_SYSTEM->SOMCR = + ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); + + R_SYSTEM->SOSCCR = 0U; + + /* r01uh0893ej0120-ra4m3 8.2.9 SOSCCR : Sub-Clock Oscillator Control Register: + * After setting the SOSTP bit to 0, use the sub-clock only after the sub-clock + * oscillation stabilization time has elapsed. + */ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + #endif + } + else + { + /* + * RA MCUs like RA6M5 requires to use sub-clock after oscillation stabilization time + * has elapsed on Power-On-Reset. But, POR is not well supported on EK boards, so BSP + * has to wait on any reset. Please override this function in application if waiting + * for stabilization is not required. + */ + R_BSP_SubClockStabilizeWaitAfterReset(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + } + } + + #else + R_SYSTEM->SOSCCR = 1U; + #endif +#endif +} + /*******************************************************************************************************************//** * Octa-SPI clock update. * @param[in] p_octaclk_setting Pointer to Octaclk setting structure which provides information regarding @@ -2122,10 +2332,18 @@ void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting) #if BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK /* Store initial value of CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR_NS; + #else uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR; + #endif /* Unlock CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #else R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #endif /* Request to change the OCTASPI Clock. */ R_SYSTEM->OCTACKCR_b.OCTACKSREQ = 1; @@ -2144,7 +2362,11 @@ void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting) FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U); /* Restore CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = bsp_prv_prcr_orig; + #else R_SYSTEM->PRCR = bsp_prv_prcr_orig; + #endif #else FSP_PARAMETER_NOT_USED(p_octaclk_setting); #endif @@ -2179,6 +2401,14 @@ void R_BSP_Init_RTC (void) /* RCKSEL bit is not initialized after reset. Use LOCO as the default * clock source if it is available. Note RCR4.ROPSEL is also cleared. */ + + #if BSP_FEATURE_RTC_IS_IRTC + if (0U == R_SYSTEM->VRTSR_b.VRTVLD) // Return if VRTC-domain is invalid + { + return; + } + #endif + #if BSP_PRV_LOCO_USED && !BSP_FEATURE_RTC_IS_IRTC R_RTC->RCR4 = 1 << R_RTC_RCR4_RCKSEL_Pos; #else @@ -2228,4 +2458,56 @@ void R_BSP_Init_RTC (void) #endif +#if BSP_FEATURE_RTC_IS_IRTC + +/*******************************************************************************************************************//** + * To check sub-clock status. + * + * @retval FSP_SUCCESS Sub-clock is ready to use. + * @retval FSP_ERR_INVALID_HW_CONDITION VRTC-domain area is invalid. + * @retval FSP_ERR_NOT_INITIALIZED Sub-clock has not been inititalized yet. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockStatusGet () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is invalid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + /* Check if SOSC has been configured */ + if ((0U == R_SYSTEM->SOSCCR) && (BSP_CLOCK_CFG_SUBCLOCK_DRIVE == R_SYSTEM->SOMCR_b.SODRV)) + { + return FSP_SUCCESS; + } + #endif + + return FSP_ERR_NOT_INITIALIZED; +} + +/*******************************************************************************************************************//** + * To initialize the sub-clock. + * + * @retval FSP_SUCCESS Sub-clock successfully initialized. + * @retval FSP_ERR_INVALID_HW_CONDITION Sub-clock cannot be initialized. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockInitialize () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is valid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + bsp_sosc_init(); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + return FSP_SUCCESS; + #else + + return FSP_ERR_INVALID_HW_CONDITION; + #endif +} + +#endif + /** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index 2ac5d8c9d..9d3f7cf29 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -1107,6 +1107,19 @@ void R_BSP_Init_RTC(void); #endif +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE +bool bsp_prv_clock_prepare_pre_sleep(void); +void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); + +#endif + +/* The public function is used to get state or initialize the sub-clock. */ +#if BSP_FEATURE_RTC_IS_IRTC +fsp_err_t R_BSP_SubclockStatusGet(); +fsp_err_t R_BSP_SubclockInitialize(); + +#endif + /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.c b/ra/fsp/src/bsp/mcu/all/bsp_common.c index a7121a54e..374b57196 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_common.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_common.c @@ -66,6 +66,12 @@ void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_AT void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function +#endif +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 +static bool bsp_valid_register_check(uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length); + #endif /*********************************************************************************************************************** @@ -141,6 +147,101 @@ void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) #endif +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Read a secure 8-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR2, + (uint32_t) &R_SYSTEM->SCKSCR, + (uint32_t) &R_SYSTEM->SPICKDIVCR, + (uint32_t) &R_SYSTEM->SPICKCR, + (uint32_t) &R_SYSTEM->SCICKDIVCR, + (uint32_t) &R_SYSTEM->SCICKCR, + (uint32_t) &R_SYSTEM->CANFDCKCR, + (uint32_t) &R_SYSTEM->PLLCR, + (uint32_t) &R_SYSTEM->PLL2CR, + (uint32_t) &R_SYSTEM->MOCOCR, + (uint32_t) &R_SYSTEM->OPCCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 16-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_DTC->DTCSTS, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 32-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +#endif + /** @} (end addtogroup BSP_MCU) */ /*******************************************************************************************************************//** @@ -196,3 +297,29 @@ BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * #endif #endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Check if a register address should be accessible by the non-secure application. + **********************************************************************************************************************/ +static bool bsp_valid_register_check (uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length) +{ + bool valid = false; + + /* Check if the given address is valid. */ + for (uint32_t i = 0; i < register_table_length; i++) + { + if (p_register_table[i] == register_address) + { + valid = true; + break; + } + } + + return valid; +} + +#endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.h b/ra/fsp/src/bsp/mcu/all/bsp_common.h index be663396e..b42e0acba 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_common.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -35,6 +35,10 @@ /* Different compiler support. */ #include "../../inc/api/fsp_common_api.h" #include "bsp_compiler_support.h" + +/* BSP TFU Includes. */ +#include "../../src/bsp/mcu/all/bsp_tfu.h" + #include "bsp_cfg.h" /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ @@ -57,6 +61,7 @@ FSP_HEADER #if 1 == BSP_CFG_RTOS /* ThreadX */ #include "tx_user.h" #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) + #include "tx_api.h" #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); #else @@ -194,7 +199,7 @@ FSP_HEADER #endif /* Use the secure registers for secure projects and flat projects. */ -#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE && !(BSP_CFG_MCU_PART_SERIES == 8) +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE #define FSP_PRIV_TZ_USE_SECURE_REGS (1) #else #define FSP_PRIV_TZ_USE_SECURE_REGS (0) @@ -207,6 +212,79 @@ FSP_HEADER #define BSP_SECTION_EARLY_INIT #endif +#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); + +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/* + * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register + * from the secure application using the provided non-secure callable functions. + */ + #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) + #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) + #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) +#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/*******************************************************************************************************************//** + * Read a non-secure 8-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 16-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 32-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/* + * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register + * using the non-secure aliased address. + */ + #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) + #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) + #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) +#else + #define FSP_STYPE3_REG8_READ(X, S) (X) + #define FSP_STYPE3_REG16_READ(X, S) (X) + #define FSP_STYPE3_REG32_READ(X, S) (X) +#endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -222,13 +300,15 @@ typedef enum e_bsp_warm_start_event /* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ typedef enum e_fsp_priv_clock { - FSP_PRIV_CLOCK_PCLKD = 0, - FSP_PRIV_CLOCK_PCLKC = 4, - FSP_PRIV_CLOCK_PCLKB = 8, - FSP_PRIV_CLOCK_PCLKA = 12, - FSP_PRIV_CLOCK_BCLK = 16, - FSP_PRIV_CLOCK_ICLK = 24, - FSP_PRIV_CLOCK_FCLK = 28, + FSP_PRIV_CLOCK_PCLKD = 0, + FSP_PRIV_CLOCK_PCLKC = 4, + FSP_PRIV_CLOCK_PCLKB = 8, + FSP_PRIV_CLOCK_PCLKA = 12, + FSP_PRIV_CLOCK_BCLK = 16, + FSP_PRIV_CLOCK_PCLKE = 20, + FSP_PRIV_CLOCK_ICLK = 24, + FSP_PRIV_CLOCK_FCLK = 28, + FSP_PRIV_CLOCK_CPUCLK = 32, } fsp_priv_clock_t; /* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ @@ -285,13 +365,17 @@ __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) **********************************************************************************************************************/ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) { - uint32_t sckdivcr = R_SYSTEM->SCKDIVCR; + uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; #if BSP_FEATURE_CGC_HAS_CPUCLK + if (FSP_PRIV_CLOCK_CPUCLK == clock) + { + return SystemCoreClock; + } /* Get CPUCLK divisor */ - uint32_t cpuclk_div = R_SYSTEM->SCKDIVCR2 & FSP_PRV_SCKDIVCR_DIV_MASK; + uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; /* Determine if either divisor is a multiple of 3 */ if ((cpuclk_div | clock_div) & 8U) @@ -307,6 +391,7 @@ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) { return (SystemCoreClock << cpuclk_div) >> clock_div; } + #else uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; @@ -323,6 +408,7 @@ __STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) { if (2U >= ckdivcr) { + /* clock_div: * - Clock Divided by 1: 0 * - Clock Divided by 2: 1 @@ -332,16 +418,19 @@ __STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) } else if (3U == ckdivcr) { + /* Clock Divided by 6 */ return 6U; } else if (4U == ckdivcr) { + /* Clock Divided by 8 */ return 8U; } else if (5U == ckdivcr) { + /* Clock Divided by 3 */ return 3U; } @@ -376,9 +465,12 @@ __STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) **********************************************************************************************************************/ __STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) { - uint32_t spidivcr = R_SYSTEM->SPICKDIVCR; + uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t spicksel = (fsp_priv_source_clock_t) R_SYSTEM->SPICKCR_b.CKSEL; + fsp_priv_source_clock_t spicksel = + (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> + R_SYSTEM_SPICKCR_CKSEL_Pos); return R_BSP_SourceClockHzGet(spicksel) / clock_div; } @@ -393,9 +485,12 @@ __STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) **********************************************************************************************************************/ __STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) { - uint32_t scidivcr = R_SYSTEM->SCICKDIVCR; + uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); - fsp_priv_source_clock_t scicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCICKCR_b.SCICKSEL; + fsp_priv_source_clock_t scicksel = + (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> + R_SYSTEM_SCICKCR_SCICKSEL_Pos); return R_BSP_SourceClockHzGet(scicksel) / clock_div; } diff --git a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h index a5159d0a3..43a316e18 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -45,7 +45,7 @@ extern "C" { #ifndef BSP_SECTION_HEAP #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" #endif - #define BSP_DONT_REMOVE + #define BSP_DONT_REMOVE __attribute__((used)) #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) #define BSP_FORCE_INLINE __attribute__((always_inline)) #elif defined(__GNUC__) /* GCC compiler */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/ra/fsp/src/bsp/mcu/all/bsp_delay.c index e51a06216..03768614d 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_delay.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_delay.c @@ -166,11 +166,12 @@ BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__( __asm volatile ( #if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__)) - /* Optimize inner loop execution time on CM85 cores (Alignment allows for instruction fusion). */ - ".align 8\n" + /* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */ + /* IAR does not support alignment control within inline assembly. */ + ".balign 8\n" #endif "sw_delay_loop: \n" -#if defined(__ICCARM__) || defined(__ARMCC_VERSION) +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__)) " subs r0, #1 \n" ///< 1 cycle #elif defined(__GNUC__) " sub r0, r0, #1 \n" ///< 1 cycle diff --git a/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h b/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h similarity index 98% rename from ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h rename to ra/fsp/src/bsp/mcu/all/bsp_exceptions.h index 14ce8f0a4..ef1dd59e6 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -20,8 +20,8 @@ /** @} (end addtogroup BSP_MCU) */ -#ifndef BSP_ARM_EXCEPTIONS_H - #define BSP_ARM_EXCEPTIONS_H +#ifndef BSP_EXCEPTIONS_H + #define BSP_EXCEPTIONS_H #ifdef __cplusplus extern "C" { diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c index 797f5c601..f94729092 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -102,7 +102,9 @@ fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_ir **********************************************************************************************************************/ void NMI_Handler (void) { - uint16_t nmisr = R_ICU->NMISR; + /* NMISR is masked by NMIER to prevent iterating over NMI status flags that are not enabled. */ + uint16_t nmier = R_ICU->NMIER; + uint16_t nmisr = R_ICU->NMISR & nmier; /* Loop over all NMI status flags */ for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_GRP_IRQ_TOTAL_ITEMS - 1); irq++) @@ -116,6 +118,14 @@ void NMI_Handler (void) /* Clear status flags that have been handled. */ R_ICU->NMICLR = nmisr; + +#if BSP_CFG_MCU_PART_SERIES == 8 + + /* Wait for NMISR to be cleared before exiting the ISR to prevent the IRQ from being regenerated. + * See section "13.2.12 NMICLR : Non-Maskable Interrupt Status Clear Register" in the RA8M1 manual + * R01UH0994EJ0100 */ + FSP_HARDWARE_REGISTER_WAIT((R_ICU->NMISR & nmisr), 0); +#endif } /** @} (end addtogroup BSP_MCU) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/ra/fsp/src/bsp/mcu/all/bsp_guard.c index d9b4df141..3c3ca2dc4 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_guard.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_guard.c @@ -24,7 +24,7 @@ #if BSP_TZ_SECURE_BUILD /* If the CGG Security Attribution is configured to secure access only. */ - #if BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU + #if BSP_CFG_CLOCKS_SECURE == 1 /*******************************************************************************************************************//** * Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed. diff --git a/ra/fsp/src/bsp/mcu/all/bsp_io.h b/ra/fsp/src/bsp/mcu/all/bsp_io.h index bbd20a481..db50c6f88 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_io.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -409,7 +409,7 @@ __STATIC_INLINE void R_BSP_PinAccessEnable (void) /** If this is first entry then allow writing of PFS. */ if (0 == g_protect_pfswe_counter) { - #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8) + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled #else @@ -448,7 +448,7 @@ __STATIC_INLINE void R_BSP_PinAccessDisable (void) /** Is it safe to disable writing of PFS? */ if (0 == g_protect_pfswe_counter) { - #if BSP_TZ_SECURE_BUILD || (BSP_CFG_MCU_PART_SERIES == 8) + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled #else diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_irq.c index 5a9faf257..a45899fba 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -67,20 +67,22 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT void bsp_irq_cfg (void) { #if FSP_PRIV_TZ_USE_SECURE_REGS + #if (BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 0) + + /* On MCUs with this implementation of TrustZone, IRQ security attribution is set to secure by default. + * This means that flat projects do not need to set security attribution to secure. */ + #else /* Unprotect security registers. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); - #if !BSP_TZ_SECURE_BUILD + #if !BSP_TZ_SECURE_BUILD /* Set the DMAC channels to secure access. */ - #ifdef BSP_TZ_CFG_ICUSARC + #ifdef BSP_TZ_CFG_ICUSARC R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk; + #endif #endif - #ifdef BSP_TZ_CFG_DMASARA - R_CPSCU->DMASARA = ~R_CPSCU_DMASARA_DMASARAn_Msk; - #endif - #endif /* Place all vectors in non-secure state unless they are used in the secure project. */ uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD]; @@ -108,10 +110,14 @@ void bsp_irq_cfg (void) /* Protect security registers. */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + #endif #endif for (uint32_t i = 0U; i < (BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT); i++) { - R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + } } } diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_irq.h index baca33c74..296f78cc1 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -73,7 +73,7 @@ __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) R_ICU->IELSR_b[irq].IR = 0U; /* Read back the IELSR register to ensure that the IR bit is cleared. - * MREF_INTERNAL_001 */ + * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */ FSP_REGISTER_READ(R_ICU->IELSR[irq]); } diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index bb601f3fc..b3501b654 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -49,11 +49,21 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif /*******************************************************************************************************************//** * Enables the module stop state. @@ -61,11 +71,21 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ - FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ - FSP_CRITICAL_SECTION_EXIT;} +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif /** @} (end addtogroup BSP_MCU) */ @@ -208,6 +228,12 @@ FSP_HEADER #define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); #define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); +#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) + #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); + #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); +#endif /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c index 03f621cb6..65ba58879 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -82,11 +82,15 @@ void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) /* Is it safe to disable write access? */ if (0U == g_protect_counters[regs_to_protect]) { - /** Enable protection using PRCR register. */ - - /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + /** Enable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#else R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#endif } /** Restore the interrupt state */ @@ -108,11 +112,15 @@ void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) /* If this is first entry then disable protection. */ if (0U == g_protect_counters[regs_to_unprotect]) { - /** Disable protection using PRCR register. */ - - /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + /** Disable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#else R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#endif } /** Increment the protect counter */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c index 32595e626..b687da943 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -125,7 +125,7 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps #endif - #else /* CM33 parts */ + #else /* CM33 & CM85 parts */ #if !BSP_TZ_NONSECURE_BUILD @@ -228,6 +228,27 @@ BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_ #endif + #if 85U == __CORTEX_M && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl0") g_bsp_rom_fsblctrl0 = + BSP_CFG_ROM_REG_FSBLCTRL0; + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl1") g_bsp_rom_fsblctrl1 = + BSP_CFG_ROM_REG_FSBLCTRL1; + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl2") g_bsp_rom_fsblctrl2 = + BSP_CFG_ROM_REG_FSBLCTRL2; + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc0") g_bsp_rom_sacc0 = + BSP_CFG_ROM_REG_SACC0; + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc1") g_bsp_rom_sacc1 = + BSP_CFG_ROM_REG_SACC1; + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_samr") g_bsp_rom_samr = + BSP_CFG_ROM_REG_SAMR; + + #endif + #endif #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c index 6a4aef542..4a11f38d1 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_security.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -28,12 +28,26 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ - #define BSP_PRV_TZ_REG_KEY (0xA500U) - #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) - #define RA_NOT_DEFINED (0) + #define BSP_PRV_TZ_REG_KEY (0xA500U) + #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) + #define RA_NOT_DEFINED (0) /* Branch T3 Instruction (IMM11=-2) */ - #define BSP_PRV_INFINITE_LOOP (0xE7FE) + #define BSP_PRV_INFINITE_LOOP (0xE7FE) + + #define BSP_SAU_REGION_CODE_FLASH_NSC (0U) + #define BSP_SAU_REGION_1_NS (1U) + #define BSP_SAU_REGION_SRAM_NSC (2U) + #define BSP_SAU_REGION_2_NS (3U) + #define BSP_SAU_REGION_3_NS (4U) + +/* Non-secure regions defined by the IDAU. These regions must be defined as non-secure in the SAU. */ + #define BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS (0x10000000U) + #define BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS (0x1FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS (0x30000000U) + #define BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS (0x3FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS (0x50000000U) + #define BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS (0xDFFFFFFFU) /*********************************************************************************************************************** * Typedef definitions @@ -73,6 +87,26 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uin BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) __section_begin( ".tz_data_flash_ns_start"); + #if BSP_FEATURE_BSP_HAS_ITCM +extern const uint32_t __tz_ITCM_N; +extern const uint32_t __tz_ITCM_S; + #endif + + #if BSP_FEATURE_BSP_HAS_DTCM +extern const uint32_t __tz_DTCM_N; +extern const uint32_t __tz_DTCM_S; + #endif + + #if BSP_FEATURE_BSP_HAS_ITCM +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_itcm = (uint32_t *) &__tz_ITCM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_itcm = (uint32_t *) &__tz_ITCM_S; + #endif + + #if BSP_FEATURE_BSP_HAS_DTCM +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_dtcm = (uint32_t *) &__tz_DTCM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_dtcm = (uint32_t *) &__tz_DTCM_S; + #endif + #elif defined(__ARMCC_VERSION) #if BSP_FEATURE_BSP_HAS_ITCM extern const uint32_t Image$$__tz_ITCM_N$$Base; @@ -87,10 +121,18 @@ extern const uint32_t Image$$__tz_STANDBY_SRAM_N$$Base; extern const uint32_t Image$$__tz_STANDBY_SRAM_S$$Base; #endif extern const uint32_t Image$$__tz_FLASH_N$$Base; + #if BSP_FEATURE_TZ_VERSION == 2 +extern const uint32_t Image$$__FLASH_NSC_START$$Base; + #else extern const uint32_t Image$$__tz_FLASH_C$$Base; + #endif extern const uint32_t Image$$__tz_FLASH_S$$Base; extern const uint32_t Image$$__tz_RAM_N$$Base; + #if BSP_FEATURE_TZ_VERSION == 2 +extern const uint32_t Image$$__RAM_NSC_START$$Base; + #else extern const uint32_t Image$$__tz_RAM_C$$Base; + #endif extern const uint32_t Image$$__tz_RAM_S$$Base; extern const uint32_t Image$$__tz_DATA_FLASH_N$$Base; extern const uint32_t Image$$__tz_DATA_FLASH_S$$Base; @@ -122,10 +164,18 @@ extern const uint32_t Image$$__tz_ID_CODE_S$$Base; #define __tz_STANDBY_SRAM_S Image$$__tz_STANDBY_SRAM_S$$Base #endif #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base - #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base + #if BSP_FEATURE_TZ_VERSION == 2 + #define __tz_FLASH_C Image$$__FLASH_NSC_START$$Base; + #else + #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base + #endif #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base #define __tz_RAM_N Image$$__tz_RAM_N$$Base - #define __tz_RAM_C Image$$__tz_RAM_C$$Base + #if BSP_FEATURE_TZ_VERSION == 2 + #define __tz_RAM_C Image$$__RAM_NSC_START$$Base + #else + #define __tz_RAM_C Image$$__tz_RAM_C$$Base + #endif #define __tz_RAM_S Image$$__tz_RAM_S$$Base #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base @@ -188,17 +238,61 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code = #elif defined(__GNUC__) + #if defined(__llvm__) && !defined(__CLANG_TIDY__) +extern const uint32_t __tz_FLASH_N; + #else extern const uint32_t FLASH_NS_IMAGE_START; + #endif + #if BSP_FEATURE_TZ_VERSION == 2 +extern const uint32_t __FLASH_NSC_START; + #else extern const uint32_t __tz_FLASH_C; + #endif extern const uint32_t __tz_DATA_FLASH_N; extern const uint32_t __tz_RAM_N; + #if BSP_FEATURE_TZ_VERSION == 2 +extern const uint32_t __RAM_NSC_START; + #else extern const uint32_t __tz_RAM_C; + #endif + + #if BSP_FEATURE_BSP_HAS_ITCM +extern const uint32_t __tz_ITCM_N; +extern const uint32_t __tz_ITCM_S; + #endif + + #if BSP_FEATURE_BSP_HAS_DTCM +extern const uint32_t __tz_DTCM_N; +extern const uint32_t __tz_DTCM_S; + #endif -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START; + #if defined(__llvm__) && !defined(__CLANG_TIDY__) +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; + #else +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &FLASH_NS_IMAGE_START; + #endif + #if BSP_FEATURE_TZ_VERSION == 2 +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) &__FLASH_NSC_START; + #else BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = (uint32_t *) &__tz_FLASH_C; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) &__tz_DATA_FLASH_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) &__tz_RAM_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) &__tz_RAM_C; + #endif +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = (uint32_t *) &__tz_DATA_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = (uint32_t *) &__tz_RAM_N; + #if BSP_FEATURE_TZ_VERSION == 2 +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) &__RAM_NSC_START; + #else +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (uint32_t *) &__tz_RAM_C; + #endif + + #if BSP_FEATURE_BSP_HAS_ITCM +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_itcm = (uint32_t *) &__tz_ITCM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_itcm = (uint32_t *) &__tz_ITCM_S; + #endif + + #if BSP_FEATURE_BSP_HAS_DTCM +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_dtcm = (uint32_t *) &__tz_DTCM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_dtcm = (uint32_t *) &__tz_DTCM_S; + #endif #endif @@ -219,7 +313,8 @@ BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = (u void R_BSP_NonSecureEnter (void) { /* The NS vector table is at the start of the NS section in flash */ - uint32_t const * p_ns_vector_table = gp_start_of_nonsecure_flash; + uint32_t const * p_ns_vector_table = + (uint32_t *) ((uint32_t) gp_start_of_nonsecure_flash | BSP_FEATURE_TZ_NS_OFFSET); /* Set up the NS Reset_Handler to be called */ uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); @@ -236,14 +331,14 @@ void R_BSP_NonSecureEnter (void) */ if (UINT32_MAX == *p_ns_reset_address) { - p_ns_reset = (bsp_nonsecure_func_t) gp_start_of_nonsecure_ram; + p_ns_reset = (bsp_nonsecure_func_t) ((uint32_t) gp_start_of_nonsecure_ram | BSP_FEATURE_TZ_NS_OFFSET); /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n )). */ - uint16_t * infinite_loop = (uint16_t *) gp_start_of_nonsecure_ram; + uint16_t * infinite_loop = (uint16_t *) ((uint32_t) gp_start_of_nonsecure_ram | BSP_FEATURE_TZ_NS_OFFSET); *infinite_loop = BSP_PRV_INFINITE_LOOP; /* Set the NS stack pointer to a valid location in NS RAM. */ - __TZ_set_MSP_NS((uint32_t) gp_start_of_nonsecure_ram + 0x20U); + __TZ_set_MSP_NS((uint32_t) gp_start_of_nonsecure_ram + 0x20U + BSP_FEATURE_TZ_NS_OFFSET); /* Jump to the infinite loop. */ p_ns_reset(); @@ -284,9 +379,96 @@ void R_BSP_SecurityInit (void) R_PSCU->SSAMONB = (uint32_t) gp_start_of_nonsecure_callable_ram & R_PSCU_SSAMONB_SS1_Msk; #endif + #if BSP_FEATURE_BSP_HAS_ITCM == 1 + + /* Total ITCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t itcm_block_size = ((MEMSYSCTL->ITGU_CFG & MEMSYSCTL_ITGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_ITGU_CFG_BLKSZ_Pos) + + 5U; + + /* The number of secure ITCM blocks is equal to size of the secure region in bytes divided by the ITCM block size. */ + uint32_t itcm_num_sec_blocks = ((uint32_t) gp_start_of_nonsecure_itcm - (uint32_t) gp_start_of_secure_itcm) >> + itcm_block_size; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->ITGU_LUT[0] = ~((1U << itcm_num_sec_blocks) - 1U); + #endif + + #if BSP_FEATURE_BSP_HAS_DTCM == 1 + + /* Total DTCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t dtcm_block_size = ((MEMSYSCTL->DTGU_CFG & MEMSYSCTL_DTGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_DTGU_CFG_BLKSZ_Pos) + + 5U; + + /* The number of secure DTCM blocks is equal to size of the secure region in bytes divided by the DTCM block size. */ + uint32_t dtcm_num_sec_blocks = ((uint32_t) gp_start_of_nonsecure_dtcm - (uint32_t) gp_start_of_secure_dtcm) >> + dtcm_block_size; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->DTGU_LUT[0] = ~((1U << dtcm_num_sec_blocks) - 1U); + #endif + + #if __SAUREGION_PRESENT + + /* Configure IDAU to divide SRAM region into NSC/NS. */ + R_CPSCU->SRAMSABAR0 = (uint32_t) gp_start_of_nonsecure_ram & R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk; + R_CPSCU->SRAMSABAR1 = (uint32_t) gp_start_of_nonsecure_ram & R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk; + + /* Configure SAU region used for Code Flash Non-secure callable. */ + SAU->RNR = BSP_SAU_REGION_CODE_FLASH_NSC; + SAU->RBAR = (uint32_t) gp_start_of_nonsecure_callable_flash & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (((uint32_t) gp_start_of_nonsecure_flash - 1U) & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 1: + * - ITCM + * - Code Flash + * - On-chip flash (Factory Flash) + * - On-chip flash (option-setting memory) + */ + SAU->RNR = BSP_SAU_REGION_1_NS; + SAU->RBAR = (uint32_t) BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = ((BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS) &SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure callable SRAM. */ + SAU->RNR = BSP_SAU_REGION_SRAM_NSC; + SAU->RBAR = (uint32_t) gp_start_of_nonsecure_callable_ram & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (((uint32_t) gp_start_of_nonsecure_ram - 1U) & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 2: + * - DTCM + * - On-chip SRAM + * - Standby SRAM + * - On-chip flash (data flash) + */ + SAU->RNR = BSP_SAU_REGION_2_NS; + SAU->RBAR = ((uint32_t) BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS & SAU_RBAR_BADDR_Msk) | BSP_FEATURE_TZ_NS_OFFSET; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 3: + * - Peripheral I/O registers + * - Flash I/O registers + * - External address space (CS area) + * - External address space (SDRAM area) + * - External address space (OSPI area) + */ + SAU->RNR = BSP_SAU_REGION_3_NS; + SAU->RBAR = BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Enable the SAU. */ + SAU->CTRL = SAU_CTRL_ENABLE_Msk; + + /* Cache maintenance is required when changing security attribution of an address. + * Barrier instructions are required to guarantee intended operation + * (See Arm Cortex-M85 Technical Reference Manual Section 10.9.3). */ + SCB_InvalidateICache(); + #else + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the * system. */ SAU->CTRL = SAU_CTRL_ALLNS_Msk; + #endif /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the @@ -345,6 +527,12 @@ void R_BSP_SecurityInit (void) R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ + #ifdef BSP_TZ_CFG_RSCSAR + R_SYSTEM->RSCSAR = BSP_TZ_CFG_RSCSAR; /* RAM Standby Control Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_PGCSAR + R_SYSTEM->PGCSAR = BSP_TZ_CFG_PGCSAR; /* Power Gating Control Security Attribution. */ + #endif #ifdef BSP_TZ_CFG_BBFSAR R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ #endif @@ -353,8 +541,8 @@ void R_BSP_SecurityInit (void) #ifdef BSP_TZ_CFG_ICUSARC R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ #endif - #ifdef BSP_TZ_CFG_DMASARA - R_CPSCU->DMASARA = BSP_TZ_CFG_DMASARA; /* DMAC Channel Security Attribution. */ + #ifdef BSP_TZ_CFG_DMACCHSAR + R_CPSCU->DMACCHSAR = BSP_TZ_CFG_DMACCHSAR; /* DMAC Channel Security Attribution. */ #endif #ifdef BSP_TZ_CFG_ICUSARD R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ @@ -366,35 +554,63 @@ void R_BSP_SecurityInit (void) #ifdef BSP_TZ_CFG_TEVTRCR R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */ #endif - R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ - R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + #ifdef BSP_TZ_CFG_ELCSARA + R_ELC->ELCSARA = BSP_TZ_CFG_ELCSARA; /* ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ + #endif + R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ + R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + #ifdef BSP_TZ_CFG_STBRAMSAR R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ - R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */ - R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ - R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ + #endif + R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */ + R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ + R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \ - (defined(BSP_TZ_CFG_DMASARA) && (BSP_TZ_CFG_DMASARA != UINT32_MAX)) + (defined(BSP_TZ_CFG_DMACCHSAR) && \ + ((BSP_TZ_CFG_DMACCHSAR & R_CPSCU_DMACCHSAR_DMACCHSARn_Msk) != R_CPSCU_DMACCHSAR_DMACCHSARn_Msk)) R_BSP_MODULE_START(FSP_IP_DMAC, 0); + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DMAST security attribution is set to secure after reset. */ + #else + /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST * in order to prevent the nonsecure program from disabling all DMAC channels. */ R_CPSCU->DMACSAR = ~1U; /* Protect DMAST from nonsecure write access. */ + #endif /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ R_DMA->DMAST = 1U; + #else + + /* On MCUs with this implementation of trustzone, DMACSAR security attribution is set to secure after reset. + * If the DMAC is not used in the secure application,then configure DMAST security attribution to non-secure. */ + R_CPSCU->DMACSAR = 1U; #endif #if BSP_TZ_CFG_DTC_USED R_BSP_MODULE_START(FSP_IP_DTC, 0); + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. */ + #else + /* If the DTC is used by the secure program, disable nonsecure write access to DTCST * in order to prevent the nonsecure program from disabling all DTC transfers. */ R_CPSCU->DTCSAR = ~1U; + #endif /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ R_DTC->DTCST = 1U; + #elif BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. + * If the DTC is not used in the secure application,then configure DTCST security attribution to non-secure. */ + R_CPSCU->DTCSAR = 1U; #endif /* Initialize security attribution registers for Pins. */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/ra/fsp/src/bsp/mcu/all/bsp_tfu.h index c4367add6..c0dc51231 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_tfu.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -40,34 +40,36 @@ FSP_HEADER * @{ **********************************************************************************************************************/ +#if BSP_FEATURE_TFU_SUPPORTED + /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f + #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f -#ifdef __GNUC__ /* and (arm)clang */ - #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + #ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) /* No form of inline is available, it happens only when -std=c89, gnu89 and * above are OK */ - #warning \ + #warning \ "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" - #else - #ifdef __GNUC_GNU_INLINE__ + #else + #ifdef __GNUC_GNU_INLINE__ /* gnu89 semantics of inline and extern inline are essentially the exact * opposite of those in C99 */ - #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) - #else /* __GNUC_STDC_INLINE__ */ - #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif #endif + #elif __ICCARM__ + #define BSP_TFU_INLINE + #else + #error "Compiler not supported!" #endif -#elif __ICCARM__ - #define BSP_TFU_INLINE -#else - #error "Compiler not supported!" -#endif /*********************************************************************************************************************** * Typedef definitions @@ -87,9 +89,9 @@ FSP_HEADER * * @retval Sine value of an angle. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE float __sinf (float angle) { /* Set the angle to R_TFU->SCDT1 */ @@ -105,9 +107,9 @@ BSP_TFU_INLINE float __sinf (float angle) * * @retval Cosine value of an angle. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE float __cosf (float angle) { /* Set the angle to R_TFU->SCDT1 */ @@ -123,9 +125,9 @@ BSP_TFU_INLINE float __cosf (float angle) * @param[out] sin Sine value of an angle. * @param[out] cos Cosine value of an angle. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) { /* Set the angle to R_TFU->SCDT1 */ @@ -145,9 +147,9 @@ BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) * * @retval Arc tangent for given values. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) { /* Set X-cordinate to R_TFU->ATDT0 */ @@ -167,9 +169,9 @@ BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) * * @retval Hypotenuse for given values. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) { /* Set X-coordinate to R_TFU->ATDT0 */ @@ -189,9 +191,9 @@ BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) * @param[out] atan2 Arc tangent for given values. * @param[out] hypot Hypotenuse for given values. **********************************************************************************************************************/ -#if __ICCARM__ - #pragma inline = forced -#endif + #if __ICCARM__ + #pragma inline = forced + #endif BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) { /* Set X-coordinate to R_TFU->ATDT0 */ @@ -207,19 +209,21 @@ BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, fl *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; } -#if BSP_CFG_USE_TFU_MATHLIB - #define sinf(x) __sinf(x) - #define cosf(x) __cosf(x) - #define atan2f(y, x) __atan2f(y, x) - #define hypotf(x, y) __hypotf(x, y) - #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) - #define sincosf(a, s, c) __sincosf(a, s, c) -#endif + #if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) + #endif /*********************************************************************************************************************** * Exported global functions (to be accessed by other files) **********************************************************************************************************************/ +#endif + /** @} (end addtogroup BSP_MCU) */ /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 7cb9297ff..33266cfc4 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -215,6 +217,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -286,6 +290,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA2A1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (3) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -362,8 +367,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -430,8 +436,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index e40e26174..fe1d98bc4 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -87,7 +87,7 @@ #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_BSP_FLASH_CACHE (0) -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0) // Feature not available on this MCU @@ -213,6 +215,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -284,6 +288,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_ICLK) // RA2E1 Flash uses ICLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (4) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -360,8 +365,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -428,8 +434,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU #define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h index 08b187118..24cc02478 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h @@ -87,7 +87,7 @@ #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) #define BSP_FEATURE_BSP_FLASH_CACHE (0) -#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0) // Feature not available on this MCU @@ -213,6 +215,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -284,6 +288,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_ICLK) // RA2E2 Flash uses ICLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (4) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -360,8 +365,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -428,8 +434,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU #define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h new file mode 100644 index 000000000..afb9e91db --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_elc.h @@ -0,0 +1,173 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2E3 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra2e3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x01), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x02), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x03), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x04), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x05), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x06), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x07), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x08), // External pin interrupt 7 + ELC_EVENT_DTC_COMPLETE = (0x09), // DTC last transfer + ELC_EVENT_DTC_END = (0x0A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x0B), // Canceling from Snooze mode + ELC_EVENT_FCU_FRDYI = (0x0C), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x0D), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x0E), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x0F), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x10), // Snooze entry + ELC_EVENT_AGT0_INT = (0x11), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x12), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x13), // Compare match B + ELC_EVENT_AGT1_INT = (0x14), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x15), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x16), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x17), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x18), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x19), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x1A), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x1B), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x1C), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x1D), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x1E), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x1F), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x20), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x21), // Compare mismatch + ELC_EVENT_IIC0_RXI = (0x27), // Receive data full + ELC_EVENT_IIC0_TXI = (0x28), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x29), // Transmit end + ELC_EVENT_IIC0_ERI = (0x2A), // Transfer error + ELC_EVENT_IIC0_WUI = (0x2B), // Slave address match + ELC_EVENT_KEY_INT = (0x33), // Key interrupt + ELC_EVENT_DOC_INT = (0x34), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x35), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x36), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x37), // Overflow interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x3D), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x3E), // Port 2 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x3F), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x40), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x41), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x42), // Port Output disable interrupt B + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x46), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x47), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x48), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x49), // Compare match D + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x4A), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x4B), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x5E), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x5F), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x60), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x61), // Compare match D + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x62), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x63), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x64), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x65), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x66), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x67), // Compare match D + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x68), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x69), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x6A), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x6B), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x6C), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x6D), // Compare match D + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x6E), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x6F), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x70), // UVW edge event + ELC_EVENT_SCI0_RXI = (0x71), // Receive data full + ELC_EVENT_SCI0_TXI = (0x72), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x73), // Transmit end + ELC_EVENT_SCI0_ERI = (0x74), // Receive error + ELC_EVENT_SCI0_AM = (0x75), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x76), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x77), // Received data full + ELC_EVENT_SCI1_TXI = (0x78), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x79), // Transmit end + ELC_EVENT_SCI1_ERI = (0x7A), // Receive error + ELC_EVENT_SCI1_AM = (0x7B), // Address match event + ELC_EVENT_SCI9_RXI = (0x7C), // Received data full + ELC_EVENT_SCI9_TXI = (0x7D), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x7E), // Transmit end + ELC_EVENT_SCI9_ERI = (0x7F), // Receive error + ELC_EVENT_SCI9_AM = (0x80), // Address match event + ELC_EVENT_SPI0_RXI = (0x81), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x82), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x83), // Idle + ELC_EVENT_SPI0_ERI = (0x84), // Error + ELC_EVENT_SPI0_TEI = (0x85), // Transmission complete event + ELC_EVENT_SCI2_RXI = (0x8E), // Received data full + ELC_EVENT_SCI2_TXI = (0x8F), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x90), // Transmit end + ELC_EVENT_SCI2_ERI = (0x91), // Receive error + ELC_EVENT_SCI2_AM = (0x92), // Address match event + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x98), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x99), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x9A), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x9B), // Compare match D + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x9C), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x9D), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x9E), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x9F), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0xA0), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0xA1), // Compare match D + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0xA2), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0xA3), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0xA4), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0xA5), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0xA6), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0xA7), // Compare match D + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0xA8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0xA9), // Underflow +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA2E3) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h new file mode 100644 index 000000000..9a0b1e36c --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_feature.h @@ -0,0 +1,448 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (9999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#else + #define CGC_MAINCLOCK_DRIVE (0x01U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U) +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U) +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKD) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADBUF (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3300) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x7807E7) // 0 to 2, 5 to 10, 19 to 22 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) + +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2) +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (0) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) +#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) +#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) +#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_OFS2 (0) +#define BSP_FEATURE_BSP_HAS_OFS3 (0) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) +#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_SYRACCR (0U) +#define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_NUM_PMSAR (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01001C00U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CANFD_FD_SUPPORT (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_LITE (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) // Feature not available on this MCU + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) // Feature not available on this MCU +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) // Feature not available on this MCU +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) // Feature not available on this MCU +#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // Feature not available on this MCU + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1) +#define BSP_FEATURE_CGC_HAS_BCLK (0U) +#define BSP_FEATURE_CGC_HAS_CPUCLK (0U) +#define BSP_FEATURE_CGC_HAS_FCLK (0U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (1U) +#define BSP_FEATURE_CGC_HAS_FLL (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (0U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (0U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PCLKE (0U) +#define BSP_FEATURE_CGC_HAS_PLL (0U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_SOPCCR (1U) +#define BSP_FEATURE_CGC_HAS_SOSC (1U) +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (24000000U) +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_P_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_Q_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_R_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_P_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_Q_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_OUT_R_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_P_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_Q_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_R_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_P_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_Q_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_OUT_R_MIN_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (0U) // Feature not available on this MCU + +#define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) + +#define BSP_FEATURE_CRYPTO_HAS_AES (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) // Feature not available on this MCU +#define BSP_FEATURE_DAC_MAX_CHANNELS (0U) // Feature not available on this MCU + +#define BSP_FEATURE_DMAC_HAS_DELSR (0U) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0U) // Feature not available on this MCU +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU + +#define BSP_FEATURE_DOC_VERSION (1U) + +#define BSP_FEATURE_DWT_CYCCNT (0U) + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0004C30FU) // Positions of event link set registers (ELSRs) available on this MCU +#define BSP_FEATURE_ELC_VERSION (1U) + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x0U) +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x7FFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (11) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (4) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_ICLK) // RA2E3 Flash uses ICLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (4) +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4U) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_TPCS_SHIFT (1U) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F1) + +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MSTP_OFFSET (0U) // Feature not available on this MCU + +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (1U) +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) // Feature not available on this MCU + +#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x01) +#define BSP_FEATURE_IIC_VERSION (1U) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (0x0006U) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) +#define BSP_FEATURE_IOPORT_VERSION (1U) + +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0U) // Feature not available on this MCU + +#define BSP_FEATURE_KINT_HAS_MSTP (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) +#define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) + +#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) +#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (100U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) +#define BSP_FEATURE_RTC_HAS_ROPSEL (1U) +#define BSP_FEATURE_RTC_HAS_TCEN (0U) +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (0U) +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (0U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x207U) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0U) // Feature not available on this MCU +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0U) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) +#define BSP_FEATURE_SCI_VERSION (1U) + +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (1U) +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x0U) + +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0) // Feature not available on this MCU + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_NS_OFFSET (0U) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_HAS_DLM (0) // Feature not available on this MCU +#define BSP_FEATURE_TZ_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) + +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x3U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_icu.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_icu.h new file mode 100644 index 000000000..c4a3fb155 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_icu.h @@ -0,0 +1,162 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ICU_H +#define BSP_ICU_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA2E3 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events to be used with the IELSR register to link interrupt events to the NVIC + * @note This list is device specific. + * */ +typedef enum e_icu_event_ra2e3 +{ + ICU_EVENT_ADC0_COMPARE_MATCH = (0x08), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ADC0_COMPARE_MISMATCH = (0x06), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ADC0_SCAN_END = (0x07), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ADC0_SCAN_END_B = (0x05), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ADC0_WINDOW_A = (0x05), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ADC0_WINDOW_B = (0x05), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_AGT0_COMPARE_A = (0x16), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_AGT0_COMPARE_B = (0x13), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_AGT0_INT = (0x11), // group3 (IELSR3/11/19/27) + ICU_EVENT_AGT1_COMPARE_A = (0x03), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_AGT1_COMPARE_B = (0x03), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_AGT1_INT = (0x05), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_CAC_FREQUENCY_ERROR = (0x0b), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_CAC_MEASUREMENT_END = (0x08), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_CAC_OVERFLOW = (0x08), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_CGC_MOSC_STOP = (0x14), // group6 (IELSR6/14/22/30) + ICU_EVENT_DOC_INT = (0x0a), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_DTC_COMPLETE = (0x02), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0a), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0a), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_FCU_FRDYI = (0x02), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0e), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0d), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_GPT0_COMPARE_C = (0x0c), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_GPT0_COMPARE_D = (0x0c), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_GPT0_COUNTER_OVERFLOW = (0x0f), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0e), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_GPT4_CAPTURE_COMPARE_A = (0x1b), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT4_CAPTURE_COMPARE_B = (0x18), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT4_COMPARE_C = (0x15), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT4_COMPARE_D = (0x13), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT4_COUNTER_OVERFLOW = (0x16), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT4_COUNTER_UNDERFLOW = (0x13), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT5_CAPTURE_COMPARE_A = (0x1a), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT5_CAPTURE_COMPARE_B = (0x17), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT5_COMPARE_C = (0x17), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT5_COMPARE_D = (0x14), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT5_COUNTER_OVERFLOW = (0x16), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT5_COUNTER_UNDERFLOW = (0x14), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT6_CAPTURE_COMPARE_A = (0x1c), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT6_CAPTURE_COMPARE_B = (0x19), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT6_COMPARE_C = (0x17), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT6_COMPARE_D = (0x15), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT6_COUNTER_OVERFLOW = (0x18), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT6_COUNTER_UNDERFLOW = (0x15), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT7_CAPTURE_COMPARE_A = (0x1b), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT7_CAPTURE_COMPARE_B = (0x18), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT7_COMPARE_C = (0x19), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT7_COMPARE_D = (0x16), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT7_COUNTER_OVERFLOW = (0x18), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT7_COUNTER_UNDERFLOW = (0x16), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT8_CAPTURE_COMPARE_A = (0x1d), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_GPT8_CAPTURE_COMPARE_B = (0x1a), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_GPT8_COMPARE_C = (0x19), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT8_COMPARE_D = (0x17), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT8_COUNTER_OVERFLOW = (0x1a), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT8_COUNTER_UNDERFLOW = (0x17), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT9_CAPTURE_COMPARE_A = (0x1c), // group4 (IELSR4/12/20/28) + ICU_EVENT_GPT9_CAPTURE_COMPARE_B = (0x19), // group5 (IELSR5/13/21/29) + ICU_EVENT_GPT9_COMPARE_C = (0x1b), // group6 (IELSR6/14/22/30) + ICU_EVENT_GPT9_COMPARE_D = (0x18), // group7 (IELSR7/15/23/31) + ICU_EVENT_GPT9_COUNTER_OVERFLOW = (0x1a), // group2 (IELSR2/10/18/26) + ICU_EVENT_GPT9_COUNTER_UNDERFLOW = (0x18), // group3 (IELSR3/11/19/27) + ICU_EVENT_GPT_UVWEDGE = (0x11), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ0 = (0x01), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ1 = (0x01), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_ICU_IRQ2 = (0x01), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_ICU_IRQ3 = (0x01), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_ICU_IRQ4 = (0x16), // group4 (IELSR4/12/20/28) + ICU_EVENT_ICU_IRQ5 = (0x13), // group5 (IELSR5/13/21/29) + ICU_EVENT_ICU_IRQ6 = (0x13), // group6 (IELSR6/14/22/30) + ICU_EVENT_ICU_IRQ7 = (0x11), // group7 (IELSR7/15/23/31) + ICU_EVENT_ICU_SNOOZE_CANCEL = (0x03), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IIC0_ERI = (0x06), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_IIC0_RXI = (0x0a), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IIC0_TEI = (0x06), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_IIC0_TXI = (0x08), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_IIC0_WUI = (0x0b), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_IOPORT_EVENT_1 = (0x15), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_IOPORT_EVENT_2 = (0x13), // group2 (IELSR2/10/18/26) + ICU_EVENT_IWDT_UNDERFLOW = (0x03), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_KEY_INT = (0x18), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_LPM_SNOOZE_REQUEST = (0x02), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_LVD_LVD1 = (0x04), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_LVD_LVD2 = (0x02), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_POEG0_EVENT = (0x0b), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_POEG1_EVENT = (0x0b), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_RTC_ALARM = (0x04), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_RTC_CARRY = (0x04), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_RTC_PERIOD = (0x04), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SCI0_AM = (0x13), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SCI0_ERI = (0x0f), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_SCI0_RXI = (0x12), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SCI0_TEI = (0x0f), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SCI0_TXI = (0x10), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_SCI1_AM = (0x1a), // group5 (IELSR5/13/21/29) + ICU_EVENT_SCI1_ERI = (0x19), // group3 (IELSR3/11/19/27) + ICU_EVENT_SCI1_RXI = (0x1e), // group0 (IELSR0/ 8/16/24) + ICU_EVENT_SCI1_TEI = (0x1b), // group2 (IELSR2/10/18/26) + ICU_EVENT_SCI1_TXI = (0x1b), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_SCI2_AM = (0x1c), // group1 (IELSR1/ 9/17/25) + ICU_EVENT_SCI2_ERI = (0x19), // group7 (IELSR7/15/23/31) + ICU_EVENT_SCI2_RXI = (0x1d), // group4 (IELSR4/12/20/28) + ICU_EVENT_SCI2_TEI = (0x1c), // group6 (IELSR6/14/22/30) + ICU_EVENT_SCI2_TXI = (0x1b), // group5 (IELSR5/13/21/29) + ICU_EVENT_SCI9_AM = (0x1b), // group3 (IELSR3/11/19/27) + ICU_EVENT_SCI9_ERI = (0x1a), // group7 (IELSR7/15/23/31) + ICU_EVENT_SCI9_RXI = (0x1e), // group4 (IELSR4/12/20/28) + ICU_EVENT_SCI9_TEI = (0x1e), // group6 (IELSR6/14/22/30) + ICU_EVENT_SCI9_TXI = (0x1c), // group5 (IELSR5/13/21/29) + ICU_EVENT_SPI0_ERI = (0x10), // group3 (IELSR3/11/19/27) or group7 (IELSR7/15/23/31) + ICU_EVENT_SPI0_IDLE = (0x10), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SPI0_RXI = (0x14), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) + ICU_EVENT_SPI0_TEI = (0x11), // group2 (IELSR2/10/18/26) or group6 (IELSR6/14/22/30) + ICU_EVENT_SPI0_TXI = (0x11), // group1 (IELSR1/ 9/17/25) or group5 (IELSR5/13/21/29) + ICU_EVENT_WDT_UNDERFLOW = (0x06), // group0 (IELSR0/ 8/16/24) or group4 (IELSR4/12/20/28) +} icu_event_t; + +/** @} (end addtogroup BSP_MCU_RA2E3) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2e3/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2e3/bsp_mcu_info.h new file mode 100644 index 000000000..435129e45 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra2e3/bsp_mcu_info.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA2E3 RA2E3 + * @includedoc config_bsp_ra2e3_fsp.html + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "../../src/bsp/mcu/ra2e3/bsp_elc.h" +#include "../../src/bsp/mcu/ra2e3/bsp_icu.h" +#include "../../src/bsp/mcu/ra2e3/bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef icu_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end defgroup BSP_MCU_RA2E3) */ diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index feae0d656..a29d115d6 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -213,6 +215,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (1) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x04000404) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -284,6 +288,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_ICLK) // RA2L1 Flash uses ICLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (4) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -360,8 +365,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -428,8 +434,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h index 9c8a900a8..5f8487095 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h index 3d38b28d0..7614995e1 100644 --- a/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h @@ -132,8 +132,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -216,6 +218,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -286,6 +290,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) // Feature not available on this MCU @@ -362,8 +367,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -430,8 +436,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index 750c55493..bdd9d23c6 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -215,6 +217,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -286,6 +290,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4M1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (3) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -362,8 +367,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -430,8 +436,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index bf7d107c9..b089b2e4e 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,9 +219,12 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) + #define BSP_FEATURE_CRYPTO_HAS_AES (1) #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) @@ -287,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -363,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -431,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index 67d70f802..34bebde8b 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -133,8 +133,11 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_VTOR_LOCKED (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +220,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +293,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +370,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +439,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h index 67590e1ed..4121e3174 100644 --- a/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4t1/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (1U) #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index 88183539f..0278a1f3e 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -129,8 +129,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -215,6 +217,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44044444) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -286,6 +290,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4W1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (3) #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -362,8 +367,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (300U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -430,8 +436,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h index 4e5585ebd..6a94dec07 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h index da00169a6..b3e81fa46 100644 --- a/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h @@ -132,8 +132,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -216,6 +218,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -286,6 +290,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) // Feature not available on this MCU @@ -362,8 +367,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -430,8 +436,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index f176a7206..1854b5bdd 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -219,6 +221,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -290,6 +294,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -366,8 +371,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -434,8 +440,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index eaf6c6d3d..1d50ce84c 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -219,6 +221,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -290,6 +294,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -366,8 +371,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -434,8 +440,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index f5b1b0072..bec26677c 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -219,6 +221,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -290,6 +294,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -366,8 +371,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -434,8 +440,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index 118f48f18..c9e009e8e 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h index 0d8b4dfbc..385387f12 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index f8e2e6e99..24d38239a 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -219,6 +221,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -290,6 +294,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) @@ -366,8 +371,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -434,8 +440,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (0U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h index 6efbe1a14..789779e25 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // Feature not available on this MCU @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -433,8 +439,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (1U) // Trigonometric Function Unit (TFU) available on this MCU #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h index d336f7314..50868fa9d 100644 --- a/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t3/bsp_feature.h @@ -133,8 +133,10 @@ #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. @@ -217,6 +219,8 @@ #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1) #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78) #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222) #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) @@ -288,6 +292,7 @@ #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) // Feature not available on this MCU @@ -364,8 +369,9 @@ #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD1 to stabilize -#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD2 to stabilize +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0U) #define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (0U) #define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (0U) @@ -432,8 +438,10 @@ #define BSP_FEATURE_TFU_SUPPORTED (1U) #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1U) +#define BSP_FEATURE_TZ_NS_OFFSET (0U) #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) #define BSP_FEATURE_TZ_HAS_DLM (0U) +#define BSP_FEATURE_TZ_VERSION (1U) #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0) #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0U) diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h new file mode 100644 index 000000000..51d00fa43 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h @@ -0,0 +1,365 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8M1 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra8m1 +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end 0 + ELC_EVENT_DMAC1_INT = (0x012), // DMAC0 transfer end 1 + ELC_EVENT_DMAC2_INT = (0x013), // DMAC0 transfer end 2 + ELC_EVENT_DMAC3_INT = (0x014), // DMAC0 transfer end 3 + ELC_EVENT_DMAC4_INT = (0x015), // DMAC0 transfer end 4 + ELC_EVENT_DMAC5_INT = (0x016), // DMAC0 transfer end 5 + ELC_EVENT_DMAC6_INT = (0x017), // DMAC0 transfer end 6 + ELC_EVENT_DMAC7_INT = (0x018), // DMAC0 transfer end 7 + ELC_EVENT_DTC_END = (0x021), // DTC transfer end + ELC_EVENT_DTC_COMPLETE = (0x022), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x027), // DMA transfer error + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_LVD_VBATT = (0x03D), // VBATT low voltage detect + ELC_EVENT_CGC_MOSC_STOP = (0x03E), // Main Clock oscillation stop + ELC_EVENT_ULPT0_INT = (0x040), // ULPT0 Underflow + ELC_EVENT_ULPT0_COMPARE_A = (0x041), // ULPT0 Compare match A + ELC_EVENT_ULPT0_COMPARE_B = (0x042), // ULPT0 Compare match B + ELC_EVENT_ULPT1_INT = (0x043), // ULPT1 Underflow + ELC_EVENT_ULPT1_COMPARE_A = (0x044), // ULPT1 Compare match A + ELC_EVENT_ULPT1_COMPARE_B = (0x045), // ULPT1 Compare match B + ELC_EVENT_AGT0_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT1_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT0_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_RTC_ALARM = (0x055), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x056), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x057), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x058), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x059), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (0x05A), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x05B), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x05C), // Receive data full + ELC_EVENT_IIC0_TXI = (0x05D), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x05E), // Transmit end + ELC_EVENT_IIC0_ERI = (0x05F), // Transfer error + ELC_EVENT_IIC0_WUI = (0x060), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x061), // Receive data full + ELC_EVENT_IIC1_TXI = (0x062), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x063), // Transmit end + ELC_EVENT_IIC1_ERI = (0x064), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x06B), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x06C), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x06D), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x06E), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x06F), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x070), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x071), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x072), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x073), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x074), // Receive data full + ELC_EVENT_SSI0_INT = (0x076), // Error interrupt + ELC_EVENT_SSI1_TXI_RXI = (0x079), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x07A), // Error interrupt + ELC_EVENT_ACMPHS0_INT = (0x07B), // Comparator interrupt 0 + ELC_EVENT_ACMPHS1_INT = (0x07C), // Comparator interrupt 1 + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x083), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x084), // Software event 1 + ELC_EVENT_IOPORT_EVENT_1 = (0x088), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x089), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x08A), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x08B), // Port 4 event + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x08C), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x08D), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x08E), // Overflow interrupt + ELC_EVENT_POEG0_EVENT = (0x08F), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x090), // Port Output disable interrupt B + ELC_EVENT_POEG2_EVENT = (0x091), // Port Output disable interrupt C + ELC_EVENT_POEG3_EVENT = (0x092), // Port Output disable interrupt D + ELC_EVENT_OPS_UVW_EDGE = (0x0A0), // UVW edge event + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0A1), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0A2), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0A3), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0A4), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0A5), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0A6), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0A7), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0A8), // Underflow + ELC_EVENT_GPT0_PC = (0x0A9), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0AA), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0Ab), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0AC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0AD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0AE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0AF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0B0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0B1), // Underflow + ELC_EVENT_GPT1_PC = (0x0B2), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0B3), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0B4), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0B5), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0B6), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0B7), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0B8), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0B9), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0BA), // Underflow + ELC_EVENT_GPT2_PC = (0x0BB), // Period count function finish + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0BC), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0BD), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0BE), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0BF), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0C0), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0C1), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0C2), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0C3), // Underflow + ELC_EVENT_GPT3_PC = (0x0C4), // Period count function finish + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0C5), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0C6), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0C7), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0C8), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0C9), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0CA), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0CB), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0CC), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0CE), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0CF), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0D7), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0D8), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0D9), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0DA), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0DB), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0DC), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0DD), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0DE), // Underflow + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0E0), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0E1), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0E2), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0E3), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0E4), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0E5), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0E6), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0E7), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x0E9), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x0EA), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x0EB), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x0EC), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x0ED), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x0EE), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x0EF), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x0F0), // Underflow + ELC_EVENT_GPT8_PC = (0x0F1), // Period count function finish + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x0F2), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x0F3), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x0F4), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x0F5), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x0F6), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x0F7), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x0F8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x0F9), // Underflow + ELC_EVENT_GPT9_PC = (0x0FA), // Period count function finish + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x0FB), // Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x0FC), // Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x0FD), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x0FE), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x0FF), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x100), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x101), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x102), // Underflow + ELC_EVENT_GPT10_PC = (0x103), // Period count function finish + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x104), // Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x105), // Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x106), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x107), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x108), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x109), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x10A), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x10B), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x10D), // Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x10E), // Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x10F), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x110), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x111), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x112), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x113), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x114), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x116), // Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x117), // Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x118), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x119), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x11A), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x11B), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x11C), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x11D), // Underflow + ELC_EVENT_EDMAC0_EINT = (0x120), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x121), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x122), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x123), // USBHS interr + ELC_EVENT_SCI0_RXI = (0x124), // Receive data full + ELC_EVENT_SCI0_TXI = (0x125), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x126), // Transmit end + ELC_EVENT_SCI0_ERI = (0x127), // Receive error + ELC_EVENT_SCI0_AED = (0x128), // Active edge detection + ELC_EVENT_SCI0_BFD = (0x129), // Break field detection + ELC_EVENT_SCI0_AM = (0x12A), // Address match event + ELC_EVENT_SCI1_RXI = (0x12B), // Receive data full + ELC_EVENT_SCI1_TXI = (0x12C), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x12D), // Transmit end + ELC_EVENT_SCI1_ERI = (0x12E), // Receive error + ELC_EVENT_SCI1_AED = (0x12F), // Active edge detection + ELC_EVENT_SCI1_BFD = (0x130), // Break field detection + ELC_EVENT_SCI1_AM = (0x131), // Address match event + ELC_EVENT_SCI2_RXI = (0x132), // Receive data full + ELC_EVENT_SCI2_TXI = (0x133), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x134), // Transmit end + ELC_EVENT_SCI2_ERI = (0x135), // Receive error + ELC_EVENT_SCI2_AM = (0x138), // Address match event + ELC_EVENT_SCI3_RXI = (0x139), // Receive data full + ELC_EVENT_SCI3_TXI = (0x13A), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x13B), // Transmit end + ELC_EVENT_SCI3_ERI = (0x13C), // Receive error + ELC_EVENT_SCI3_AM = (0x13F), // Address match event + ELC_EVENT_SCI4_RXI = (0x140), // Receive data full + ELC_EVENT_SCI4_TXI = (0x141), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x142), // Transmit end + ELC_EVENT_SCI4_ERI = (0x143), // Receive error + ELC_EVENT_SCI4_AM = (0x146), // Address match event + ELC_EVENT_SCI9_RXI = (0x163), // Receive data full + ELC_EVENT_SCI9_TXI = (0x164), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x165), // Transmit end + ELC_EVENT_SCI9_ERI = (0x166), // Receive error + ELC_EVENT_SCI9_AM = (0x169), // Address match event + ELC_EVENT_SPI0_RXI = (0x178), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x179), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x17A), // Idle + ELC_EVENT_SPI0_ERI = (0x17B), // Error + ELC_EVENT_SPI0_TEI = (0x17C), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x17D), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x17E), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x17F), // Idle + ELC_EVENT_SPI1_ERI = (0x180), // Error + ELC_EVENT_SPI1_TEI = (0x181), // Transmission complete event + ELC_EVENT_XSPI_ERR = (0x182), // xSPI Error + ELC_EVENT_XSPI_CMP = (0x183), // xSPI Complete + ELC_EVENT_CAN_RXF = (0x185), // Global recieve FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x186), // Global error + ELC_EVENT_CAN0_DMAREQ0 = (0x187), // Channel rx fifio DMA request + ELC_EVENT_CAN0_DMAREQ1 = (0x188), // Channel rx fifio DMA request + ELC_EVENT_CAN1_DMAREQ0 = (0x18B), // Channel rx fifio DMA request + ELC_EVENT_CAN1_DMAREQ1 = (0x18C), // Channel rx fifio DMA request + ELC_EVENT_CAN0_TX = (0x18F), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x190), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x191), // Common FIFO recieve interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x192), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x193), // RXMB interrupt lines + ELC_EVENT_CAN1_TX = (0x194), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x195), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x196), // Common FIFO recieve + ELC_EVENT_CAN1_CF_DMAREQ = (0x197), // Channel DMA req + ELC_EVENT_CAN1_RXMB = (0x198), // RXMB interrupt lines + ELC_EVENT_CAN0_MRAM_ERI = (0x19B), // CANFD0 ECC error + ELC_EVENT_CAN1_MRAM_ERI = (0x19C), // CANFD1 ECC error + ELC_EVENT_I3C0_RESPONSE = (0x19D), // Response status buffer full + ELC_EVENT_I3C0_COMMAND = (0x19E), // Command buffer empty + ELC_EVENT_I3C0_IBI = (0x19F), // IBI status buffer full + ELC_EVENT_I3C0_RX = (0x1A0), // Receive + ELC_EVENT_I3C0_TX = (0x1A1), // Transmit + ELC_EVENT_I3C0_RCV_STATUS = (0x1A2), // Receive status buffer full + ELC_EVENT_I3C0_HRESP = (0x1A3), // High priority response queue full + ELC_EVENT_I3C0_HCMD = (0x1A4), // High priority command queue empty + ELC_EVENT_I3C0_HRX = (0x1A5), // High priority rx data buffer full + ELC_EVENT_I3C0_HTX = (0x1A6), // High priority tx data buffer empty + ELC_EVENT_I3C0_TEND = (0x1A7), // Transmit end + ELC_EVENT_I3C0_EEI = (0x1A8), // Error + ELC_EVENT_I3C0_STEV = (0x1A9), // Synchronous Timing + ELC_EVENT_I3C0_MREFOVF = (0x1AA), // MREF counter overflow + ELC_EVENT_I3C0_MREFCPT = (0x1AB), // MREF capture + ELC_EVENT_I3C0_AMEV = (0x1AC), // Additional master-initiated bus event + ELC_EVENT_I3C0_WU = (0x1AD), // Wake-up Condition Detection interrupt + ELC_EVENT_ADC0_SCAN_END = (0x1AE), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x1AF), // End of A/D scanning operation for Group B + ELC_EVENT_ADC0_WINDOW_A = (0x1B0), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x1B1), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x1B2), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x1B3), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x1B4), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x1B5), // End of A/D scanning operation for Group B + ELC_EVENT_ADC1_WINDOW_A = (0x1B6), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x1B7), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch + ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt + ELC_EVENT_CEU_CEUI = (0x1DA), // CEU interrupt +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA8M1) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h new file mode 100644 index 000000000..8e3fe9357 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h @@ -0,0 +1,451 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x05U) +#elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x03U) +#else + #define CGC_MAINCLOCK_DRIVE (0x00U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0U) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0U) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) // ADC Derived from RA8M1 +#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0xF01FF) // 0 to 8, 16 to 19 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F007F) // 0 to 6, 16 to 22 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2) +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) +#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) +#define BSP_FEATURE_BSP_HAS_DTCM (1U) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0U) // Mutually exclusive with USB60 Clock +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) +#define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_ITCM (1U) +#define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1U) +#define BSP_FEATURE_BSP_HAS_OFS2 (1U) +#define BSP_FEATURE_BSP_HAS_OFS3 (0) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SCI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) +#define BSP_FEATURE_BSP_HAS_SPI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_SP_MON (0U) +#define BSP_FEATURE_BSP_HAS_SYRACCR (1U) +#define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POST_CRUNTIME_INIT (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SECURITY_PREINIT (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (240000000U) // The maximum frequency allowed without having five ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (192000000U) // The maximum frequency allowed without having four ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (120000000U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (48000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (144000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (96000000U) // The maximum frequency allowed without having two ROM wait cycles. (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x03008190U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CANFD_FD_SUPPORT (1U) +#define BSP_FEATURE_CANFD_LITE (1U) +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_INSTANCES (2U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA8M1 has CAN-FD + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0) +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_CPUCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PCLKE (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (1U) +#define BSP_FEATURE_CGC_HAS_SOPCCR (0U) +#define BSP_FEATURE_CGC_HAS_SOSC (1U) +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA8M1 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk) +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_P_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_Q_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_R_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000U) +#define BSP_FEATURE_CGC_PLL_OUT_P_MIN_HZ (40000000U) +#define BSP_FEATURE_CGC_PLL_OUT_Q_MIN_HZ (71000000U) +#define BSP_FEATURE_CGC_PLL_OUT_R_MIN_HZ (71000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (48000000U) +#define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (8000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_P_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_Q_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_R_MAX_HZ (480000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_P_MIN_HZ (40000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_Q_MIN_HZ (71000000U) +#define BSP_FEATURE_CGC_PLL2_OUT_R_MIN_HZ (71000000U) +#define BSP_FEATURE_CGC_PLL2_SRC_MAX_HZ (48000000U) +#define BSP_FEATURE_CGC_PLL2_SRC_MIN_HZ (8000000U) + +#define BSP_FEATURE_CGC_PLLCCR_TYPE (3U) +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SODRV_MASK (3U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0U) +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8) +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00000000) +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00) +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_NEW_PROCS (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_AES_IP_VERSION (0) +#define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) +#define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) +#define BSP_FEATURE_CRYPTO_HAS_RSIP7 (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) // Feature not available on this MCU +#define BSP_FEATURE_CTSU_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) +#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_HAS_DELSR (1U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DOC_VERSION (2U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA8M1 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x4003FFFFU) // Positions of event link set registers (ELSRs) available on this MCU +#define BSP_FEATURE_ELC_VERSION (2U) + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1U) // Feature available on this MCU + +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000U) +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000U) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x02200000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1) +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00FFU) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (115000000U) +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (200000000U) +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000U) +#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_TPCS_SHIFT (0U) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFU) + +#define BSP_FEATURE_I3C_NUM_CHANNELS (1U) +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (8U) +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16U) +#define BSP_FEATURE_I3C_MSTP_OFFSET (4U) + +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFU) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) + +#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01) +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01) +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0x03) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) +#define BSP_FEATURE_IIC_VERSION (0) // Feature not available on this MCU + +#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) +#define BSP_FEATURE_IOPORT_VERSION (2U) + +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1U) + +#define BSP_FEATURE_KINT_HAS_MSTP (0U) // Feature not available on this MCU + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x12FFFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0xAF1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1U) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (1U) +#define BSP_FEATURE_LPM_HAS_LPSCR (1U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (0U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1U) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD ((lvd_threshold_t) 0) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD ((lvd_threshold_t) 15) // 1.71V +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (20U) // LVD1 operation stabilization time after LVD1 is enabled +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (20U) // LVD2 operation stabilization time after LVD2 is enabled +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1U) + +#define BSP_FEATURE_NUM_PLL1_OUTPUT_CLOCKS (3U) +#define BSP_FEATURE_NUM_PLL2_OUTPUT_CLOCKS (3U) + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000U) +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x0U) + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1U) +#define BSP_FEATURE_RTC_IS_IRTC (0U) +#define BSP_FEATURE_RTC_HAS_ROPSEL (0) // Feature not available on this MCU +#define BSP_FEATURE_RTC_HAS_TCEN (1U) +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3U) +#define BSP_FEATURE_SYSC_HAS_VBTICTLR (1U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0U) +#define BSP_FEATURE_SCI_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (1U) +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x21FU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) +#define BSP_FEATURE_SCI_VERSION (2U) + +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03U) + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_SPCR3 (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (1) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) + +#define BSP_FEATURE_TFU_SUPPORTED (0U) // Trigonometric Function Unit (TFU) available on this MCU + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) +#define BSP_FEATURE_TZ_NS_OFFSET (1U << 28U) +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) +#define BSP_FEATURE_TZ_HAS_DLM (1U) +#define BSP_FEATURE_TZ_VERSION (2U) + +#define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (2) +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_CRC_HAS_SNOOP (1U) +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x4U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h new file mode 100644 index 000000000..991310e57 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA8M1 RA8M1 + * @includedoc config_bsp_ra8m1_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA8M1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h new file mode 100644 index 000000000..b30b1f0fd --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h @@ -0,0 +1,97 @@ +/*********************************************************************************************************************** + * Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8M1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8M1) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ + +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +#define BSP_OVERRIDE_GROUP_IRQ_T + +/* Override definitions. */ + +#define ELC_PERIPHERAL_NUM (30U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_I3C = (30), +} elc_peripheral_t; + +/* Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error + BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error + BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error +} bsp_grp_irq_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/ra/fsp/src/r_acmphs/r_acmphs.c b/ra/fsp/src/r_acmphs/r_acmphs.c index cdee2c0f5..17fba163b 100644 --- a/ra/fsp/src/r_acmphs/r_acmphs.c +++ b/ra/fsp/src/r_acmphs/r_acmphs.c @@ -376,7 +376,8 @@ static void acmphs_hardware_initialize (acmphs_instance_ctrl_t * const p_instanc R_MSTP->MSTPCRD_b.MSTPD28 = 0; /* Read back the register to ensure that the write has completed. - * MREF_INTERNAL_002 */ + * See Note for readback in section "10.2.4 MSTPCRA: Module Stop Control Register A" in + * the RA8M1 manual R01UH0994EJ0100. */ FSP_REGISTER_READ(R_MSTP->MSTPCRD); /*Writes to VREFEN bit must be in critical sections to ensure the driver is reentrant for different channels.*/ diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c index 231da4c83..12723a70c 100644 --- a/ra/fsp/src/r_agt/r_agt.c +++ b/ra/fsp/src/r_agt/r_agt.c @@ -723,13 +723,14 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; FSP_ASSERT((AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) || (p_cfg->channel & 1U)); - /* Devices with RTCCR.TCEN support P402/P403 as count sources. */ + /* Devices with RTCCR.TCEN support P402/P403/P404 as count sources. */ #if !BSP_FEATURE_RTC_HAS_TCEN if (AGT_PRV_IS_AGTW(p_instance_ctrl)) { - /* Return error for MCUs that do not support P402 and P403 as count sources*/ + /* Return error for MCUs that do not support P402, P403 and P404 as count sources*/ FSP_ASSERT(AGT_CLOCK_P402 != p_extend->count_source); FSP_ASSERT(AGT_CLOCK_P403 != p_extend->count_source); + FSP_ASSERT(AGT_CLOCK_P404 != p_extend->count_source); } #endif diff --git a/ra/fsp/src/r_ble/r_ble.c b/ra/fsp/src/r_ble/r_ble.c index 2072c6915..55d4c18dc 100644 --- a/ra/fsp/src/r_ble/r_ble.c +++ b/ra/fsp/src/r_ble/r_ble.c @@ -62,6 +62,340 @@ * Exported global functions **********************************************************************************************************************/ +ble_status_t R_BLE_ISO_SetPerAdvRecvEnable (uint16_t sync_hdl, uint8_t enable) { + FSP_PARAMETER_NOT_USED(sync_hdl); + FSP_PARAMETER_NOT_USED(enable); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetCteConnlessParam (st_ble_gap_cte_connless_t * cte_param) { + FSP_PARAMETER_NOT_USED(cte_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_EnableCteConnless (uint16_t adv_hdl, uint8_t enable) { + FSP_PARAMETER_NOT_USED(adv_hdl); + FSP_PARAMETER_NOT_USED(enable); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StartCteConnlessRecv (st_ble_gap_cte_connless_recv_t * p_cte_recv) { + FSP_PARAMETER_NOT_USED(p_cte_recv); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StopCteConnlessRecv (uint16_t sync_hdl) { + FSP_PARAMETER_NOT_USED(sync_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetCteConnParam (st_ble_gap_cte_conn_t * p_cte_param) { + FSP_PARAMETER_NOT_USED(p_cte_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_EnableCteConnRsp (uint16_t conn_hdl, uint8_t enable) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(enable); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetCteConnRecvParam (st_ble_gap_cte_conn_rx_param_t * p_cte_param) { + FSP_PARAMETER_NOT_USED(p_cte_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StopCteConnRecvSampling (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StartCteConnReq (st_ble_gap_cte_conn_req_t * p_req) { + FSP_PARAMETER_NOT_USED(p_req); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StopCteConnReq (uint16_t handle) { + FSP_PARAMETER_NOT_USED(handle); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetDefaultSubrate (st_ble_gap_subrate_param_t * p_subrate_param) { + FSP_PARAMETER_NOT_USED(p_subrate_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_RequestSubrate (uint16_t conn_hdl, st_ble_gap_subrate_param_t * p_subrate_param) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(p_subrate_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StartPerdAdvSetInfoTransfer (uint16_t adv_hdl, uint16_t conn_hdl, uint16_t service_data) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(adv_hdl); + FSP_PARAMETER_NOT_USED(service_data); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_StartPerdAdvSyncTransfer (uint16_t sync_hdl, uint16_t conn_hdl, uint16_t service_data) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(sync_hdl); + FSP_PARAMETER_NOT_USED(service_data); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetPerdAdvSyncTransferParam (uint16_t conn_hdl, st_ble_gap_past_param_t * p_past_param) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(p_past_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetDefPerdAdvSyncTransferParam (st_ble_gap_past_param_t * p_past_param) { + FSP_PARAMETER_NOT_USED(p_past_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_ReadAntennaInfo (void) { + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_ReceiverTest (st_ble_gap_recv_test_param_t * p_rx_test_param) { + FSP_PARAMETER_NOT_USED(p_rx_test_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_TransmitterTest (st_ble_gap_trans_test_param_t * p_tx_test_param) { + FSP_PARAMETER_NOT_USED(p_tx_test_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_ModifySleepClockAccuracy (uint8_t act) { + FSP_PARAMETER_NOT_USED(act); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_ReadRemoteTransmitPowerLevel (uint16_t conn_hdl, uint8_t phy) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(phy); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetPathLossReportingParam (st_ble_gap_set_path_loss_rpt_param_t * p_loss_rpt_param) { + FSP_PARAMETER_NOT_USED(p_loss_rpt_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetPathLossReportingEnable (uint16_t conn_hdl, uint8_t enable) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(enable); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetTransmitPowerReportingEnable (uint16_t conn_hdl, uint8_t local_enable, + uint8_t remote_enable) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(local_enable); + FSP_PARAMETER_NOT_USED(remote_enable); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetDataRelatedAddrChanges (uint8_t adv_hdl, uint8_t change_reason) { + FSP_PARAMETER_NOT_USED(adv_hdl); + FSP_PARAMETER_NOT_USED(change_reason); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_TestEnd (void) { + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_ReqPeerSCA (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_EnhancedReadTxPowerLevel (uint16_t conn_hdl, uint8_t phy) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(phy); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_GAP_SetHostFeat (uint8_t bit_number, uint8_t bit_value) { + FSP_PARAMETER_NOT_USED(bit_number); + FSP_PARAMETER_NOT_USED(bit_value); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_CreateBig (uint8_t * big_hdl, uint8_t adv_hdl, st_ble_iso_big_param_t * p_big_param) { + FSP_PARAMETER_NOT_USED(big_hdl); + FSP_PARAMETER_NOT_USED(adv_hdl); + FSP_PARAMETER_NOT_USED(p_big_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_StopBig (uint8_t big_hdl, uint8_t reason) { + FSP_PARAMETER_NOT_USED(big_hdl); + FSP_PARAMETER_NOT_USED(reason); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_CreateBigSync (uint8_t * big_hdl, + uint16_t sync_hdl, + st_ble_iso_big_sync_param_t * p_big_sync_param) { + FSP_PARAMETER_NOT_USED(big_hdl); + FSP_PARAMETER_NOT_USED(sync_hdl); + FSP_PARAMETER_NOT_USED(p_big_sync_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_TerminateBigSync (uint8_t big_hdl) { + FSP_PARAMETER_NOT_USED(big_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_SetCigParam (uint8_t * cig_id, st_ble_iso_cig_param_t * p_cig_param) { + FSP_PARAMETER_NOT_USED(cig_id); + FSP_PARAMETER_NOT_USED(p_cig_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_CreateCis (st_ble_iso_cis_conn_t * p_cis_conn) { + FSP_PARAMETER_NOT_USED(p_cis_conn); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_RemoveCig (uint8_t cig_id) { + FSP_PARAMETER_NOT_USED(cig_id); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_ReplyCisRequest (uint8_t cig_id, uint8_t cis_id, uint8_t response, uint8_t reason) { + FSP_PARAMETER_NOT_USED(cig_id); + FSP_PARAMETER_NOT_USED(cis_id); + FSP_PARAMETER_NOT_USED(response); + FSP_PARAMETER_NOT_USED(reason); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_SetupDataPath (uint16_t conn_hdl, st_ble_iso_chan_path * p_path) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(p_path); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_SendData (st_ble_iso_sdu_t * sdu_info) { + FSP_PARAMETER_NOT_USED(sdu_info); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_SendDataNoCopy (st_ble_iso_sdu_t * sdu_info) { + FSP_PARAMETER_NOT_USED(sdu_info); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_GetTxSync (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_CreateBigTest (uint8_t * big_hdl, + uint8_t adv_hdl, + st_ble_iso_create_big_test_param_t * p_create_big_test_param) { + FSP_PARAMETER_NOT_USED(big_hdl); + FSP_PARAMETER_NOT_USED(adv_hdl); + FSP_PARAMETER_NOT_USED(p_create_big_test_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_SetCigParamTest (uint8_t * cig_id, + st_ble_iso_set_cig_param_test_param_t * p_set_cig_param_test_param) { + FSP_PARAMETER_NOT_USED(cig_id); + FSP_PARAMETER_NOT_USED(p_set_cig_param_test_param); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_TransmitTest (uint16_t conn_hdl, uint8_t payload_type) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(payload_type); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_ReceiveTest (uint16_t conn_hdl, uint8_t payload_type) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(payload_type); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_ReadTestCounters (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_TestEnd (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_ReadLinkQuality (uint16_t conn_hdl) { + FSP_PARAMETER_NOT_USED(conn_hdl); + + return BLE_ERR_UNSUPPORTED; +}; + +ble_status_t R_BLE_ISO_RemoveDataPath (uint16_t conn_hdl, uint8_t dir) { + FSP_PARAMETER_NOT_USED(conn_hdl); + FSP_PARAMETER_NOT_USED(dir); + + return BLE_ERR_UNSUPPORTED; +}; + void r_ble_rf_control_error(uint32_t err_no); uint8_t r_ble_rf_power_save_mode(void); @@ -116,6 +450,7 @@ void r_ble_wake_up_task (void * EventGroupHandle) { xSemaphoreGive(semaphore_handle); } + #else EventGroupHandle_t event_group_handle = (EventGroupHandle_t) EventGroupHandle; @@ -142,6 +477,7 @@ void r_ble_wake_up_task_from_isr (void * EventGroupHandle) xSemaphoreGiveFromISR(semaphore_handle, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } + #else /* Event flag notifications */ diff --git a/ra/fsp/src/r_cac/r_cac.c b/ra/fsp/src/r_cac/r_cac.c index d346f3133..6d18c4867 100644 --- a/ra/fsp/src/r_cac/r_cac.c +++ b/ra/fsp/src/r_cac/r_cac.c @@ -226,7 +226,7 @@ fsp_err_t R_CAC_StopMeasurement (cac_ctrl_t * const p_ctrl) * @retval FSP_ERR_ASSERTION An argument is NULL. * @retval FSP_ERR_NOT_OPEN R_CAC_Open() has not been successfully called. **********************************************************************************************************************/ -fsp_err_t R_CAC_Read (cac_ctrl_t * const p_ctrl, uint16_t * const p_counter) +fsp_err_t R_CAC_Read (cac_ctrl_t * const p_ctrl, uint32_t * const p_counter) { #if (CAC_CFG_PARAM_CHECKING_ENABLE == 1) cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; diff --git a/ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 b/ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 deleted file mode 100644 index d36530594..000000000 --- a/ra/fsp/src/r_canfd/.module_descriptions/Renesas##HAL Drivers##all##{module_variant}####4.6.0.xml.j2 +++ /dev/null @@ -1,838 +0,0 @@ -{% if 'r_canfd' == module_variant %} - {% set num_rx_fifos=8 %} - {% set num_common_fifos=6 %} -{% else %} - {% set num_rx_fifos=2 %} - {% set num_common_fifos=1 %} -{% endif %} -{% macro deref_id(id_prefix,name) %}${{ '{' + id_prefix + '.driver.' + id_name() + '.' + name + '}' }}{% endmacro %} -{% macro id_name() %}{%- if 'r_canfd' == module_variant %}canfd{%- else %}canfdlite{%- endif %}{% endmacro %} -{% macro rx_fifo_properties(id_prefix, index) %} - - - - - - - - - -{% endmacro %} -{% macro common_fifo_properties(id_prefix, index) %} - - - - - - - - - - - - - - - - - - testInteger("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txmb{{ '}' }}") - && (("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txmb{{ '}' }}" >= 0) - &&("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txmb{{ '}' }}" <= 31)) - - - - - testInteger("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txdelay{{ '}' }}") - && (("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txdelay{{ '}' }}" >= 0) - &&("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txdelay{{ '}' }}" <= 255)) - - - - - - -{% endmacro %} -{% macro common_fifo_config(id_prefix, num_common_fifos) -%} - {%- for index in range(num_common_fifos) %} - {%- filter e %} -#define CANFD_CFG_COMMONFIFO{{ index }} ((${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.enable} << R_CANFD_CFDCFCC_CFE_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.rxi_enable} << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txi_enable} << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.payload} << R_CANFD_CFDCFCC_CFPLS_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.mode} << R_CANFD_CFDCFCC_CFM_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.interval_source} << R_CANFD_CFDCFCC_CFITSS_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.refclk_resolution} << R_CANFD_CFDCFCC_CFITR_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.int_mode} << R_CANFD_CFDCFCC_CFIM_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.int_threshold} << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txmb} << R_CANFD_CFDCFCC_CFTML_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.depth} << R_CANFD_CFDCFCC_CFDC_Pos) | \ - (${{'{'}}{{ id_prefix }}.driver.{{ id_name() }}.commonfifo.{{ index }}.txdelay} << R_CANFD_CFDCFCC_CFITT_Pos)){{'\r\n'}} - {%- endfilter %} - {%- endfor %} -{%- endmacro %} -{% macro global_config(id_prefix, num_fifos, num_common_fifos) %} - - {% filter js_eval %}{% include "ram_usage_export.js.j2" with context %}{% endfilter -%} - - - - - - - - - - - - testInteger("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}") && (("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}" >= 0) && ("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}" <= 32)) - - - -{% for index in range(num_fifos) %}{{ rx_fifo_properties(id_prefix,index) }}{% endfor %} -{% for index in range(num_common_fifos) %}{{ common_fifo_properties(id_prefix, index) }}{% endfor %} -{% endmacro %} -{% macro global_config_constraints(id_prefix, num_fifos, num_common_fifos) %} - {% filter js_eval %}{% include "ram_usage_constraint.js.j2" with context %}{% endfilter -%} -{%- if 'r_canfd' == module_variant %} - - ("${interface.mcu.feature_set.b}" > "0") || - (("{{deref_id(id_prefix,'rxmb.size')}}" === "{{id_prefix}}.driver.{{ id_name() }}.rxmb.size.8") &&{% for fifo_number in range(num_fifos - 1) %} - ("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.payload')}}" === "enum.driver.canfd.fifo.payload.8") &&{% endfor %} - ("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.payload')}}" === "enum.driver.canfd.fifo.payload.8")) - - - ("${interface.mcu.feature_set.b}" > "0") || - (("{{deref_id(id_prefix,'fd.overflow')}}" === "{{id_prefix}}.driver.{{ id_name() }}.fd.overflow.reject") && - (!testOption("{{deref_id(id_prefix,'global_err.sources')}}", "{{id_prefix}}.driver.{{ id_name() }}.global_err.sources.overflow"))) - -{%- endif %} -{%- endmacro %} - - - - - - - - - - - - - - - - -